research-article

Standby and dynamic power minimization using enhanced hybrid power gating structure for deep-submicron CMOS VLSI

Authors:

J. Jeba Johannah,

Maria KalavathyAuthors Info & Claims

Microelectronics Journal, Volume 62, Issue C

Pages 137 - 145

https://doi.org/10.1016/j.mejo.2017.02.003

Published: 01 April 2017 Publication History

Abstract

Scaling down of CMOS Technology reduces supply voltage which helps evade device botch caused by high electric fields in the conducting channel under the gate and gate oxide. Voltage scaling lessens circuit power consumption but increases delay of logic gates badly and the performance is degraded to a large extent in deep submicron CMOS VLSI circuits. In order to achieve good performance, the delay of logic gates has to be decreased. Circuits for trimming down of leakage power in sub-micron technologies also increase the dynamic power to a large extent. In this paper, a novel hybrid MTCMOS technique is proposed to reduce the enormous delay in gates due to sleep transistors; also, static power consumption is reduced without much affecting the dynamic power consumption of the circuit. For the 16-bit Ripple Carry Adder, the proposed technique can save up to 76.8% of static power consumption and 55.5% of dynamic power consumption also. Display Omitted Addition of high threshold voltage or low threshold voltage transistor(s) in gates.Enhanced performance of gates in deep sub-micron CMOS.Very high static power minimization in Nano technology.Full output voltage swing.

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Cited By

Kajal Sharma V(2021)Design and Simulation for NBTI Aware Logic GatesWireless Personal Communications: An International Journal10.1007/s11277-021-08522-z120:2(1525-1542)Online publication date: 1-Sep-2021
https://dl.acm.org/doi/10.1007/s11277-021-08522-z
Mushtaq USharma V(2021)Performance analysis for reliable nanoscaled FinFET logic circuitsAnalog Integrated Circuits and Signal Processing10.1007/s10470-020-01765-z107:3(671-682)Online publication date: 1-Jun-2021
https://dl.acm.org/doi/10.1007/s10470-020-01765-z
Kilani DMohammad BAlhawari MSaleh HIsmail M(2019)Analysis and characterization of leakage reduction methodologies for stacking, body biasing and DLS in 65 nm CMOS technologyAnalog Integrated Circuits and Signal Processing10.1007/s10470-019-01520-z102:1(1-8)Online publication date: 10-Aug-2019
https://dl.acm.org/doi/10.1007/s10470-019-01520-z

Standby and dynamic power minimization using enhanced hybrid power gating structure for deep-submicron CMOS VLSI
1. Hardware
2. Networks
  1. Network types
    1. Ad hoc networks

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Published In

cover image Microelectronics Journal

Microelectronics Journal Volume 62, Issue C

April 2017

146 pages

ISSN:0026-2692

Issue’s Table of Contents

Copyright © Elsevier Ltd.

Publisher

Elsevier Science Publishers B. V.

Netherlands

Publication History

Published: 01 April 2017

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Cited By

Kajal Sharma V(2021)Design and Simulation for NBTI Aware Logic GatesWireless Personal Communications: An International Journal10.1007/s11277-021-08522-z120:2(1525-1542)Online publication date: 1-Sep-2021
https://dl.acm.org/doi/10.1007/s11277-021-08522-z
Mushtaq USharma V(2021)Performance analysis for reliable nanoscaled FinFET logic circuitsAnalog Integrated Circuits and Signal Processing10.1007/s10470-020-01765-z107:3(671-682)Online publication date: 1-Jun-2021
https://dl.acm.org/doi/10.1007/s10470-020-01765-z
Kilani DMohammad BAlhawari MSaleh HIsmail M(2019)Analysis and characterization of leakage reduction methodologies for stacking, body biasing and DLS in 65 nm CMOS technologyAnalog Integrated Circuits and Signal Processing10.1007/s10470-019-01520-z102:1(1-8)Online publication date: 10-Aug-2019
https://dl.acm.org/doi/10.1007/s10470-019-01520-z

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