article

A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms

Authors:

Abbas Dehghani,

Kamal JamshidiAuthors Info & Claims

The Journal of Supercomputing, Volume 71, Issue 8

Pages 3116 - 3148

https://doi.org/10.1007/s11227-015-1430-z

Published: 01 August 2015 Publication History

Abstract

Wireless network on chip (WNoC) is a promising new solution for overcoming the constraints in the traditional electrical interconnections. However, the occurrence of faults has become more prevalent because of the continuous shrinkage of CMOS technology and integration of wireless technology in such complex circuits. This can lead to formation of faulty regions on chip, where the probability of the entire system failure increases in a significant manner. This issue is not addressed in the previous works on WNoC systems. In this article, a fault-tolerant hierarchical hybrid WNoC architecture is proposed. First, an innovative strategy is proposed for solving the problem of fault-tolerant wireless routers placement in standard mesh networks inspired by node-disjoint communication structures. Next, efficient fault-tolerant communication protocols are presented for applying this structure. The experimental results demonstrate the robustness of this proposed architecture in the presence of various fault regions under different traffic patterns.

References

[1]

Benini L, De Micheli G (2002) Networks on chip: a new paradigm for systems on chip design. Proc 2002 Des Autom Test Eur Conf Exhib IEEE Comput Soc:418---419.

[2]

Kaplan AB (2008) Architectural integration of RF-interconnect to enhance on-chip communication for Many-Core Chip Multiprocessors. Ph.D. diss., University of California Los Angeles

[3]

Shacham A, Bergman K, Carloni LP (2008) Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors. IEEE Trans Comput 57:1246---1260.

Digital Library

[4]

Deb S, Ganguly A, Pande PP et al (2012) Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges. IEEE J Emerg Sel Top Circuits Syst 2:228---239.

[5]

Ogras UY, Marculescu R (2006) "It's a small world after all": NoC performance optimization via long-range link insertion. IEEE Trans Very Large Scale Integr Syst 14:693---706.

Digital Library

[6]

Sabbaghi-Nadooshan R, Modarressi M, Sarbazi-Azad H (2010) The 2D digraph-based NoCs: attractive alternatives to the 2D mesh NoCs. J Supercomput 59:1---21.

[7]

ITRS Edition (2011) . http://www.itrs.net/Links/2011ITRS/Home2011.htm. Accessed 10 Oct 2014

[8]

Ganguly A, Chang K, Deb S et al (2011) Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems. IEEE Trans Comput 60:1485---1502.

Digital Library

[9]

Deb S, Chang K, Yu X et al (2013) Design of an Energy-Efficient CMOS-Compatible NoC Architecture with Millimeter-Wave Wireless Interconnects. IEEE Trans Comput 62:2382---2396.

Digital Library

[10]

Chang K, Deb S, Ganguly A et al (2012) Performance evaluation and design trade-offs for wireless network-on-chip architectures. ACM J Emerg Technol Comput Syst 8:1---25.

Digital Library

[11]

Hu W-H, Wang C, Bagherzadeh N (2014) Design and analysis of a mesh-based wireless network-on-chip. J Supercomput.

[12]

Matolak D, Kodi A, Kaya S et al (2012) Wireless networks-on-chips: architecture, wireless channel, and devices. IEEE Wirel Commun 19:58---65.

[13]

More A, Taskin B (2012) A unified design methodology for a hybrid wireless 2-D NoC. 2012 IEEE Int Symp Circuits Syst IEEE: 640---643.

[14]

Chang K-C (2009) Reliable network-on-chip design for multi-core system-on-chip. J Supercomput 55:86---102.

[15]

Radetzki M, Feng C, Zhao X, Jantsch A (2013) Methods for fault tolerance in networks-on-chip. ACM Comput Surv 46:1---38.

Digital Library

[16]

Wettin P, Pande PP, Heo D et al (2013) Design space exploration for reliable mm-wave wireless NoC architectures. IEEE 24th Int Conf Appl Syst Archit Process IEEE:79---82.

[17]

Ganguly A, Pande P, Belzer B, Nojeh A (2011) A unified error control coding scheme to enhance the reliability of a hybrid wireless network-on-chip. IEEE Int Symp Defect Fault Toler VLSI Nanotechnol Syst IEEE:277---285.

[18]

Wettin P, Vidapalapati A, Gangul A, Pande PP (2013) Complex network-enabled robust wireless network-on-chip architectures. ACM J Emerg Technol Comput Syst 9:1---19.

Digital Library

[19]

Nojeh A, Pande P, Ganguly A et al (2008) Reliability of wireless on-chip interconnects based on carbon nanotube antennas. IEEE 14th Int Mix Sensors Syst Test Work IEEE:1---6.

[20]

Vijayakumaran V, Yuvaraj MP, Mansoor N et al (2014) CDMA Enabled Wireless Network-on-Chip. ACM J Emerg Technol Comput Syst 10:1---20.

Digital Library

[21]

Lloyd EL (2010) Fault-Tolerant Relay Node Placement in Heterogeneous Wireless Sensor Networks. IEEE Trans Mob Comput 9:643---656.

Digital Library

[22]

Chen C-W, Chung C-P (2005) Designing a disjoint paths interconnection network with fault tolerance and collision solving. J Supercomput 34:63---80.

Digital Library

[23]

Furhad MH, Kim J-M (2014) A shortly connected mesh topology for high performance and energy efficient network-on-chip architectures. J Supercomput 69:766---792.

Digital Library

[24]

Zhao D, Wang Y (2008) MTNet: Design of a Wireless Test Framework for Heterogeneous Nanometer Systems-on-Chip. IEEE Trans Very Large Scale Integr Syst 16:1046---1057.

[25]

Zhao D, Wang Y, Li J, Kikkawa T (2011) Design of multi-channel wireless NoC to improve on-chip communication capacity!. Proc Fifth ACM/IEEE Int Symp Netw Chip ACM:177---184

[26]

Zhao D, Wang Y (2008) SD-MAC: Design and Synthesis of a Hardware-Efficient Collision-Free QoS-Aware MAC Protocol for Wireless Network-on-Chip. IEEE Trans Comput 57:1230---1245.

Digital Library

[27]

Deb S, Ganguly A, Chang K et al (2010) Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnects. In: ASAP 2010---21st IEEE Int. Conf. Appl. Syst. Archit. Process. IEEE, pp 73---80.

[28]

Lee S-B, Zhang L, Cong J et al (2009) A scalable micro wireless interconnect structure for CMPs. In: Proc. 15th Annu. Int. Conf. Mob. Comput. Netw.--MobiCom '09. ACM Press, New York.

[29]

Kempa K, Rybczynski J, Huang Z et al (2007) Carbon Nanotubes as Optical Antennae. Adv Mater 19:421---426.

[30]

West DB (2001) Introduction to graph theory. Prentice hall, Upper Saddle River

[31]

Boppana RV, Chalasani S (1995) Fault-tolerant wormhole routing algorithms for mesh networks. IEEE Trans Comput 44:848---864.

Digital Library

[32]

Duato J, Yalamanchili S, Ni LM (2003) Interconnection networks: an engineering approach. Morgan Kaufmann Publishers Inc, USA

[33]

Zhang Z, Greiner A, Taktak S (2008) A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip. Proc Des Autom Conf:441---446.

[34]

Manevich R, Polishuk L, Cidon I, Kolodny A (2014) Designing single-cycle long links in hierarchical NoCs. Microprocess Microsyst 38:814---825.

Digital Library

[35]

Varga A (2001) The OMNeT++ discrete event simulation system. Proc. Eur. Simul. Multiconference. sn. p 185

[36]

Ben-Itzhak Y, Zahavi E, Cidon I, Kolodny A (2012) HNOCS: modular open-source simulator for Heterogeneous NoCs. Int Conf Embed Comput Syst IEEE. pp 51---57.

[37]

Koohi S, Hessabi S (2011) Hierarchical opto-electrical on-chip network for future multiprocessor architectures. J Syst Archit 57:4---23.

Digital Library

[38]

Pande PP, Grecu C, Jones M et al (2005) Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans Comput 54:1025---1040.

Digital Library

[39]

Zhang Y, Hu X, Deutsch A et al (2011) Prediction and comparison of high-performance on-chip global interconnection. IEEE Trans Very Large Scale Integr Syst 19:1154---1166.

[40]

Kahng a. B, Li BL Bin, Peh L-SPL-S, Samadi K (2009) ORION 2.0: A fast and accurate NoCapower and area model for early-stage design space exploration. 2009 Des Autom Test Eur Conf Exhib .pp 423---428.

[41]

Hayenga M, Johnson DR, Lipasti M (2010) Pitfalls of orion-based simulation. ORION 35:0---40

[42]

Sun C, Chen C-HO, Kurian G, et al. (2012) DSENT--a Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling. 2012 IEEE/ACM Sixth Int. Symp. Networks-on-Chip. IEEE. pp 201---210.

Digital Library

[43]

PTM--Latest models. http://ptm.asu.edu/latest.html. Accessed 10 Oct 2014

[44]

Francis RM (2009) Exploring networks-on-chip for FPGAs. Ph.D. diss., University of Cambridge

[45]

Banerjee N, Vellanki P, Chatha KS (2004) A power and performance model for network-on-chip architectures. Proc Des Autom Test Eur Conf Exhib IEEE Comput Soc:1250---1255.

Cited By

Wang QOuyang YLu YLiang HZhu D(2021)Neural Network-based Online Fault Diagnosis in Wireless-NoC SystemsJournal of Electronic Testing: Theory and Applications10.1007/s10836-021-05966-w37:4(545-559)Online publication date: 1-Aug-2021
https://dl.acm.org/doi/10.1007/s10836-021-05966-w
Dehghani A(2020)A design flow for an optimized congestion-aware application-specific wireless network-on-chip architectureFuture Generation Computer Systems10.1016/j.future.2020.01.001106:C(234-249)Online publication date: 1-May-2020
https://dl.acm.org/doi/10.1016/j.future.2020.01.001
Mortazavi SAkbar RSafaei FRezaei A(2019)A fault-tolerant and congestion-aware architecture for wireless networks-on-chipWireless Networks10.1007/s11276-019-01962-325:6(3675-3687)Online publication date: 20-Jul-2019
https://dl.acm.org/doi/10.1007/s11276-019-01962-3
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A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms

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Published In

cover image The Journal of Supercomputing

The Journal of Supercomputing Volume 71, Issue 8

August 2015

431 pages

ISSN:0920-8542

Issue’s Table of Contents

Copyright © Copyright © 2015 Springer Science+Business Media New York.

Publisher

Kluwer Academic Publishers

United States

Publication History

Published: 01 August 2015

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Cited By

Wang QOuyang YLu YLiang HZhu D(2021)Neural Network-based Online Fault Diagnosis in Wireless-NoC SystemsJournal of Electronic Testing: Theory and Applications10.1007/s10836-021-05966-w37:4(545-559)Online publication date: 1-Aug-2021
https://dl.acm.org/doi/10.1007/s10836-021-05966-w
Dehghani A(2020)A design flow for an optimized congestion-aware application-specific wireless network-on-chip architectureFuture Generation Computer Systems10.1016/j.future.2020.01.001106:C(234-249)Online publication date: 1-May-2020
https://dl.acm.org/doi/10.1016/j.future.2020.01.001
Mortazavi SAkbar RSafaei FRezaei A(2019)A fault-tolerant and congestion-aware architecture for wireless networks-on-chipWireless Networks10.1007/s11276-019-01962-325:6(3675-3687)Online publication date: 20-Jul-2019
https://dl.acm.org/doi/10.1007/s11276-019-01962-3
Yazdanpanah FAfsharmazayejani RAlaei MRezaei ADaneshtalab M(2019)An energy-efficient partition-based XYZ-planar routing algorithm for a wireless network-on-chipThe Journal of Supercomputing10.1007/s11227-018-2617-x75:2(837-861)Online publication date: 1-Feb-2019
https://dl.acm.org/doi/10.1007/s11227-018-2617-x
Xie PGu HWang KYu XMa S(2019)Mesh-of-TorusThe Journal of Supercomputing10.1007/s11227-018-2610-475:1(255-271)Online publication date: 1-Jan-2019
https://dl.acm.org/doi/10.1007/s11227-018-2610-4

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