Search Results (310)

Silicon carbide (SiC) metal oxide semiconductor field-effect transistors (MOSFETs) are a future trend in traction inverters in electric vehicles (EVs), and their thermal safety is crucial. Temperature-sensitive electrical parameters’ (TSEPs) indirect detection normally requires additional circuits, which can interfere with the system and increase costs, thereby limiting applications. Therefore, there is still a lack of cost-effective and sensorless thermal monitoring techniques. This paper proposes a high-efficiency datasheet-driven method for sensorless estimation utilizing the third-quadrant characteristics of MOSFETs. Without changing the existing hardware, the closure degree of MOS channels is controlled through a dual-gate bias (DGB) strategy to achieve reverse conduction in different patterns with body diodes. This method introduces a MOSFET operating current that TSEPs are equally sensitive to into the two-argument function, improving the complexity and accuracy. A two-stage current pulse is used to decouple the motor effect in various conduction modes, and the TSEP-combined temperature function is built dynamically by substituting the currents. Then, the junction temperature is estimated by the measured bus voltage and current. Its effectiveness was verified through spice model simulation and a test bench with a three-phase inverter. The average relative estimation error of the proposed method is below 7.2% in centigrade. Full article

The short-circuit (SC) robustness of SiC MOSFETs is critical for high-power applications, yet 1.2 kV devices often struggle to meet the industry-standard SC withstand time (SCWT) under practical operating conditions. Despite growing interest in higher voltage classes, no prior study has systematically evaluated the SC performance of 1.7 kV SiC MOSFETs. This study provides the first comprehensive evaluation of commercially available 1.7 kV SiC MOSFETs, analyzing their SC performance under varying electrical stress conditions. Results indicate a clear trade-off between SC withstand time (SCWT) and drain-source voltage (V_DS), with SCWT decreasing from 32 µs at 400 V to 4 µs at 1100 V. Under 600 V, a condition representative of practical use cases in many high-voltage applications, the devices achieved an SCWT of 12 µs, exceeding the industry-standard 10 µs benchmark—a threshold often unmet by 1.2 kV devices under similar conditions. Failure analysis revealed gate dielectric breakdown as the dominant failure mode at V_DS ≤ 600 V, while thermal runaway was observed at higher voltages (V_DS = 800 V and 1100 V). These findings underscore the critical importance of robust gate drive designs and effective thermal management. By surpassing the shortcomings of lower voltage classes, 1.7 kV SiC MOSFETs can be a more reliable, and efficient choice for operating at higher voltages in next-generation power systems. Full article

In medium- and high-power-density applications, silicon carbide (SiC) metal-oxide semiconductor field effect transistors (MOSFETs) are often connected in parallel increasing the current capability. However, the current sharing of paralleled SiC MOSFETs is affected by the mismatched technical parameters of devices and the deviated power circuit parasitic inductances, even if power devices are controlled by a single gate driver. This leads to unevenly distributed power losses causing different stress between SiC MOSFETs. As a result, unbalanced current sharing increases the probability of severe power switch(es) and system failures. For over a decade, the current imbalance issue between parallel-connected SiC MOSFETs has concerned the scientific community, and many methods and techniques have been proposed. However, most of these solutions are impossible to realize without the necessity of screening power devices to measure their technical parameters. Consequently, system costs significantly increase due to the expensive equipment for screening SiC MOSFETs. Also, transient current imbalance is the main concern of most papers, without addressing static imbalance. In this paper, an innovative approach is proposed, capable of suppressing both static and transient current imbalance between paralleled SiC MOSFETs, under both symmetrical and asymmetrical layouts, through an improved active gate driver and without the requirement for any power device screening process. Additionally, the proposed solution employs a self-sustaining algorithmic approach utilizing current sensors and a field-programmable gate array (FPGA). The functionality of the proposed solution is verified through experimental tests, achieving current imbalance suppression between two paralleled SiC MOSFETs, actively and autonomously. Full article

Split Gate SiC MOSFETs (SG-MOSFETs) have been demonstrated to exhibit excellent power dissipation at high operating frequencies due to their low specific reverse transfer capacitance (C_rss,sp); however, there are several reliability issues of SG-MOSFETs, including electric field crowding at the gate oxide and insufficient short-circuit (SC) robustness. In this paper, we propose a device structure to enhance the short-circuit withstand time (SCWT) of 1.2 kV SG-MOSFETs. The proposed P-shielded SG-MOSFETs (PSG-MOSFETs) feature a P-shielding region that expands the depletion region within the JFET region under both blocking mode and SC conditions. Compared to the conventional structure, this reduces the maximum electric field in the gate oxide, enabling a higher doping concentration in the JFET region, which can reduce the specific on-resistance (R_on,sp) to minimize power dissipation during device operation. The SC robustness of PSG-MOSFETs, with an R_on,sp identical to those of SG-MOSFETs, was investigated by adjusting the width of the P-shielding region (W_P). Furthermore, the C_rss,sp of PSG-MOSFETs was compared with that of SG-MOSFETs to analyze the relationship between the W_P and high-frequency figure of merit (HF-FOM), defined as R_on,sp × C_rss,sp. These results demonstrated that the PSG-MOSFET achieved an enhanced SC robustness and HF-FOM in comparison to the SG-MOSFET. Thus, the proposed PSG-MOSFET is a highly suitable candidate for high-frequency and reliable applications. Full article

The SiC MOSFET with an integrated SBD (SBD-MOSFET) exhibits excellent performance in power electronics. However, the static and dynamic characteristics of this device are influenced by a multitude of parameters, and traditional TCAD simulation methods are often characterized by their complexity. Due to the increasing research on neural networks in recent years, such as the application of neural networks to the prediction of GaN JBS and Finfet devices, this paper considers the application of neural networks to the performance prediction of SiC MOSFET devices with an integrated SBD. This study introduces a novel approach utilizing neural network machine learning to predict the static and dynamic characteristics of the SBD-MOSFET. In this research, SBD-MOSFET devices are modeled and simulated using Sentaurus TCAD(2017) software, resulting in the generation of 625 sets of device structure and sample data, which serve as the sample set for the neural network. These input variables are then fed into the neural network for prediction. The findings indicate that the mean square error (MSE) values for the threshold voltage (Vth), breakdown voltage (BV), specific on-resistance (R_on), and total switching power dissipation (E) are 0.0051, 0.0031, 0.0065, and 0.0220, respectively, demonstrating a high degree of accuracy in the predicted values. Meanwhile, in the comparison of convolutional neural networks and machine learning, the CNN accuracy is much higher than the machine learning methods. This method of predicting device performance via neural networks offers a rapid means of designing SBD-MOSFETs with specified performance targets, thereby presenting significant advantages in accelerating research on SBD-MOSFET performance prediction. Full article

This paper examines the current state of Home Energy Management Systems (HEMSs), highlighting the key role of the single-phase bidirectional rectifier (SPBR). It provides a detailed design process for the converter used in HEMSs, with a particular focus on the bidirectional charge and discharge of high-voltage batteries. The converter’s operating conditions were determined through a comprehensive evaluation of its components, which were designed and assessed to enable accurate power loss calculations. This approach ensures proper component sizing and a clear understanding of the converter’s efficiency. A specialized electronic control circuit manages two operating modes of the converter: a boost rectifier with power factor correction (PFC) and a sinusoidal pulse width modulation (SPWM) inverter. To validate the design, a 7.4 kW prototype was developed using silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs). The prototype achieved a peak efficiency of nearly 98% in both modes, with a unity power factor (PF) and total harmonic distortion (THD) below 7% at full power. Full article

Arguably, SiC technology is the most rapidly expanding IC manufacturing technology driven mostly by the aggressive roadmap for battery electric vehicle penetration and also industrial high-voltage/high-power applications. This paper provides a comprehensive overview of the state of the art of SiC technology focusing on the challenges starting from the difficult and lengthy SiC substrate growth all the way to the complex MOSFET assembly processes. We focus on the differentiation from the established Si manufacturing processes and provide a comprehensive list of references as well as a brief description of our own research into the key manufacturing processes in this technology. We also present a SiC technology and product roadmap. Full article

A novel cell topology for a vertical 1200 V SiC planar double-implanted MOSFET (DMOSFET) is proposed in this work. Based on the conventional linear cell topology and the calibrated two-dimensional (2D) technology computer-aided design (TCAD) model parameters, a novel cell topology with the insertion of P+ body implanted regions over a fractional part of the channel and junction field effect transistor (JFET) regions was designed and optimized to achieve a low high-frequency figure of merit (HF-FOM, R_on × C_gd). Utilizing three-dimensional (3D) TCAD simulations, the new proposed cell topology with optimized selected structure parameters exhibits an HF-FOM of 328.748 mΩ·pF, which is 10.02% lower than the conventional linear topology. It also shows an improvement in the switching performance, with an 11.73% reduction in switching loss. Moreover, the impact of source ohmic contact resistivity on the performance of the proposed cell topology was highlighted, indicating the dependency of the source ohmic contact resistivity on the switching performance. This research provides a new perspective for enhancing the switching performance of SiC MOSFETs in high-frequency applications, considering practical factors such as contact resistivity. Full article

In a converter of actual working condition, the change in the current and voltage of the power device will cause the junction temperature to fluctuate greatly. This device is subjected to high thermal stress due to the change in the junction temperature. Therefore, it is necessary to adopt junction temperature control to reduce or smooth the junction temperature fluctuation, so as to realize the junction temperature control and improve the reliability of the device. At present, the methods for the junction temperature control of power devices have certain limitations and there are few active thermal management methods proposed for SiC device characteristics. In this paper, a method for realizing the smooth control of the junction temperature of a SiC device based on the conduction loss adjustment of the body diode for the SiC device has been proposed, considering that the conduction loss of the body diode is greater than the conduction loss of the SiC MOSFET. The conduction time of SiC MOSFET body diode was adjusted. By adjusting the conduction loss of the SiC MOSFET device, the fluctuation range of the junction temperature of the SiC MOSFET device was controlled, the smooth control of the junction temperature of the SiC device was realized, and the thermal stress of the device was reduced. Full article

A novel planar silicon carbide (SiC) MOSFET integrated with both MOS-channel diode (MCD) and junction barrier Schottky diode (JBS) on the same chip (MCD-JBSFET) is proposed and investigated through Technology Computer-Aided Design (TCAD) simulations in this paper. The proposed device features the lowest turn-on voltage and the best current conduction capability under the reverse-biased conditions, allowing it to achieve the same reverse conduction capability with fewer MCDs compared to conventional MOSFET with MCD structures (MCDFET). This reduction in the number of MCDs enables more channels to operate under forward-biased conditions, thereby improving power density. Compared to a conventional MOSFET integrated with JBS structure (JBSFET), the reverse current in the MCD-JBSFET flows through both the MCD and JBS, which suppresses the peak lattice temperature at Schottky contact and enhances the high-temperature robustness, especially under surge current conditions. In addition, the split-gate structure in the proposed structure optimizes the reverse capacitance and the figure of merit R_on,sp × Q_g by factors of 0.65 and 2.15, respectively. Finally, the switching losses are reduced by 40.2%, indicating the suitability of MCD-JBSFET for high-frequency and high-current applications. Full article

Accurate modeling of the switching transients of SiC MOSFETs is essential for overvoltage evaluation, EMI prediction, and other critical applications. Due to the fast switching speed, the switching transients of SiC MOSFETs are highly sensitive to parasitic parameters and nonlinear components, making precise modeling challenging. This paper proposes a hybrid model for SiC MOSFET, in which the analytical model is treated as the basis to provide the fundamental waveforms (knowledge-driven), while the neural network (NN) is utilized to fit the high-order and nonlinear features (data-driven). An NN training method with augmented data is proposed to minimize the training datasets. Verification results show that, even though the NN is trained with the data from a single operating condition, the model can accurately predict switching transients of other operating conditions. The proposed methodology has the potential to co-work with the “black-box” or “grey-box” models to enhance the model accuracy. Full article

This work consists of the analysis and design of a LC series resonant inverter with reactive element control for induction heating hardening applications. This novel method uses a current-controlled variable transformer (VT) to control the reflected inductance of the inductor in the resonant, and a magnetic energy recovery switch (MERS) to vary the influence of the capacitor as a reactive power compensation element. This converter topology allows quality factor (Q) or operating frequency (fsw) to be adjusted, making it possible to harden workpieces of different geometries and materials with a single converter. In the article, the design of both elements will be studied and tested. Experimental results were carried out with a 10 kW induction heating inverter prototype, with a frequency range of 60 kHz to 100 kHz and a quality factor of 6 to 10, measuring efficiencies above 95%. Full article

Power devices in series are low-voltage power devices used in medium- and high-voltage applications in a more direct program. However, when power devices in series are used, because of their electrical performance parameters or external circuit conditions, there are unique short-circuit voltage imbalances, a serious threat to the safety of the device. The article first summarizes the research status and characteristics of the four models of SiC MOSFETs based on the domestic and international research on the models of SiC MOSFETs in recent years; second, the voltage balancing technology of series-connected SiC MOSFETs is sorted out and summarized, and then the driving circuits of SiC MOSFETs are sorted out and summarized. Again, several voltage balancing techniques reviewed are compared in six different aspects: cost, modularity, complexity, speed of voltage balancing, losses, and effectiveness of voltage balancing. Finally, an outlook of voltage balancing techniques for series SiC MOSFETs is provided. Full article

This work investigates the performance of state-of-the-art non-commercial 6.5 kV Silicon Carbide (SiC) PiN and Junction Barrier Schottky (JBS) diodes in hybrid (Si IGBT with SiC diode) and full SiC (SiC MOSFET with SiC diode) switch topologies. The static and dynamic performance has been systematically evaluated at distinct temperatures, gate resistances and currents for each configuration. The SiC PiN diode presented higher current density capability and lower leakage current density than the JBS diode. Moreover, in most cases, the SiC PiN diode-based topologies demonstrated slightly higher total switching losses compared to the SiC JBS diode-based equivalent configurations. A loadability analysis in a three-level NPC converter is presented to evaluate the potential of each configuration in a converter application. The SiC PiN technology presented a 25% power extension compared to the SiC JBS technology with similar efficiency at typical industrial drives switching frequency operation when comparing same-active-area diode technologies. Finally, a long-term reliability test (H3TRB) is presented to demonstrate the SiC PiN diode technology’s potential for operation in harsh environments. Such characteristics show the advantage of the 6.5 kV SiC PiN diode when a high current density (>100 A/cm²), high efficiency and reliability are required. Full article

This work investigates the gate oxide reliability of commercial 1.2 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with planar and trench gate structures. The performance of threshold voltage (Vth) and gate leakage current (Igss) in SiC MOSFETs is evaluated under positive and negative gate voltage stress. The oxide lifetimes of SiC planar and trench MOSFETs at 150 °C are measured using constant voltage Time-Dependent Dielectric Breakdown (TDDB) testing. From the test results, it is found that electron trapping and hole trapping in SiO2 caused by oxide electric field (Eox) stress affect the Vth of SiC MOSFETs. The saturation and turnaround behavior of the Vth shift during positive and negative gate voltage stresses indicates that the influence of charge trapping in the gate oxide varies with stress time. The Igss under positive and negative gate voltages depends on the tunneling barrier height for electrons and holes, respectively, which can be calculated using the Fowler–Nordheim (FN) tunneling mechanism. Moreover, the presence of near-interface traps (NITs) affects the barrier height for holes under negative gate voltages. The behavior of Vth shift and Igss under high-temperature gate bias reflects the charge trapping occurring in different regions of the gate oxide. In addition, compared to SiC planar MOSFETs, SiC trench MOSFETs with thicker gate oxide tend to exhibit higher lifetimes in TDDB tests. Full article