Flip chip

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Intel Mobile Celeron in a flip-chip BGA package (FCBGA-479); the flip chip, BGA substrate is dark yellow, and the silicon die appears dark blue Celeron mobile.jpg
Intel Mobile Celeron in a flip-chip BGA package (FCBGA-479); the flip chip, BGA substrate is dark yellow, and the silicon die appears dark blue
Underside of a die from a flip chip package, the top metal layer on the IC die or top metallization layer, and metallized pads for flip chip mounting are visible AMD@7nm(12nmIOD)@Zen2@Rome@EPYC 7702 ES@2S1404E2VJUG5 BB ES DSCx6 IOD top metal@5x.jpg
Underside of a die from a flip chip package, the top metal layer on the IC die or top metallization layer, and metallized pads for flip chip mounting are visible

Flip chip, also known as controlled collapse chip connection or its abbreviation, C4, [1] is a method for interconnecting dies such as semiconductor devices, IC chips, integrated passive devices and microelectromechanical systems (MEMS), to external circuitry with solder bumps that have been deposited onto the chip pads. The technique was developed by General Electric's Light Military Electronics Department, Utica, New York. [2] The solder bumps are deposited on the chip pads on the top side of the wafer during the final wafer processing step. In order to mount the chip to external circuitry (e.g., a circuit board or another chip or wafer), it is flipped over so that its top side faces down, and aligned so that its pads align with matching pads on the external circuit, and then the solder is reflowed to complete the interconnect. This is in contrast to wire bonding, in which the chip is mounted upright and fine wires are welded onto the chip pads and lead frame contacts to interconnect the chip pads to external circuitry. [3]

Contents

Process steps

  1. Integrated circuits are created on the wafer.
  2. Pads are metallized on the surface of the chips.
  3. A solder ball is deposited on each of the pads, in a process called wafer bumping
  4. Chips are cut.
  5. Chips are flipped and positioned so that the solder balls are facing the connectors on the external circuitry.
  6. Solder balls are then remelted (typically using hot air reflow).
  7. Mounted chip is "underfilled" using a (capillary, shown here) electrically-insulating adhesive. [4] [5]

Comparison of mounting technologies

Wire bonding/thermosonic bonding

The interconnections in a power package are made using thick aluminium wires (250 to 400 mm) wedge-bonded Wirebonding Workaround.svg
The interconnections in a power package are made using thick aluminium wires (250 to 400 μm) wedge-bonded

In typical semiconductor fabrication systems, chips are built up in large numbers on a single large wafer of semiconductor material, typically silicon. The individual chips are patterned with small pads of metal near their edges that serve as the connections to an eventual mechanical carrier. The chips are then cut out of the wafer and attached to their carriers, typically via wire bonding such as thermosonic bonding. These wires eventually lead to pins on the outside of the carriers, which are attached to the rest of the circuitry making up the electronic system.

Flip chip

Side-view schematic of a typical flip chip mounting Flip chip side-view.svg
Side-view schematic of a typical flip chip mounting

Processing a flip chip is similar to conventional IC fabrication, with a few additional steps. [6] Near the end of the manufacturing process, the attachment pads are metalized to make them more receptive to solder. This typically consists of several treatments. A small dot of solder is then deposited on each metalized pad. The chips are then cut out of the wafer as normal.

To attach the flip chip into a circuit, the chip is inverted to bring the solder dots down onto connectors or pads on the underlying electronics or circuit board or substrate. The solder is then re-melted to produce an electrical connection, typically using a thermosonic bonding or alternatively reflow solder process. [7]

This also leaves a small space between the chip's circuitry and the underlying mounting. In many cases an electrically-insulating adhesive is then "underfilled" to provide a stronger mechanical connection, provide a heat bridge, and to ensure the solder joints are not stressed due to differential heating of the chip and the rest of the system. The underfill distributes the thermal expansion mismatch between the chip and the board, preventing stress concentration in the solder joints which would lead to premature failure. [8]

Solder balls can be mounted on the chips by separately making the balls and then attaching them to the chips by using a vacuum pick up device to pick up the balls and then placing them into a chip with flux applied on contact pads for the balls, or by electroplating in which seed metals are first deposited onto a wafer with the chips to be bumped. This allows the solder to adhere to the contact pads of the chips during the electroplating process. The seed metals are alloys and are deposited by sputtering onto the wafer with the chips to be bumped. A photoresist mask is used to only deposit the seed metal on top of the contact pads of the chips. The wafer then undergoes electroplating, and the photoresist layer is removed or stripped. Then the solder on the chips undergoes solder reflow to form the bumps into their final shape. This entire process is known as wafer bumping. Solder balls are often 75 to 500 microns in diameter. [9] [10]

In 2008, High-speed mounting methods evolved through a cooperation between Reel Service Ltd. and Siemens AG in the development of a high speed mounting tape known as 'MicroTape'. By adding a tape-and-reel process into the assembly methodology, placement at high speed is possible, achieving a 99.90% pick rate and a placement rate of 21,000 cph (components per hour), using standard PCB assembly equipment.

Flip chip packages often consist of a silicon die sitting on top of a "substrate" which then sits on top of a traditional PCB. The substrate can have a Ball Grid Array (BGA) on its underside. The substrate makes the connections to the die available for use by the PCB. [11] Substates made with build up film such as Ajinomoto Build up Film (ABF), are manufactured around a core, and the film is stacked on the core in layers by vacuum lamination at high temperatures. After each layer is applied, the film is cured, and laser vias are made with CO2 or UV lasers, then the blind vias in the substrate are cleaned and the build up film is roughened chemically with a permanganate, and then copper is deposited using electroless copper plating, followed by creating a pattern on the copper using photolithography and etching, and then this process is repeated for every layer of the substrate. [12] [13]

Tape-automated bonding

Tape-automated bonding (TAB) was developed for connecting dies with thermocompression or thermosonic bonding to a flexible substrate including from one to three conductive layers. Also with TAB it is possible to connect die pins all at the same time as with the soldering based flip chip mounting. Originally TAB could produce finer pitch interconnections compared to flip chip, but with the development of the flip chip this advantage has diminished and has kept TAB to be a specialized interconnection technique of display drivers or similar requiring specific TAB compliant roll-to-roll (R2R, reel-to-reel) like assembly system.

Advantages

The resulting completed flip chip assembly is much smaller than a traditional carrier-based system; the chip sits directly on the circuit board, and is much smaller than the carrier both in area and height. The short wires greatly reduce inductance, allowing higher-speed signals, and also conduct heat better.

Disadvantages

Flip chips have several disadvantages.

The lack of a carrier means they are not suitable for easy replacement, or unaided manual installation. They also require very flat mounting surfaces, which is not always easy to arrange, or sometimes difficult to maintain as the boards heat and cool. This limits the maximum device size.

Also, the short connections are very stiff, so the thermal expansion of the chip must be matched to the supporting board or the connections can crack. [14] The underfill material acts as an intermediate between the difference in CTE of the chip and board.

History

The process was originally introduced commercially by IBM in the 1960s for individual transistors and diodes packaged for use in their mainframe systems. [15]

Ceramic subtrates for flip chip BGA were replaced with organic substrates to reduce costs and use existing PCB manufacturing techniques to produce more packages at a time by using larger PCB panels during manufacturing. [16] Ajinomoto Build up Film (ABF) was developed in 1999 and has become a material widely used in flip chip packages, used for manufacturing flip chip substrates in a semi-additive process, first pioneered by Intel. [17] [18] [19] Build up film helped transition the industry away from ceramic substrates, and this film is now essential in the production of organic flip chip package substrates. [20] [21]

Alternatives

Since the flip chip's introduction a number of alternatives to the solder bumps have been introduced, including gold balls or molded studs, electrically conductive polymer and the "plated bump" process that removes an insulating plating by chemical means. Flip chips have recently gained popularity among manufacturers of cell phones and other small electronics where the size savings are valuable.[ citation needed ]

See also

Related Research Articles

<span class="mw-page-title-main">Printed circuit board</span> Board to support and connect electronic components

A printed circuit board (PCB), also called printed wiring board (PWB), is a medium used to connect or "wire" components to one another in a circuit. It takes the form of a laminated sandwich structure of conductive and insulating layers: each of the conductive layers is designed with a pattern of traces, planes and other features etched from one or more sheet layers of copper laminated onto or between sheet layers of a non-conductive substrate. Electrical components may be fixed to conductive pads on the outer layers, generally by means of soldering, which both electrically connects and mechanically fastens the components to the board. Another manufacturing process adds vias, drilled holes that allow electrical interconnections between conductive layers.

<span class="mw-page-title-main">Ball grid array</span> Surface-mount packaging that uses an array of solder balls

A ball grid array (BGA) is a type of surface-mount packaging used for integrated circuits. BGA packages are used to permanently mount devices such as microprocessors. A BGA can provide more interconnection pins than can be put on a dual in-line or flat package. The whole bottom surface of the device can be used, instead of just the perimeter. The traces connecting the package's leads to the wires or balls which connect the die to package are also on average shorter than with a perimeter-only type, leading to better performance at high speeds.

<span class="mw-page-title-main">Surface-mount technology</span> Method for producing electronic circuits

Surface-mount technology (SMT), originally called planar mounting, is a method in which the electrical components are mounted directly onto the surface of a printed circuit board (PCB). An electrical component mounted in this manner is referred to as a surface-mount device (SMD). In industry, this approach has largely replaced the through-hole technology construction method of fitting components, in large part because SMT allows for increased manufacturing automation which reduces cost and improves quality. It also allows for more components to fit on a given area of substrate. Both technologies can be used on the same board, with the through-hole technology often used for components not suitable for surface mounting such as large transformers and heat-sinked power semiconductors.

<span class="mw-page-title-main">Integrated circuit packaging</span> Final stage of semiconductor device fabrication

Integrated circuit packaging is the final stage of semiconductor device fabrication, in which the die is encapsulated in a supporting case that prevents physical damage and corrosion. The case, known as a "package", supports the electrical contacts which connect the device to a circuit board.

<span class="mw-page-title-main">Rework (electronics)</span> Refinishing operation of an electronic printed circuit board assembly

In electronics, rework is the repair or refinish of a printed circuit board (PCB) assembly, usually involving desoldering and re-soldering of surface-mounted electronic components (SMD). Mass processing techniques are not applicable to single device repair or replacement, and specialized manual techniques by expert personnel using appropriate equipment are required to replace defective components; area array packages such as ball grid array (BGA) devices particularly require expertise and appropriate tools. A hot air gun or hot air station is used to heat devices and melt solder, and specialised tools are used to pick up and position often tiny components. A rework station is a place to do this work—the tools and supplies for this work, typically on a workbench. Other kinds of rework require other tools.

<span class="mw-page-title-main">Chip-scale package</span> Integrated circuit package that is no or barely larger than the die it contains

A chip scale package or chip-scale package (CSP) is a type of integrated circuit package.

<span class="mw-page-title-main">Hybrid integrated circuit</span> Type of miniature electronic circuit

A hybrid integrated circuit (HIC), hybrid microcircuit, hybrid circuit or simply hybrid is a miniaturized electronic circuit constructed of individual devices, such as semiconductor devices and passive components, bonded to a substrate or printed circuit board (PCB). A PCB having components on a Printed Wiring Board (PWB) is not considered a true hybrid circuit according to the definition of MIL-PRF-38534.

<span class="mw-page-title-main">System in a package</span> Electronic component

A system in a package (SiP) or system-in-package is a number of integrated circuits (ICs) enclosed in one chip carrier package or encompassing an IC package substrate that may include passive components and perform the functions of an entire system. The ICs may be stacked using package on package, placed side by side, and/or embedded in the substrate. The SiP performs all or most of the functions of an electronic system, and is typically used when designing components for mobile phones, digital music players, etc. Dies containing integrated circuits may be stacked vertically on the package substrate. They are internally connected by fine wires that are bonded to the package substrate. Alternatively, with a flip chip technology, solder bumps are used to join stacked chips together and to the package substrate, or even both techniques can be used in a single package. SiPs are like systems on a chip (SoCs) but less tightly integrated and not on a single semiconductor die.

<span class="mw-page-title-main">Tape-automated bonding</span> Places a microchip on a flexible circuit board

Tape-automated bonding (TAB) is a process that places bare semiconductor chips (dies) like integrated circuits onto a flexible circuit board (FPC) by attaching them to fine conductors in a polyamide or polyimide film carrier. This FPC with the die(s) can be mounted on the system or module board or assembled inside a package. Typically the FPC includes from one to three conductive layers and all inputs and outputs of the semiconductor die are connected simultaneously during the TAB bonding. Tape automated bonding is one of the methods needed for achieving chip-on-flex (COF) assembly and it is one of the first roll-to-roll processing type methods in the electronics manufacturing.

<span class="mw-page-title-main">Flat no-leads package</span> Integrated circuit package with contacts on all 4 sides, on the underside of the package

Flat no-leads packages such as quad-flat no-leads (QFN) and dual-flat no-leads (DFN) physically and electrically connect integrated circuits to printed circuit boards. Flat no-leads, also known as micro leadframe (MLF) and SON, is a surface-mount technology, one of several package technologies that connect ICs to the surfaces of PCBs without through-holes. Flat no-lead is a near chip scale plastic encapsulated package made with a planar copper lead frame substrate. Perimeter lands on the package bottom provide electrical connections to the PCB. Flat no-lead packages usually, but not always, include an exposed thermally conductive pad to improve heat transfer out of the IC. Heat transfer can be further facilitated by metal vias in the thermal pad. The QFN package is similar to the quad-flat package (QFP), and a ball grid array (BGA).

Package on a package (PoP) is an integrated circuit packaging method to vertically combine discrete logic and memory ball grid array (BGA) packages. Two or more packages are installed atop each other, i.e. stacked, with a standard interface to route signals between them. This allows higher component density in devices, such as mobile phones, personal digital assistants (PDA), and digital cameras, at the cost of slightly higher height requirements. Stacks with more than 2 packages are uncommon, due to heat dissipation considerations.

<span class="mw-page-title-main">Thermal copper pillar bump</span>

The thermal copper pillar bump, also known as the "thermal bump", is a thermoelectric device made from thin-film thermoelectric material embedded in flip chip interconnects for use in electronics and optoelectronic packaging, including: flip chip packaging of CPU and GPU integrated circuits (chips), laser diodes, and semiconductor optical amplifiers (SOA). Unlike conventional solder bumps that provide an electrical path and a mechanical connection to the package, thermal bumps act as solid-state heat pumps and add thermal management functionality locally on the surface of a chip or to another electrical component. The diameter of a thermal bump is 238 μm and 60 μm high.

<span class="mw-page-title-main">Wafer-level packaging</span> Means of packaging an integrated circuit

Wafer-level packaging (WLP) is a process in integrated circuit manufacturing where packaging components are attached to an integrated circuit (IC) before the wafer – on which the IC is fabricated – is diced. In WLP, the top and bottom layers of the packaging and the solder bumps are attached to the integrated circuits while they are still in the wafer. This process differs from a conventional process, in which the wafer is sliced into individual circuits (dice) before the packaging components are attached.

A semiconductor package is a metal, plastic, glass, or ceramic casing containing one or more discrete semiconductor devices or integrated circuits. Individual components are fabricated on semiconductor wafers before being diced into die, tested, and packaged. The package provides a means for connecting it to the external environment, such as printed circuit board, via leads such as lands, balls, or pins; and protection against threats such as mechanical impact, chemical contamination, and light exposure. Additionally, it helps dissipate heat produced by the device, with or without the aid of a heat spreader. There are thousands of package types in use. Some are defined by international, national, or industry standards, while others are particular to an individual manufacturer.

<span class="mw-page-title-main">Embedded wafer level ball grid array</span> Packaging technology for integrated circuits

Embedded wafer level ball grid array (eWLB) is a packaging technology for integrated circuits. The package interconnects are applied on an artificial wafer made of silicon chips and a casting compound.

<span class="mw-page-title-main">Solder ball</span>

In integrated circuit packaging, a solder ball, also a solder bump is a ball of solder that provides the contact between the chip package and the printed circuit board, as well as between stacked packages in multichip modules; in the latter case, they may be referred to as microbumps, since they are usually significantly smaller than the former. The solder balls can be placed manually or by automated equipment, and are held in place with a tacky flux.

Digital image correlation analyses have applications in material property characterization, displacement measurement, and strain mapping. As such, DIC is becoming an increasingly popular tool when evaluating the thermo-mechanical behavior of electronic components and systems.

<span class="mw-page-title-main">Chip on board</span> Method of circuit board manufacture

Chip on board (COB) is a method of circuit board manufacturing in which the integrated circuits (e.g. microprocessors) are attached (wired, bonded directly) to a printed circuit board, and covered by a blob of epoxy. Chip on board eliminates the packaging of individual semiconductor devices, which allows a completed product to be less costly, lighter, and more compact. In some cases, COB construction improves the operation of radio frequency systems by reducing the inductance and capacitance of integrated circuit leads.

Glossary of microelectronics manufacturing terms

References

  1. ↑ E. J. Rymaszewski, J. L. Walsh, and G. W. Leehan, "Semiconductor Logic Technology in IBM", IBM Journal of Research and Development, 25, no. 5 (September 1981): 605.
  2. ↑ Filter Center, Aviation Week & Space Technology , September 23, 1963, v. 79, no. 13, p. 96.
  3. ↑ Peter Elenius and Lee Levine, Chip Scale Review. "Comparing Flip-Chip and Wire-Bond Interconnection Technologies". July/August 2000. Retrieved July 30, 2015.
  4. ↑ "BGA Underfill for COTS Ruggedization". NASA. 2019.
  5. ↑ "Underfill revisited: How a decades-old technique enables smaller, more durable PCBs". 2011.
  6. ↑ George Riley, Flipchips.com. “Solder Bump Flip Chip.” November 2000. Retrieved July 30, 2015.
  7. ↑ https://www.analog.com/media/en/technical-documentation/application-notes/AN-617.pdf [ bare URL PDF ]
  8. ↑ Venkat Nandivada. "Enhance Electronic Performance with Epoxy Compounds". Design World. 2013.
  9. ↑ "The back-end process: Step 7 – Solder bumping step by step | Semiconductor Digest".
  10. ↑ "Flip Chip—The Bumping Processes". Integrated Circuit Packaging, Assembly and Interconnections. Springer. 2007. pp. 143–167. doi:10.1007/0-387-33913-2_10. ISBN   978-0-387-28153-7.
  11. ↑ Herbst, Wolfgang. "The back-end process: Step 5 – Flip chip attachProcess and material options". Semiconductor Digest. Retrieved 2024-08-24.
  12. ↑ Materials for Advanced Packaging. Springer. 18 November 2016. ISBN   978-3-319-45098-8.
  13. ↑ He, Lei (2010). "System-in-Package: Electrical and Layout Perspectives". Foundations and Trends in Electronic Design Automation. 4 (4): 223–306. doi:10.1561/1000000014.
  14. ↑ Demerjian, Charlie (2008-12-17), Nvidia chips show underfill problems, The Inquirer, archived from the original on July 21, 2009, retrieved 2009-01-30{{citation}}: CS1 maint: unfit URL (link)
  15. ↑ George Riley, Introduction to Flip Chip: What, Why, How, Flipchips.com October 2000.
  16. ↑ Materials for Advanced Packaging. Springer. 17 December 2008. ISBN   978-0-387-78219-5.
  17. ↑ "Ajinomoto's 'secret ingredient' is now vital to chipmaking giants". 9 November 2022.
  18. ↑ Li, Tengyu; Li, Peng; Sun, Rong; Yu, Shuhui (2023). "Polymer-based nanocomposites in semiconductor packaging". IET Nanodielectrics. 6 (3): 147–158. doi: 10.1049/nde2.12050 .
  19. ↑ Materials for Advanced Packaging. Springer. 17 December 2008. ISBN   978-0-387-78219-5.
  20. ↑ "ABF substrate shortages may dent 2021 shipments of new CPU, GPU chips". 14 December 2020.
  21. ↑ Materials for Advanced Packaging. Springer. 18 November 2016. ISBN   978-3-319-45098-8.
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