Ohtake et al., 1998 - Google Patents

A non-scan DFT method for controllers to achieve complete fault efficiency

Ohtake et al., 1998

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Document ID
7312437380648515583
Author
Ohtake S
Masuzawa T
Fujiwara H
Publication year
Publication venue
Proceedings Seventh Asian Test Symposium (ATS'98)(Cat. No. 98TB100259)

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Snippet

This paper presents a non-scan design-for-testability method for controllers that are synthesized from FSMs (Finite State Machines). The proposed method can achieve complete fault efficiency: test patterns for a combinational circuit of a controller are applied to …
Continue reading at www.researchgate.net (PDF) (other versions)

Classifications

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    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
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    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
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    • G—PHYSICS
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