Sunter et al., 2002 - Google Patents
Complete, contactless I/O testing reaching the boundary in minimizing digital IC testing costSunter et al., 2002
- Document ID
- 6801260956270910651
- Author
- Sunter S
- Nadeau-Dostie B
- Publication year
- Publication venue
- Proceedings. International Test Conference
External Links
Snippet
Embedded test of memory and random logic can enable very low cost ATE to test large, high speed ICs because high quality at-speed tests can be generated onchip. However, it is also necessary to test the DC and AC parameters of the input/output (I/O) circuitry. This paper …
- 238000000034 method 0 abstract description 25
Classifications
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318555—Control logic
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- G01R31/318594—Timing aspects
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- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
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- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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- G01R31/2855—Environmental, reliability or burn-in testing
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- G—PHYSICS
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/3167—Testing of combined analog and digital circuits
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- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
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