Numata et al., 2005 - Google Patents

Control of threshold-voltage and short-channel effects in ultrathin strained-SOI CMOS devices

Numata et al., 2005

Document ID
6384725463890448718
Author
Numata T
Mizuno T
Tezuka T
Koga J
Takagi S
Publication year
Publication venue
IEEE transactions on electron devices

External Links

Snippet

This paper presents a quantitative study on the device design for the control of threshold- voltage and the suppression of short-channel effects (SCEs) in ultrathin strained-silicon-on- insulator (strained-SOI) CMOSFETs in the sub-100-nm regime. A two-dimensional device …
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
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    • H01L29/76Unipolar devices, e.g. field effect transistors
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