Mitra et al., 2003 - Google Patents

XMAX: X-tolerant architecture for MAXimal test compression

Mitra et al., 2003

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Document ID
15018725976524308363
Author
Mitra S
Kim K
Publication year
Publication venue
Proceedings 21st International Conference on Computer Design

External Links

Snippet

XMAX is a novel test data compression architecture capable of achieving almost exponential reduction in scan test data volume and test time while allowing use of commercial automatic test pattern generation (ATPG) tools. It tolerates presence of sources of unknown logic …
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Classifications

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    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558Addressing or selecting of subparts of the device under test
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    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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    • G01R31/318541Scan latches or cell details
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    • G01R31/318371Methodologies therefor, e.g. algorithms, procedures
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    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
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    • G01R31/3177Testing of logic operation, e.g. by logic analysers
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    • G01R31/2851Testing of integrated circuits [IC]

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