Michael, 2004 - Google Patents

Practical lock-free and wait-free LL/SC/VL implementations using 64-bit CAS

Michael, 2004

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Document ID
13638797212670933803
Author
Michael M
Publication year
Publication venue
Distributed Computing: 18th International Conference, DISC 2004, Amsterdam, The Netherlands, October 4-7, 2004. Proceedings 18

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The ideal semantics of the instructions LL/SC/VL (Load-Linked, Store-Conditional, Validate) are inherently immune to the ABA problem which is a fundamental problem that affects most lock-free algorithms. This paper presents practical lock-free and wait-free implementations of …
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Classifications

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    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • G—PHYSICS
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    • G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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