Hanindhito et al., 2021 - Google Patents
Wave-pim: Accelerating wave simulation using processing-in-memoryHanindhito et al., 2021
View PDF- Document ID
- 11881391789780500734
- Author
- Hanindhito B
- Li R
- Gourounas D
- Fathi A
- Govil K
- Trenev D
- Gerstlauer A
- John L
- Publication year
- Publication venue
- Proceedings of the 50th International Conference on Parallel Processing
External Links
Snippet
Wave simulations are used in many applications: medical imaging, oil and gas exploration, earthquake hazard mitigation, and defense systems, among others. Most of these applications require repeated solutions of the wave equation on supercomputers …
- 238000004088 simulation 0 title description 41
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/80—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/08—Multi-objective optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computer systems based on biological models
- G06N3/02—Computer systems based on biological models using neural network models
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computer systems based on biological models
- G06N3/12—Computer systems based on biological models using genetic models
- G06N3/126—Genetic algorithms, i.e. information processing using digital simulations of the genetic system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/25—Using a specific main memory architecture
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F19/00—Digital computing or data processing equipment or methods, specially adapted for specific applications
- G06F19/10—Bioinformatics, i.e. methods or systems for genetic or protein-related data processing in computational molecular biology
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N99/00—Subject matter not provided for in other groups of this subclass
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Wang et al. | Via: A novel vision-transformer accelerator based on fpga | |
Ma et al. | Performance modeling for CNN inference accelerators on FPGA | |
Zhou et al. | An FPGA framework for edge-centric graph processing | |
Escobar et al. | Suitability analysis of FPGAs for heterogeneous platforms in HPC | |
Ramanathan et al. | Look-up table based energy efficient processing in cache support for neural network acceleration | |
Ranjan et al. | X-mann: A crossbar based architecture for memory augmented neural networks | |
Hanindhito et al. | Wave-pim: Accelerating wave simulation using processing-in-memory | |
Yavits et al. | Sparse matrix multiplication on an associative processor | |
Wang et al. | ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing | |
Caminal et al. | CAPE: A content-addressable processing engine | |
Zou et al. | Optimization schemes and performance evaluation of Smith–Waterman algorithm on CPU, GPU and FPGA | |
Gupta | Computing aspects of molecular dynamics simulation | |
Hong et al. | Multi-dimensional parallel training of winograd layer on memory-centric architecture | |
Hazarika et al. | Survey on memory management techniques in heterogeneous computing systems | |
Lenjani et al. | Gearbox: A case for supporting accumulation dispatching and hybrid partitioning in PIM-based accelerators | |
Zhong et al. | CoGNN: An algorithm-hardware co-design approach to accelerate GNN inference with minibatch sampling | |
Zhou et al. | ReD-LUT: Reconfigurable in-DRAM LUTs enabling massive parallel computation | |
Tian et al. | G-nmp: Accelerating graph neural networks with dimm-based near-memory processing | |
Odetola et al. | 2l-3w: 2-level 3-way hardware-software co-verification for the mapping of deep learning architecture (dla) onto fpga boards | |
He et al. | Parallel GMRES solver for fast analysis of large linear dynamic systems on GPU platforms | |
Singh et al. | Cidan-xe: Computing in dram with artificial neurons | |
Lou et al. | Unleashing Network/Accelerator Co-Exploration Potential on FPGAs: A Deeper Joint Search | |
Sharma et al. | A Heterogeneous Chiplet Architecture for Accelerating End-to-End Transformer Models | |
Zhou et al. | Pim-dl: Boosting dnn inference on digital processing in-memory architectures via data layout optimizations | |
Ham et al. | ONNXim: A Fast, Cycle-level Multi-core NPU Simulator |