WO2022012473A1

WO2022012473A1 - Wafer-level packaging method

Info

Publication number: WO2022012473A1
Application number: PCT/CN2021/105823
Authority: WO
Inventors: 黄河; 刘孟彬; 向阳辉
Original assignee: 中芯集成电路（宁波）有限公司上海分公司
Priority date: 2020-07-14
Filing date: 2021-07-12
Publication date: 2022-01-20
Also published as: CN113937017A

Abstract

A wafer-level packaging method. The method comprises: providing a first device wafer on which multiple first chips are formed, each first chip comprising a first surface and a second surface which are opposite to each other, and the first surface being provided with exposed first interconnected electrode and external electrode which are spaced from each other; forming a blocking layer covering the external electrode; providing multiple second chips, the surface of each second chip being provided with an exposed second interconnected electrode; bonding the second chip on the first surface of the first chip by using a bonding layer, the second interconnected electrode and the first interconnected electrode being opposite to each other in the up and down direction to form a cavity, and the second chip being exposed out of the external electrode; after the blocking layer is formed, forming a chip interconnected structure filling the cavity; and after the chip interconnected structure is formed, removing the blocking layer. The present invention improves the packaging reliability and reduces the packaging cost while achieving wafer-level packaging.

Description

Wafer Level Packaging Method

technical field

Embodiments of the present invention relate to the technical field of semiconductor packaging, and in particular, to a wafer-level packaging method.

Background technique

With the development trend of VLSI, the feature size of integrated circuits continues to decrease, and people's requirements for the packaging technology of integrated circuits continue to increase accordingly. Existing packaging technologies include ball grid array packaging (ball grid array, BGA), chip size package (chip scale package, CSP), wafer-level packaging (wafer) level package, WLP), three-dimensional package (3D) and system package (system in package, SiP).

At present, in order to meet the goals of lower cost, more reliability, faster and higher density of integrated circuit packaging, advanced packaging methods mainly adopt the three-dimensional stacking mode of wafer-level system packaging (wafer level package system in package, WLPSIP), compared with the traditional system package, the wafer level system package is to complete the packaging integration process on the wafer, which has the advantages of greatly reducing the area of the package structure, reducing the manufacturing cost, optimizing the electrical performance, batch Sub-manufacturing and other advantages can significantly reduce workload and equipment requirements.

In the wafer-level system packaging process, not only need to bond two bare chips together to achieve physical connection, but also need to connect their interconnecting leads to achieve electrical connection.

technical problem

The problem solved by the embodiments of the present invention is to provide a wafer-level packaging method, which can improve packaging reliability and reduce packaging costs while implementing wafer-level packaging.

technical solutions

To solve the above problems, embodiments of the present invention provide a wafer-level packaging method, including: providing a first device wafer formed with a plurality of first chips, the first chips including opposite first surfaces and second surfaces , the first surface has exposed and spaced first interconnect electrodes and external electrodes; a shielding layer covering the external electrodes is formed; a plurality of second chips are provided, and the surfaces of the second chips have exposed first Two interconnection electrodes; the second chip is bonded on the first surface of the first chip by a bonding layer, the second interconnection electrode and the first interconnection electrode are opposite up and down, and form a cavity, and the second chip exposes the external electrodes; after the shielding layer is formed, a chip interconnection structure filled in the cavity is formed; after the chip interconnection structure is formed, the shielding layer is removed.

beneficial effect

Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages: the embodiment of the present invention provides a first device wafer and a second chip formed with a plurality of first chips, and the first surface of the first chip has a bare surface. The first interconnect electrode and the external electrode are separated and spaced apart, and the surface of the second chip has the exposed second interconnect electrode. After the shielding layer covering the external electrode is formed, the second chip is bonded to the first chip by the bonding layer. On the surface, the second interconnection electrode and the first interconnection electrode face each other up and down to form a cavity, and the second chip exposes the external electrode, and then a chip interconnection structure filled in the cavity is formed; A chip interconnection structure filled in the cavity is formed, thereby realizing wafer-level packaging, and in the process of forming the chip interconnection structure, the shielding layer is used to protect the external electrodes, so as to prevent the external electrodes from being exposed to the formation of chip interconnections. Therefore, the formation of external interconnection bumps on the surface of the external electrodes can be avoided. Since the chip interconnection structure has a certain volume, whether the connection between the external interconnection bumps and the chip interconnection structure can be avoided accordingly, which reduces the The probability of electrical connection between the first interconnection electrode and the external electrode is improved, thereby improving the reliability of the package. In addition, the second chip is bonded to the surface of the first chip and the external electrode is exposed, which can provide accommodation for the bonding wire connecting the external electrode. space, so that the bonding wire is compatible with the three-dimensional stacked wafer-level packaging, which will not lead to an increase in the height of the packaging structure, and has the advantages of simple wire bonding process and low cost; At the same time, the packaging reliability is improved and the packaging cost is reduced.

In an optional solution, the etching selection ratio of the shielding layer and the external electrode is greater than 10:1, so that when the shielding layer is removed, the damage to the external electrode is small, and the surface flatness of the external electrode is maintained, thereby ensuring the follow-up. Wire bond reliability.

In an optional solution, the process of removing the shielding layer includes one or both of a plasma oxidation process and a plasma nitridation process. The gasification method under certain conditions removes the shielding layer, which is not easy to damage the external electrodes, and maintains the surface flatness of the external electrodes, thereby ensuring the reliability of subsequent wire bonding.

Description of drawings

1 to 8 are schematic structural diagrams corresponding to each step in an embodiment of the wafer level packaging method of the present invention.

Embodiments of the present invention

In the field of integrated circuit packaging, it is necessary to integrate two bare chips with different functions or structures, that is, a SIP using a three-dimensional stacking mode. This packaging not only requires bonding two bare chips to achieve physical connection, but also It is also necessary to realize the electrical connection between the two.

Among them, the most typical packaging method can be: 1) The upper and lower bare chips are three-dimensionally stacked on the substrate by curing glue, and wire interconnects are used. Wire the lead pads of the two bare chips to the substrate by bonding) process; 2) Three-dimensionally stack the upper and lower bare chips on the substrate by curing glue, and use the wire bonding process to wire the lead pads of the upper bare chip to the lower bare chip. 3) Flip-chip is realized by bump welding prefabricated on the surface of the upper bare chip or bump welding prefabricated on the surface of the lower bare chip solder, and use wire Bond the lead pads of the lower bare chip to the substrate; 4) Flip-chip bonding is realized by bump welding prefabricated on the surface of the upper bare chip or bump welding prefabricated on the surface of the lower bare chip, and using prefabricated bump welding on the surface of the lower bare chip A through-silicon via (TSV) structure within connects the lead pads of the lower die to the backside of the lower die.

Among them, the bump flip-chip welding process has been used more and more. However, this process is likely to cause unnecessary process modules with high cost, low efficiency and high difficulty. Therefore, it still has the advantages of reducing the overall processing cost and improving the finished product. rate space.

In order to solve the technical problem, embodiments of the present invention provide a first device wafer formed with a plurality of first chips and a second chip, wherein the first surface of the first chip has exposed and spaced apart first interconnect electrodes and a second chip. The external electrode, the surface of the second chip has a second exposed second interconnection electrode, after forming a shielding layer covering the external electrode, the second chip is bonded on the first surface by the bonding layer, the second interconnection electrode and the first surface The interconnection electrodes are opposite up and down to form a cavity, and the external electrodes are exposed from the second chip, and then a chip interconnection structure filled in the cavity is formed; wherein, in the embodiment of the present invention, a chip interconnection structure filled in the cavity is formed by forming a chip interconnection structure. , so as to realize wafer-level packaging, and in the process of forming the chip interconnection structure, the shielding layer is used to protect the external electrodes, so as to prevent the external electrodes from being exposed to the environment in which the chip interconnection structure is formed, thereby avoiding the surface of the external electrodes. The formation of external interconnection bumps, because the chip interconnection structure has a certain volume, can avoid the problem of connection between the external interconnection bumps and the chip interconnection structure, which reduces the electrical generation between the first interconnection electrode and the external electrode. In addition, the second chip is bonded to the surface of the first chip, and the external electrodes are exposed, which can provide accommodation space for the bonding wires connected to the external electrodes, so that the bonding wires are compatible with three-dimensional stacked crystals. Round-level packaging does not lead to an increase in the height of the packaging structure, and has the advantages of simple wire bonding process and low cost. In conclusion, the embodiments of the present invention improve packaging reliability and reduce packaging costs while implementing wafer-level packaging.

In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 1 , a first device wafer (CMOS Wafer) 100 formed with a plurality of first chips 110 is provided, the first chips 110 include opposing first and second surfaces 110 a and 110 b, the first surface 110 a having a bare and The first interconnection electrode 130 and the external electrode 120 are spaced apart.

The packaging method is used to implement wafer-level system packaging, and the first device wafer 100 is used for bonding with the chip to be integrated in a subsequent process.

In this embodiment, the first device wafer 100 is fabricated by using an integrated circuit fabrication technology, and the first device wafer 100 includes a substrate. As an example, the substrate is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator liner Bottom and other types of substrates.

In this embodiment, the first device wafer 100 includes a front side of the wafer and a back side of the wafer, and the back side of the wafer refers to the bottom surface of the substrate in the first device wafer 100 .

A plurality of first chips 110 are formed in the first device wafer 100, the first surface 110a of the first chip 110 has the first interconnection electrodes 130 and the external electrodes 120, and at the edge of the first surface 110a, the first interconnection electrodes 110a are formed. The connecting electrode 130 and the external electrode 120 are exposed. The first surface 110 a and the front surface of the wafer are the same surface, and the first interconnection electrodes 130 and the external electrodes 120 are both interconnection lead pads (Pads) of the first chip 110 , which are used to realize the connection between the first chip 110 and other chips. or electrical connection of circuit structures.

In this embodiment, the first interconnection electrodes 130 and the external electrodes 120 are electrically connected to different circuit structures in the first chip 110 .

In this embodiment, the second chip is subsequently bonded on the first chip 110 , and the first interconnection electrode 130 is used to realize electrical connection with the second chip. The external electrodes 120 are used to electrically lead out the stack formed by the first chip 110 and the second chip, so as to realize the electrical connection between the stack and other substrates having circuit structures.

It should be noted that the exposed positions of the first interconnection electrode 130 and the external electrode 120 are protected by a dielectric layer (not marked) to prevent short circuits, and during the fabrication of the first device wafer 100 , the dielectric layer is etched etched to expose the first interconnection electrodes 130 and the external electrodes 120, therefore, the surfaces of the first interconnection electrodes 130 and the external electrodes 120 are lower than the first surface 110a, that is, the first surface 110a is formed to expose the first interconnection electrodes 130, respectively and the groove of the external electrode 120.

It should also be noted that, for the convenience of illustration, this embodiment is described by taking as an example that five first chips 110 are formed in the first device wafer 100 . But the number of the first chips 110 is not limited to five.

Referring to FIG. 2 , a shielding layer 150 covering the external electrodes 120 is formed.

The shielding layer 150 is used to protect the external electrodes 120 .

Subsequently, a second chip will be bonded on the first surface 110a, the second interconnection electrode of the second chip and the first interconnection electrode 130 are opposed to each other up and down, forming a cavity, and the second chip exposes the external electrodes, and then a filling is formed in the second chip. The chip interconnection structure in the cavity; in the process of forming the chip interconnection structure, the shielding layer 150 is used to protect the external electrodes 120, so as to prevent the external electrodes 120 from being exposed to the environment in which the chip interconnection structure is formed, so as to avoid external External interconnection bumps are formed on the surface of the electrode 120. Since the chip interconnection structure has a certain volume, whether the connection between the external interconnection bumps and the chip interconnection structure can be avoided accordingly, which reduces the amount of the first interconnection electrode 130 and the chip interconnection structure. The probability of electrical connection between the external electrodes 120 is increased, thereby improving the reliability of the package. For example, when an electroplating process is used to form the chip interconnection structure filled in the cavity, the shielding layer can prevent electroplating on the surface of the external electrode 120 during the electroplating process, thereby avoiding the formation of external interconnection on the surface of the external electrode 120 For connecting bumps, since the electroplating bodies formed by the electroplating process all have a certain volume, whether it is possible to avoid the problem of connecting the external interconnection bumps with the chip interconnection structure.

It should be noted that electroplating will be performed on the surface of the first interconnection electrode 130 later. Therefore, in order to reduce the influence of the formation of the shielding layer 150 on the subsequent electroplating process, the process of forming the shielding layer 150 will damage the first interconnection electrode 130 small. Moreover, the shielding layer 150 will be removed later. Correspondingly, the process of removing the shielding layer 150 has little damage to the first interconnection electrode 130, and can maintain the surface flatness of the first interconnection electrode 130, thereby ensuring the smoothness of the subsequent electroplating process. reliability.

Similarly, when the shielding layer 150 is subsequently removed, the damage to the external electrodes 120 is small, and the surface flatness of the external electrodes 120 can be maintained, thereby ensuring the reliability of subsequent bonding wires.

Therefore, the material of the shielding layer 150 satisfies that the etching selectivity ratio between the shielding layer 150 and the first interconnection electrode 130 is greater than 10:1, and the etching selectivity ratio between the shielding layer 150 and the external electrode 120 is greater than 10:1.

In this embodiment, the material of the shielding layer 150 includes one or both of polyimide (PI) and carbon-containing media.

Polyimide is an organic material, therefore, the removal process of the polyimide layer causes less damage to the first interconnection electrode 130 and the external electrode 120 . The carbon-containing medium can react with the gas-phase etchant to form a gas, and the process of removing the carbon-containing medium also causes less damage to the first interconnection electrode 130 and the external electrode 120 . As an example, the carbonaceous medium may include amorphous carbon.

As an example, the material of the shielding layer 150 is polyimide.

Specifically, the steps of forming the shielding layer 150 include: depositing a shielding material layer on the first device wafer 100 ; and etching the shielding material layer in the remaining areas exposed by the external electrodes 120 to form the shielding layer 150 .

In this embodiment, the etching selection ratio between the shielding layer 150 and the first interconnection electrode 130 is, therefore, in the step of etching the shielding material layer in the remaining area exposed by the external electrode 120, the damage to the first interconnection electrode 130 is small. .

It should be noted that the thickness of the shielding layer 150 should not be too small or too large. If the thickness of the shielding layer 150 is too small, in the subsequent electroplating process, metal ions can easily pass through the shielding layer 150 and contact the external electrodes 120 , so that a randomly distributed electroplating layer is easily formed on the surface of the external electrodes 120 , thereby causing the external electrodes 120 If the thickness of the shielding layer 150 is too large, the process time required for etching the shielding material layer and subsequent removal of the shielding layer 150 will be longer, which is not conducive to improving the packaging efficiency. Moreover, when the shielding layer 150 is removed, the first interconnection electrode 130 is exposed to the process environment in which the shielding layer 150 is removed for a long time, and the probability of damage to the first interconnection electrode 130 becomes high. To this end, in this embodiment, the thickness of the shielding layer 150 is 0.1 μm to 1 μm. For example, the thickness of the blocking layer 150 may be 0.3 microns, 0.5 microns, 0.7 microns or 0.9 microns.

Referring to FIG. 3 , a plurality of second chips 200 are provided, and the surfaces of the second chips 200 have exposed second interconnect electrodes 210 .

The second chip 200 is used as a chip to be integrated in the wafer level system package.

The second chip 200 may be one or more of active elements, passive elements, micro-electromechanical systems, optical elements, and the like. Specifically, the second chip 200 may be a functional chip such as a memory chip, a communication chip, a processing chip, a flash memory chip, or a logic chip.

Subsequently, a plurality of second chips 200 are integrated on the first device wafer 100 , and a packaging integration process is completed on the first device wafer 100 to realize wafer-level packaging, thereby greatly reducing the area of the packaging structure and the manufacturing process. Cost, optimized electrical performance, batch manufacturing and other advantages can significantly reduce workload and equipment requirements.

In this embodiment, the number of the second chips 200 is the same as the number of the first chips 110 . In other embodiments, the numbers of the first chips and the second chips may also be different.

In this embodiment, the second chip 200 is fabricated by using an integrated circuit fabrication technology, and the second chip 200 includes a substrate. For the description of the substrate of the second chip 200, reference may be made to the foregoing description of the first chip 110, and details are not repeated here.

The surface of the second chip 200 has a second interconnection electrode 210 , and at the edge of the surface of the second chip 200 , the second interconnection electrode 210 is exposed, and the second interconnection electrode 210 is an interconnection wire bond of the second chip 200 plate. In this embodiment, the second chip 200 includes a front side of the chip and a back side of the chip, and the second interconnect electrodes 210 are located on the front side of the chip, that is, the second interconnect electrodes 210 are exposed from the front side of the chip. Here, the backside of the chip refers to the bottom surface of the substrate in the second chip 200 .

It should be noted that the second chip 200 may have a surface structure similar to that of the first chip 110 , the exposed positions of the second interconnection electrodes 210 are protected by a dielectric layer (not marked) to prevent short circuits, and the second interconnection electrodes 210 are The surface is lower than the surface of the second chip 200 , that is, the surface of the second chip 200 is formed with grooves exposing the second interconnection electrodes 210 .

It should also be noted that the size of the second chip 200 is smaller than that of the first chip 110 , so that after the second chip 200 is bonded to the first chip 110 , the second chip 200 can expose the external electrodes of the first chip 110 120.

Continuing to refer to FIG. 3 , the second chip 200 is bonded on the first surface 110 a (shown in FIG. 1 ) of the first chip 110 by using the bonding layer 140 , and the second interconnection electrode 210 and the first interconnection electrode 130 are up and down On the other hand, the cavity 10 is enclosed, and the second chip 200 exposes the external electrodes 120 of the first chip 110 .

By bonding the second chip 200 on the first chip 110 , the system integration of the second chip 200 and the first wafer 100 is realized.

Moreover, the second chip 200 is bonded on the first surface 110 a so as to realize the electrical connection between the second chip 200 and the first chip 110 .

In addition, the second chip 200 exposes the external electrodes 120 of the first chip 110, so that the packaging method can be compatible with the wire bonding process, that is, it can provide accommodation space for the bonding wires connected to the external electrodes 120, so that the bonding wires are compatible Wafer-level packaging for three-dimensional stacking without increasing the height of the package structure.

In this embodiment, after bonding, the second interconnection electrode 210 and the first interconnection electrode 130 face each other up and down to form a cavity 10 , and the second interconnection electrode 210 and the first interconnection electrode 130 are located in the cavity 10 .

The cavity 10 is used to provide a space for the subsequent formation of a chip interconnection structure electrically connecting the second interconnection electrode 210 and the first interconnection electrode 130 . The cavity 10 is formed by the groove where the first interconnection electrode 130 is located and the groove where the second interconnection electrode 210 is located.

As an example, each second chip 200 is individually bonded to the corresponding first chip 110 on the first device wafer 100 in a chip-level manner, so that each second chip 200 can be accurately bonded to at the preset position.

In this embodiment, the second chip 200 is bonded to the first surface 110a by using the bonding layer 140 . The bonding layer 140 has a certain thickness so as to form the unsealed cavity 10 .

In this embodiment, the bonding layer 140 has viscosity, so that the adhesive bonding can be realized. The bonding temperature of the adhesive bonding is low, which is beneficial to reduce the influence on the performance of the chip, and the process of the adhesive bonding is simple.

Specifically, the material of the bonding layer 140 is a photosensitive material, so that patterning can be achieved through a photolithography process, thereby reducing damage to the electrodes.

In this embodiment, the bonding layer 140 is a dry film. In other embodiments, other types of adhesive layers may also be used, for example, Die Attach Film (DAF).

As shown in FIG. 2 , in this embodiment, before bonding, the bonding layer 140 is formed on the exposed first surface 110 a of the first interconnection electrode 130 and the external electrode 120 .

The bonding layer 140 is formed on the first device wafer 100, so that the bonding layer 140 can be formed on the plurality of first chips 110 in the same step, thereby improving the packaging efficiency.

Moreover, the bonding layer 140 exposes the first interconnection electrodes 130 and the external electrodes 120 , thereby forming the unsealed cavity 10 .

It should be noted that the thickness of the bonding layer 140 should not be too small or too large. If the thickness of the bonding layer 140 is too small, the adhesive force of the bonding layer 140 may be insufficient, thereby reducing the bonding strength between the second chip 200 and the first device wafer 100 , and the thickness of the bonding layer 140 will affect the For the height of the cavity 10, if the thickness of the bonding layer 140 is too small, the height of the cavity 10 is likely to be too small, thereby increasing the difficulty of filling the cavity 10 with subsequent electroplating bodies; if the thickness is too large, it will lead to The thickness of the encapsulation structure formed subsequently is too large, which is not conducive to the development of device miniaturization. Therefore, in this embodiment, the thickness of the bonding layer 140 is 5 micrometers to 50 micrometers. For example, the thickness of the bonding layer 140 may be 10 microns, 20 microns, 30 microns or 40 microns.

In this embodiment, after the blocking layer 150 is formed, the bonding layer 140 is formed. By first forming the shielding layer 150 , the shielding layer 150 is used to protect the external electrodes 120 , thereby preventing the process of forming the bonding layer 140 from affecting the external electrodes 120 .

In other embodiments, according to process requirements, the second chip may be bonded to the first chip after the bonding layer is formed on the second chip.

In this embodiment, the optical alignment process is used to realize the bonding.

During the preparation process of the second chip 200 and the first device wafer 100, the surfaces of the second chip 200 and the first chip 110 have corresponding optical alignment marks. Therefore, the optical alignment process can be used to realize the bonding, thereby It is beneficial to improve the bonding accuracy.

Wherein, the light source used in the optical alignment process includes an infrared light source or a visible light source. As an example, the optical alignment process uses an infrared light source to further improve alignment accuracy.

In other embodiments, according to the actual situation, the bonding can also be realized by means of mechanical alignment. For example, when the chip surface is not formed with alignment marks.

It should be noted that this embodiment takes adhesive bonding as an example for description. In other embodiments, other bonding methods can also be used to bond the second chip to the first device wafer. The bonding is realized by fusion bonding of silicon oxide. Correspondingly, the dielectric layer used for realizing the bonding is used as the bonding layer, and the dielectric layer may be a silicon oxide layer.

It should also be noted that, in this embodiment, before the second chip is bonded to the first device wafer 100, the shielding layer 150 is formed to facilitate the deposition and etching of the shielding material layer, thereby reducing the formation of the shielding layer. 150 is difficult to process, and it is beneficial to remove the shielding material layer on the surface of the first interconnection electrode 130 , thereby exposing the first interconnection electrode 130 .

In other embodiments, depending on the actual situation, a shielding layer covering the external electrodes may be formed after bonding, or, after the bonding layer is formed on the first device wafer, before bonding, a shielding layer covering the external electrodes may be formed occlusion layer.

Referring to FIG. 4 , after the blocking layer 150 is formed, the chip interconnection structure 31 filled in the cavity 10 (as shown in FIG. 3 ) is formed.

The chip interconnection structure 31 is used to realize the electrical connection between the first interconnection electrode 130 and the second interconnection electrode 210 , so as to realize the interconnection package of the second chip 200 and the first device wafer 100 .

Moreover, in this embodiment, by forming the chip interconnection structure 31 filled in the cavity 10 , wafer level packaging can be realized.

In the present embodiment, the chip interconnection structure 31 is formed by an electroplating process. Through the electroplating process, a good filling effect can be achieved in the cavity 10, thereby improving the reliability of the electrical connection and correspondingly improving the packaging reliability. The electroplating process enables wafer-level packaging.

In this embodiment, an electroplating process is performed, so that the electroplating body is filled into the cavity 10 from the boundary of the second chip 200 , and the electroplating body in the cavity 10 is in contact with both the first interconnection electrode 130 and the second interconnection electrode 210 , so as to realize the electrical connection between the first interconnection electrode 130 and the second interconnection electrode 210 .

Wherein, since the external electrode 120 is covered by the shielding layer 150 , the electroplating body cannot be deposited on the surface of the external electrode 120 , so the electroplating body is only filled in the cavity 10 .

In this embodiment, the electroplating process is electroless electroplating (ie, electroless plating). Specifically, the bonded second chip 200 and the first device wafer 100 are placed in a solution containing metal ions (eg, electroless silver plating, nickel plating, copper plating, etc.) In principle, a strong reducing agent is used to reduce metal ions to metal and deposit them on the surfaces of the first interconnection electrode 130 and the second interconnection electrode 210 to form a dense metal coating. After a period of reaction time, the metal coating fills the cavity 10 , thereby forming the chip interconnect structure 31 .

By using electroless plating, there is no need to energize, and the electroplating body is deposited on the exposed electrode surface, thereby reducing the requirements for the interconnection mode of the electrodes inside the chip, and the process flexibility is higher.

In this embodiment, the material of the chip interconnection structure 31 includes one or more of copper, nickel, zinc, tin, silver, gold, tungsten and magnesium.

Referring to FIG. 5 , after the chip interconnect structure 31 is formed, the blocking layer 150 (as shown in FIG. 4 ) is removed.

The shielding layer 150 is removed to expose the external electrodes 120, so as to prepare for the subsequent electrical connection between the external electrodes 120 and other substrates, chips or interconnect structures.

In this embodiment, according to the material of the shielding layer 150, the process of removing the shielding layer 150 includes one or both of a plasma oxidation process and a plasma nitridation process. For example, the shielding layer 150 is removed by vaporizing under the condition of oxygen) or nitrogen-containing gas (for example, nitrogen), which is not easy to damage the external electrodes 120, and can maintain the surface flatness of the external electrodes 120, thereby ensuring the reliability of subsequent wire bonding .

In this embodiment, the material of the shielding layer 150 is a carbon-containing medium, therefore, the shielding layer 150 is removed by a plasma oxidation process. The oxygen-containing gas (eg, oxygen) used in the plasma oxidation process can oxidize the carbon-containing medium to carbon dioxide, thereby directly removing the reaction by-products from the reaction chamber, so there is less damage to the electrodes, and it is also beneficial to reduce the generation of The probability of the blocking layer 150 remaining or reaction by-products.

In other embodiments, when the material of the shielding layer is polyimide, a plasma oxidation process is used to remove the shielding layer.

Referring to FIG. 6 , after the chip interconnect structure 31 is formed, the first device wafer 100 (shown in FIG. 5 ) is cut to form a chip module (not shown), the chip module includes the second chip 200 and the second chip 200 and the second chip 200 bonded together. A chip 110 .

After the first device wafer 100 is cut, the second chip 200 and the corresponding first chip 110 form an independent chip module, so as to prepare for the subsequent fixing of the chip module to other substrates.

The first device wafer 100 is generally provided with scribe lines that are crisscrossed, and the scribe lines are disposed between any two adjacent first chips 110 on the first device wafer 100 . The first device wafer 100 is diced by the lanes.

In this embodiment, the first device wafer 100 between the first chips 110 is partially etched from the first surface 110 a (shown in FIG. 1 ) to form trenches (not shown in the figure), and then the second device wafer 100 is partially etched between the first chips 110 . The surface 110b (shown in FIG. 1 ) is subjected to a backside thinning process to expose trenches to separate the individual first chips 110 .

Since the etching process has a wider process window, narrower dicing lines can be etched, thereby reducing the probability of damage to the second chip 200 and the chip interconnection structure 31, and also improving the collapse of the first chip 110. The edge phenomenon reduces the probability of damage to the effective circuit inside the first chip 110 , which is beneficial to obtain a complete independent stack, which in turn is beneficial to improve package reliability.

Moreover, by performing the backside thinning process on the second surface 110b, a lighter, thinner and smaller wafer-level chip package can be realized.

In other embodiments, laser cutting or mechanical cutting may also be used for cutting.

It should be noted that, in this embodiment, the second chip 200 is bonded to the first device wafer 100 in a chip-level manner. In other embodiments, the second chip may also be bonded to the first device wafer in a wafer-level manner.

Specifically, in the step of providing a plurality of second chips 200, the second chips 200 are located in the second device wafer; in the step of bonding, the second device wafer is correspondingly bonded to the first device wafer. Therefore, before cutting the first device wafer, the packaging method further includes: cutting the second device wafer to separate each of the second chips 200 .

As an example, the second device wafer is diced to separate the individual second chips 200 prior to forming the chip interconnect structure. By cutting the second device wafer first, the cavity can be better exposed so that the material of the chip interconnect structure can enter the cavity. For the description of the dicing process of the second device wafer, reference may be made to the foregoing corresponding description of the dicing process of the first device wafer, which will not be repeated here.

Referring to FIG. 7 , after cutting the first device wafer 100 (as shown in FIG. 5 ), the packaging method further includes: adhering the chip module to a substrate 300 having a circuit structure 310 in the substrate 300 .

Specifically, the second surface 110 b of the first chip 110 (as shown in FIG. 1 ) is bonded to the substrate 300 .

By adhering the second surface 110b to the substrate 300, it is prepared for the subsequent wire bonding process, so as to use the circuit structure 310 in the substrate 300 to provide a circuit to the stack composed of the first chip 110 and the second chip 200 signal, or, using the circuit structure 310 in the substrate 300 to realize the electrical connection of the stack to other chips or other substrates.

In this embodiment, the substrate 300 may be a printed circuit board (printed circuit board, printed circuit board). In other embodiments, the substrate may also be other types of substrates such as an FPC board (flexible printed circuit board, flexible circuit board) or an interposer board.

In this embodiment, the second surface 110b is adhered to the substrate 300 through the adhesive layer 230 . As an example, the adhesive layer 230 may be an adhesive film.

It should be noted that, in this embodiment, after the chip interconnection structure 31 is formed and before the first device wafer 100 is cut, the shielding layer 150 is removed, so that the shielding layer 150 on each external electrode 120 can be removed at the same time, thereby improving the packaging efficient.

In other embodiments, according to process requirements, the shielding layer may also be removed after the second surface of the first chip is bonded to the substrate, thereby reducing the probability of the external electrodes being oxidized, thereby helping to improve the subsequent wire bonding. bond) process reliability.

Continuing to refer to FIG. 7 , after removing the shielding layer 150 (as shown in FIG. 4 ), a wire bonding process is used to form a bonding wire 220 , and the bonding wire 220 is electrically connected to the external electrode 120 and the circuit structure 310 in the substrate 300 .

The bonding wires 220 electrically connect the external electrodes 120 with the circuit structure 310 , thereby realizing the system integration of the independent chip module composed of the first chip 110 and the second chip 200 and the substrate 300 .

The wire bonding process is the most commonly used circuit connection method in the integrated circuit packaging process. The method enables the thin metal wires or metal strips to be punched in sequence on the bonding points of the chip and the lead frame or the packaging substrate to form a circuit connection. The wire bonding process has high compatibility with the current packaging process, and has the advantages of simple process and low cost. Therefore, by using the wire bonding process, it is beneficial to reduce the packaging cost.

In this embodiment, the bonding wire 220 is a metal wire, such as a gold wire or an aluminum wire.

In this embodiment, the highest point of the bonding wire 220 is lower than the surface of the second chip 200 facing away from the first chip 110 . A cover layer covering at least the chip interconnection structure 31 and the bonding wire 220 will also be formed in the subsequent process. and the bonding wires 220 are buried in the capping layer, and at the same time, it is easy to make the thickness of the package structure small.

In other embodiments, the highest point of the bonding wire may also be flush with the surface of the second chip facing away from the chip.

Referring to FIG. 8 , after the bonding wires 220 are formed, the packaging method further includes: forming a capping layer 250 covering at least the chip interconnection structure 31 and the bonding wires 220 .

The cover layer 250 plays a role in fixing the first chip 110 and the second chip 200 , and is used to realize package integration of the first chip 110 and the second chip 200 . Also, the capping layer 250 is used to achieve insulation, sealing and protection of the chip interconnect structure 31 and the bonding wires 220 .

Therefore, the material of the cover layer 250 is an insulating material. In this embodiment, the material of the cover layer 250 includes one or both of a dielectric material and a plastic sealing material, and the dielectric material may be silicon oxide, silicon nitride or other dielectric materials.

In this embodiment, the material of the cover layer 250 is a plastic sealing material. Specifically, the material of the cover layer 250 may be epoxy resin. Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties and low cost, so it is widely used as packaging material for electronic devices and integrated circuits.

As an example, the cover layer 250 may be formed by an injection molding process.

In this embodiment, the cover layer 250 also covers the surface of the second chip 200 facing away from the first chip 110 , so as to bury the second chip 200 , the first chip 110 , the chip interconnection structure 31 and the bonding wires 220 , and further Conducive to improving packaging reliability.

In other embodiments, the top surface of the cover layer may also be flush with the surface of the second chip facing away from the first chip, or the cover layer covers part of the sidewall of the second chip.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims

A wafer-level packaging method, comprising:

A first device wafer is provided formed with a plurality of first chips, the first chips including opposing first and second surfaces, the first surface having exposed and spaced apart first interconnect electrodes and external electrode;

forming a shielding layer covering the external electrodes;

providing a plurality of second chips, the surfaces of the second chips have exposed second interconnect electrodes;

The second chip is bonded on the first surface of the first chip by using a bonding layer, the second interconnection electrode and the first interconnection electrode face each other up and down to form a cavity, and the second interconnection electrode is opposite to the first interconnection electrode. The chip exposes the external electrodes;

After forming the shielding layer, forming a chip interconnection structure filled in the cavity;

After the chip interconnect structure is formed, the blocking layer is removed.
The wafer-level packaging method according to claim 1, wherein the wafer-level packaging method further comprises: after forming the chip interconnection structure, cutting the first device wafer to form a chip module, the The chip module includes the second chip and the first chip bonded together.
The wafer-level packaging method according to claim 2, wherein after cutting the first device wafer, the wafer-level packaging method further comprises: adhering the chip module to a substrate, the The substrate has a circuit structure;

A bonding wire is formed by a wire bonding process, and the bonding wire electrically connects the external electrode and the circuit structure in the circuit substrate.
The wafer-level packaging method according to claim 1, wherein the chip interconnection structure is formed by an electroplating process, and the electroplating process includes an electroless electroplating process.
The wafer-level packaging method of claim 1, wherein the shielding layer is formed before bonding.
The wafer-level packaging method of claim 2, wherein the shielding layer is removed after the chip interconnection structure is formed and before the first device wafer is cut.
The wafer-level packaging method according to claim 1, wherein the etching selection ratio between the shielding layer and the first interconnection electrode is greater than 10:1, and the etching selection ratio between the shielding layer and the external electrode is greater than 10:1. The eclipse selection ratio is greater than 10:1.
The wafer-level packaging method according to claim 1, wherein the material of the shielding layer comprises one or both of polyimide and carbon-containing media.
The wafer level packaging method according to claim 1, wherein the process of removing the shielding layer comprises one or both of a plasma oxidation process and a plasma nitridation process.
The wafer-level packaging method according to claim 1, wherein the step of forming the shielding layer comprises: depositing a shielding material layer on the first device wafer; etching the remaining area exposed by the external electrode The said shielding material layer forms a shielding layer.
The wafer-level packaging method according to claim 1, wherein the shielding layer has a thickness of 0.1 micrometer to 1 micrometer.
The wafer-level packaging method according to claim 1, wherein the bonding layer comprises a dry film or an adhesive film, and the thickness of the bonding layer is 5 micrometers to 50 micrometers.
The wafer-level packaging method according to claim 1, wherein each of the second chips is individually bonded to the corresponding first chip on the first device wafer.
The wafer-level packaging method according to claim 1, wherein in the step of providing the plurality of second chips, the second chips are located in the second device wafer;

In the bonding step, the second device wafer is bonded to the first device wafer.
The wafer-level packaging method according to claim 14, wherein before forming the chip interconnection structure, the wafer-level packaging method further comprises: cutting the second device wafer to separate the second chip.
The wafer-level packaging method according to claim 1, wherein the bonding is realized by an optical alignment process.
The wafer-level packaging method according to claim 3, wherein after the bonding wires are formed, the wafer-level packaging method further comprises: forming a cover layer covering at least the chip interconnection structure and the bonding wires.