US20150194320A1 - Metallic mask patterning process for minimizing collateral etch of an underlayer - Google Patents

Metallic mask patterning process for minimizing collateral etch of an underlayer Download PDF

Info

Publication number
US20150194320A1
US20150194320A1 US14/149,898 US201414149898A US2015194320A1 US 20150194320 A1 US20150194320 A1 US 20150194320A1 US 201414149898 A US201414149898 A US 201414149898A US 2015194320 A1 US2015194320 A1 US 2015194320A1
Authority
US
United States
Prior art keywords
layer
organic planarization
metallic
planarization layer
hard mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US14/149,898
Other versions
US9093387B1 (en
Inventor
Scott D. Allen
Kuang-Jung Chen
Huihang Dong
Wai-kin Li
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alsephina Innovations Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US14/149,898 priority Critical patent/US9093387B1/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, KUANG-JUNG, ALLEN, SCOTT D, DONG, HUIHANG, LI, WAI-KIN
Publication of US20150194320A1 publication Critical patent/US20150194320A1/en
Application granted granted Critical
Publication of US9093387B1 publication Critical patent/US9093387B1/en
Assigned to GLOBALFOUNDRIES U.S. 2 LLC reassignment GLOBALFOUNDRIES U.S. 2 LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL BUSINESS MACHINES CORPORATION
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES U.S. 2 LLC, GLOBALFOUNDRIES U.S. INC.
Assigned to ALSEPHINA INNOVATIONS INC. reassignment ALSEPHINA INNOVATIONS INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES INC.
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: WILMINGTON TRUST, NATIONAL ASSOCIATION
Expired - Fee Related legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Definitions

  • the present disclosure relates to methods of patterning a metallic material layer on a dielectric material layer and structures for effecting the same.
  • Patterning of a metallic material layer overlying a dielectric layer can result in collateral damages of the underlying dielectric layer.
  • the functionality of the dielectric layer is affected by collateral damages as in the case of a gate dielectric layer, minimizing the collateral damages during the processing steps is critical in providing high performance and/or reliability in the device employing the dielectric layer.
  • a patterning process for a stack of a high dielectric constant (high-k) gate dielectric layer including a dielectric metal oxide and a metallic material layer can employ an etch mask stack including a second metallic material layer in addition to a photoresist layer. While the second metallic material layer can be advantageously employed to generate a high fidelity replica of the pattern in the photoresist layer, removal of the second metallic material layer can result in collateral etch of the high-k gate dielectric layer and metallic contamination in a processing tool. Further, removal of additional materials in the etch mask stack can result in further collateral etching of the metallic material layer.
  • a method is desired for patterning a metallic material layer while minimizing collateral etches of an underlying dielectric layer and avoiding metallic contamination.
  • a stack of a dielectric material layer and a metallic material layer are formed on a substrate.
  • a first organic planarization layer, a non-metallic hard mask layer, and a photoresist layer are sequentially deposited over the metallic material layer.
  • the photoresist layer is lithographically patterned, and the pattern in the photoresist layer is transferred through the non-metallic hard mask layer, the first organic planarization layer, and the metallic material layer to form a cavity.
  • a second organic planarization layer is deposited within the cavity and over remaining portions of the photoresist layer.
  • the second organic planarization layer and the photoresist layer are recessed, and the non-metallic hard mask layer is subsequently removed. Remaining portions of the first and second organic planarization layers are simultaneously removed to provide physically exposed surfaces of the patterned metallic material layer and a top surface of the dielectric material layer.
  • a method of forming a patterned structure is provided.
  • a vertical stack is formed over a dielectric material layer on a substrate.
  • the vertical stack includes, from bottom to top, a metallic material layer, a first organic planarization layer, and a non-metallic hard mask layer.
  • a cavity is formed though the non-metallic hard mask layer, the first organic planarization layer, and the metallic material layer.
  • a top surface of the dielectric material layer is physically exposed underneath the cavity.
  • a second organic planarization layer is applied in the cavity and over the non-metallic hard mask layer. An upper portion of the second organic planarization layer is recessed.
  • the non-metallic hard mask layer is removed.
  • a lower portion of the second organic planarization layer and the first organic planarization layer are removed.
  • the top surface of the dielectric material layer is physically exposed again.
  • FIG. 1 is a vertical cross-sectional view of an exemplary structure after formation of a stack including a dielectric material layer, a metallic material layer, a first organic planarization layer, a dielectric mask layer, and a patterned photoresist layer on a substrate according to an embodiment of the present disclosure.
  • FIG. 2 is a vertical cross-sectional view of the exemplary structure after transfer of the pattern of in the photoresist layer into the dielectric mask layer, the first organic planarization layer, and the first metallic material layer by a set of at least one etch according to an embodiment of the present disclosure.
  • FIG. 3 is a vertical cross-sectional view of the exemplary structure after application of a second organic planarization layer according to an embodiment of the present disclosure.
  • FIG. 4 is a vertical cross-sectional view of the exemplary structure after recessing the second organic planarization layer and collateral removal of any remaining portion of the photoresist layer according to an embodiment of the present disclosure.
  • FIG. 5 is a vertical cross-sectional view of the exemplary structure after removal of the dielectric mask layer according to an embodiment of the present disclosure.
  • FIG. 6 is a vertical cross-sectional view of the exemplary structure after removal of the first and second organic planarization layers according to an embodiment of the present disclosure.
  • FIG. 7 is a vertical cross-sectional view of a variation of the exemplary structure after application of a second organic planarization layer according to an embodiment of the present disclosure.
  • the present disclosure relates to methods of patterning a metallic material layer on a dielectric material layer and structures for effecting the same, which are now described in detail with accompanying figures. It is noted that like and corresponding elements are referred to by like reference numerals.
  • the drawings are not in scale.
  • ordinals such as “first” and “second” are employed merely to distinguish similar elements, and different ordinals may be employed to designate a same element in the specification and/or claims.
  • an exemplary structure includes a material stack formed on a substrate 10 .
  • the material stack includes, from bottom to top, of a dielectric material layer 20 , a metallic material layer 30 , a first organic planarization layer 40 , a dielectric mask layer 50 , and a patterned photoresist layer 57 .
  • the substrate 10 can include any solid material.
  • the substrate 10 can include at least one semiconductor material, at least one conductive material, at least one dielectric material, or a combination or a stack thereof.
  • Semiconductor materials that can be included in the substrate 10 include, but are not limited to, an elemental semiconductor material such as silicon or germanium; an alloy of Group IV elements such as a silicon-germanium alloy, a silicon-carbon alloy, and a silicon-germanium-carbon alloy; a compound semiconductor material; an organic semiconductor material; and combinations thereof.
  • Metallic material that can be included in the substrate 10 include, but are not limited to, an elemental metal, an intermetallic alloy, a conductive metallic nitride, a conductive metallic carbide, and combinations and alloys thereof.
  • Dielectric materials that can be included in the substrate 10 include, but are not limited to, a dielectric oxide of at least one semiconductor element such as silicon oxide, a dielectric nitride of at least one semiconductor element such as silicon nitride, a dielectric metal oxide, a dielectric metal nitride, and combinations and alloys thereof.
  • the substrate 10 can be sufficiently thick to provide mechanical support for the material stack thereupon.
  • the thickness of the substrate 10 can be in a range from 30 microns to 1 mm, although lesser and greater thicknesses can also be employed.
  • the topmost portion of the substrate 10 can include a semiconductor layer embedding various doped semiconductor material portions.
  • the substrate 10 can include source and drain regions of field effect transistors that are formed in a semiconductor material portion.
  • the semiconductor material portion can be a planar semiconductor portion laterally surrounded by a shallow trench isolation structure (not shown) and having a top surface that is coplanar with the topmost surface of the substrate 10 , or can be a semiconductor fin as known in the art.
  • the topmost portion of the substrate 10 can include a metal interconnect structure including at least one interlayer dielectric (ILD) material layer and at least one metal line structure and/or at least one metal via structure as known in the art.
  • the topmost portions of the substrate can include a dielectric material such as silicon oxide, silicon nitride, porous or non-porous organosilicate glass, or combinations thereof.
  • at least one metal line structure and/or at least one metal via structure can include a metallic material such as copper, aluminum, tungsten, a metallic nitride, a metallic carbide, or a combination thereof.
  • the dielectric material layer 20 can include any dielectric material.
  • the dielectric material layer 20 can include a dielectric material that is known to be suitable for a gate dielectric of a field effect transistor.
  • the thickness of the dielectric material layer 20 can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed.
  • the dielectric material layer 20 can include a dielectric oxide of at least one semiconductor element such as silicon oxide or a silicon-germanium oxide, or a dielectric oxynitride of at least one semiconductor element such as silicon oxynitride or a silicon-germanium oxynitride.
  • the dielectric material layer 20 can include a high dielectric constant (high-k) dielectric material.
  • a high-k dielectric material refers to a dielectric material having a dielectric constant greater than 7.9.
  • the high-k dielectric material of the dielectric material layer 20 can include a dielectric metal oxide.
  • Exemplary high-k dielectric materials that can be employed for dielectric material layer 20 include, but are not limited to, HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , TiO 2 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , HfO x N y , ZrO x N y , La 2 O x N y , Al 2 O x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y 2 O x N y , a silicate thereof, and an alloy thereof.
  • the high-k dielectric material can be selected from HfO 2 , ZrO 2 , and TiO 2 .
  • the first high-k dielectric material can be HfO 2 .
  • the first high-k dielectric material can be deposited by methods well known in the art including, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), atomic layer deposition (ALD), etc.
  • the dielectric material layer 20 can include a dielectric material that is known to be suitable for an interlayer dielectric (ILD) material.
  • the dielectric material layer 20 can include porous or non-porous organosilicate glass (OSG), doped silicate glass, undoped silicate glass, silicon nitride, silicon oxynitride, nitrogen-doped organosilicate glass, or combinations thereof.
  • the dielectric constant of the material of the dielectric material layer 20 can be in a range from 2.0 to 3.9.
  • the interlayer dielectric material can be deposited, for example, by chemical vapor deposition, spin-coating, or a combination thereof.
  • the thickness of the dielectric material layer 20 can be in a range from 10 nm to 300 nm, although lesser and greater thicknesses can also be employed.
  • the metallic material layer 30 can include an elemental metal, an alloy of at least two elemental metals, a compound of at least one metal and nitrogen, a compound of at least one metal and carbon, or a stack thereof.
  • the metallic material layer 30 can include any elemental metal, which can be an elemental transition metal, a Lanthanide, an Actinide, an alkali metal, or an alkaline earth metal.
  • the metallic material layer 30 can include an intermetallic alloy of at least two elemental metals.
  • the metallic material layer includes a metallic nitride, a metallic carbide, or an alloy or a stack thereof.
  • Exemplary metallic nitride materials that can be employed for the metallic material layer 30 include, but are not limited to, titanium nitride, tantalum nitride, tungsten nitride, aluminum nitride, yttrium nitride, zirconium nitride, vanadium nitride, niobium nitride, and other nitrides of at least one metallic element.
  • Exemplary metallic carbide materials that can be employed for the metallic material layer 30 include, but are not limited to, titanium carbide, tantalum carbide, tungsten carbide, zirconium carbide, vanadium carbide, niobium carbide, hafnium carbide, chromium carbide, molybdenum carbide, and other carbides of at least one metallic element.
  • the metallic material layer 30 can include a stack of multiple metallic layers having different compositions.
  • the metallic material layer 30 can be deposited, for example, by physical vapor deposition (sputtering), chemical vapor deposition, atomic layer deposition, or a combination thereof.
  • the thickness of the metallic material layer 30 can be in a range from 1 nm to 30 nm, although lesser and greater thicknesses can also be employed.
  • the first organic planarization layer 40 includes an organic planarization material as known in the art.
  • the organic planarization material of the first organic planarization layer 40 is herein referred to as a first organic planarization material.
  • the first organic planarization layer 40 can include a non-photosensitive organic polymer material.
  • a “non-photosensitive” material refers to a material that does not change chemical property upon irradiation for lithographic exposure employing a conventional light wavelength and a conventional dose level for exposure as known in the art.
  • Exemplary materials that can be employed for the first organic planarization layer 40 include ODL-102, commercially available from ShinEtsu Chemical Co. Ltd.; HM8006 and HM8014, commercially available from JSR Corporation; and CHM701B, commercially available from Cheil Chemical Co. Ltd.
  • the first organic planarization layer 40 can be formed, for example, by a spin-on coating.
  • the thickness of the first organic planarization layer 40 can be in a range from 30 nm to 600 nm, although lesser and greater thicknesses can also be employed.
  • the non-metallic hard mask layer 50 includes a non-metallic non-photosensitive material.
  • the non-metallic hard mask layer 50 can include a dielectric oxide, a dielectric nitride, or a dielectric oxynitride including a group IV element.
  • the non-metallic hard mask layer 50 can include a silicon oxide material, a silicon nitride material, or a silicon oxynitride material.
  • the non-metallic hard mask layer 50 can be deposited by chemical vapor deposition, atomic layer deposition, spin coating, or a combination thereof.
  • the non-metallic hard mask layer 50 can include a nitrogen-containing organosilicate glass (OSG), which includes Si, C, O, H, and N.
  • OSG nitrogen-containing organosilicate glass
  • An exemplary material for a nitrogen-containing OSG is NBLoKTM available from Applied Materials, Inc.
  • the non-metallic hard mask layer 50 can include a silicon-containing antireflective coating (Si-ARC) material as known in the art.
  • the Si-ARC material can be a polymer containing Si with organic units or halide bound to the silicon, which are generally polysiloxanes.
  • the Si-ARC material can include more than 30% in atomic concentration of silicon.
  • the Si-ARC material can be applied, for example, by spin coating, and can be cured at an elevated temperature around 220° C. during a post application bake (PAB) process.
  • PAB post application bake
  • the non-metallic hard mask layer 50 can include a dielectric metal oxide.
  • dielectric metal oxides include, but are not limited to, HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , TiO 2 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , HfO x N y , ZrO x N y , La 2 O x N y , Al 2 O x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y 2 O x N y , a silicate thereof, and an alloy thereof.
  • Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2.
  • the dielectric metal oxide material can be deposited by methods well known in the art including, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), atomic layer deposition (ALD), etc.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • MBD molecular beam deposition
  • PLD pulsed laser deposition
  • LSMCD liquid source misted chemical deposition
  • ALD atomic layer deposition
  • the thickness of the non-metallic hard mask layer 50 can be in a range from 1 nm to 30 nm, although lesser and greater thicknesses can also be employed. In one embodiment, the thickness of the non-metallic hard mask layer 50 can be in a range from 3 nm to 10 nm.
  • the patterned photoresist layer 57 includes a photoresist material.
  • the patterned photoresist layer 57 can be formed by forming a blanket photoresist material layer over the top surface of the non-metallic hard mask layer 50 by spin coating, lithographically exposing the blanket photoresist material layer by electromagnetic radiation or by an electron beam, and developing the lithographically exposed photoresist material layer.
  • the thickness of the blanket photoresist material layer can be in a range from 50 nm to 1,000 nm, although lesser and greater thicknesses can also be employed.
  • the lithographic exposure of the blanket photoresist layer can be performed by deep ultraviolet (DUV) lithography, mid-ultraviolet lithography (MUV), grayscale lithography, electron beam lithography, or a combination thereof.
  • DUV deep ultraviolet
  • UUV mid-ultraviolet lithography
  • the development process can remove lithographically exposed portions selective to lithographically unexposed portions of the photoresist material, or can remove lithographically unexposed portions of the photoresist material selective to the lithographically exposed portions of the photoresist material.
  • the patterned photoresist layer 57 includes at least one opening therein. A portion of the top surface of the non-metallic hard mask layer 50 is physically exposed underneath each opening in the patterned photoresist layer 57 .
  • the pattern of the opening in the patterned photoresist layer 57 corresponds to the area from which removal of the metallic material layer 30 is desired.
  • the area of the remaining portions of the patterned photoresist layer 57 corresponds to the area in which preservation of the metallic material layer 30 is desired after patterning of the metallic material layer 30 .
  • the pattern in the patterned photoresist layer 57 is transferred through the stack of the non-metallic hard mask layer 50 , the first organic planarization layer 40 , and the metallic material layer 30 by at least one etch.
  • at least one anisotropic etch can be employed among the at least one etch that transfers the pattern in the patterned photoresist layer 57 is transferred through the stack of the non-metallic hard mask layer 50 , the first organic planarization layer 40 , and the metallic material layer 30 .
  • a cavity 59 is formed though the non-metallic hard mask layer 50 , the first organic planarization layer 40 , and the metallic material layer 30 .
  • a top surface of the dielectric material layer 20 is physically exposed underneath the cavity 59 .
  • the non-metallic hard mask layer 50 can be etched, for example, by an anisotropic etch or an isotropic etch.
  • the etch chemistry for etching the non-metallic hard mask layer 50 can be selected based on the material of the non-metallic hard mask layer as known in the art.
  • the patterned photoresist layer 57 is employed as an etch mask during the etching of unmasked portions of the non-metallic hard mask layer 50 .
  • the non-metallic hard mask layer 50 can be etched by a reactive ion etch, which is an anisotropic etch.
  • the non-metallic hard mask layer 50 can be etched by a wet etch, which is an isotropic etch.
  • the portion(s) of the first organic planarization layer 40 underlying each opening in the patterned photoresist layer 57 can be etched by another etch.
  • the first organic planarization layer 40 can be etched employing an anisotropic etch process, which forms vertical sidewalls in the first organic planarization layer 40 as the etch process proceeds.
  • the patterned photoresist layer 57 can be vertically recessed during the etching of the first organic planarization layer 40 .
  • a cavity 59 is formed in the first organic planarization layer 40 underneath each opening in the patterned photoresist layer 57 .
  • the patterned photoresist layer 57 can be completely consumed before, or at the time of, the cavity 59 reaching the interface between the first organic planarization layer 40 and the metallic material layer.
  • the sidewalls of the non-metallic hard mask layer 50 and the sidewalls of the first organic planarization layer 40 can be vertically coincident among one another after formation of the cavity 59 .
  • a first surface and a second surface are vertically coincident with each other if the first surface overlies, or underlies, the second surface and a vertical plane including the first surface and the second surface exists.
  • the physically exposed portion of the metallic material layer 30 underlying the cavity 59 can be subsequently removed by another etch, which can be an isotropic etch or an anisotropic etch.
  • the physical exposed portion of the metallic material layer 30 can be removed by a wet etch.
  • the chemistry of the etch process employed to etch the metallic material layer 30 can be selected to avoid damaging the material of the dielectric material layer 20 . Suitable etch chemistries known in the art can be employed to etch the metallic material layer 30 while minimizing collateral etching of the dielectric material layer 20 . Methods for selective wet etching of metal nitrides can be found, for example, in United States Patent Application No. 2006/0226122A1.
  • the metallic material layer 30 can be etched selective to the dielectric oxide material by a wet etch employing a mixture of hydrogen peroxide and ethylenediaminetetraacetic acid.
  • a 1:1 mixture of hydrogen peroxide and ethylenediaminetetraacetic acid elevated to a temperature of 60° C. or higher can be employed to etch a titanium nitride film selective to a dielectric metal oxide material.
  • a second organic planarization layer 60 is deposited in the cavity 59 (See FIG. 2 ) and over the non-metallic hard mask layer 50 .
  • the second organic planarization layer 60 is deposited into the cavity 59 and over the non-metallic hard mask layer 50 .
  • the second organic planarization layer 60 can be formed directly on a top surface and sidewalls of the remaining portion of the non-metallic hard mask layer 50 that remains after the at least one anisotropic etch that forms the cavity 59 and the etch process that forms an opening in the metallic material layer 30 .
  • the second organic planarization layer 60 can include any organic planarization material that can be employed as the first organic planarization layer 40 .
  • the organic planarization material of the second organic planarization layer 60 is herein referred to as a second organic planarization material.
  • the first organic planarization material and the second organic planarization material may, or may not, be the same as the organic planarization material of the first organic planarization material layer 40 .
  • each of the first and second organic planarization layers ( 40 , 60 ) can include a non-photosensitive organic polymer material.
  • the non-photosensitive organic polymer material of the second organic planarization layer 60 can be selected independent of the non-photosensitive organic polymer material of the first organic planarization layer 40 .
  • the second organic planarization layer 60 can be applied, for example, by spin coating of an organic planarization material.
  • a dimple may be present on the top surface of the second organic planarization layer 60 over the volume of each cavity 59 (See FIG. 2 ) that is filled with the organic planarization material of the second organic planarization layer 60 .
  • the thickness of the second organic planarization layer 60 as measured above the top surface of the non-metallic hard mask layer 50 , may be in a range from 1 nm to 300 nm, although lesser and greater thicknesses can also be employed.
  • the topmost surface of the second organic planarization layer 60 may be formed below the horizontal plane including the top surface of the non-metallic hard mask layer 50 .
  • the second organic planarization layer 60 can be employed to minimize additional collateral etching of the dielectric material layer 20 after the patterning of the metallic material layer 30 and during the removal of the non-metallic hard mask layer 59 , and the first organic planarization layer 40 .
  • the organic planarization material of the second organic planarization layer 60 that is present on the top surface of the dielectric material layer 20 protects the dielectric material layer 20 during subsequent processing steps for removal of the non-metallic hard mask layer 59 , and during an initial portion of the processing step for removal of the first organic planarization layer 40 .
  • an upper portion of the second organic planarization layer 60 is recessed by an etch process or by an ashing process such that the recessed top surface of the second organic planarization layer 60 is present below the horizontal plane including the top surface of the non-metallic hard mask layer 50 .
  • the upper portion of the second organic planarization layer 60 can be removed by a dry etch.
  • the dry etch can be an anisotropic etch such as a reactive ion etch, or an isotropic etch as chemical downstream etch.
  • the upper portion of the second organic planarization layer 60 can be removed by an ashing process, in which the organic planarization material of the second organic planarization layer 60 combines with oxygen, becomes volatilized, and is removed in a gas phase out of a processing chamber.
  • the recessing of the upper portion of the second organic planarization layer 60 can be performed employing an etch process that is selective to the material of the non-metallic hard mask layer 50 . In another embodiment, the recessing of the upper portion of the second organic planarization layer 60 can be performed employing an etch process that is not selective to the material of the non-metallic hard mask layer 50 .
  • the second planarization layer 60 partially fills each cavity within the vertical stack of the metallic material layer 30 , the first organic planarization layer 40 , and the non-metallic hard mask layer 50 (if present).
  • the top surface of the remaining portion of the second organic planarization layer 60 within each cavity may have a concave top surface due to a dimple in the top surface of the second organic planarization layer 60 as formed at the processing step of FIG. 3 and due to the geometrical effects of the cavity 59 during the recessing of the second organic planarization layer 60 .
  • the dielectric mask layer 50 if not collaterally etched during the recessing of the second organic planarization layer 60 at the processing step of FIG. 4 , can be removed.
  • the removal of the dielectric mask layer 50 can be performed by an etch, which can be an anisotropic etch such as a reactive ion etch or an isotropic etch such as a wet etch.
  • the etch process that is employed to remove the dielectric mask layer 50 may, or may not, be selective to the materials of the first organic planarization layer 40 and/or the second organic planarization layer 60 .
  • a suitable etch chemistry may be employed to remove the non-metallic hard mask layer 50 as known in the art.
  • the presence of the organic planarization material of the second organic planarization layer 60 on the top surface of the dielectric material layer 20 provides protection for the top surface of the dielectric material layer 20 underlying the cavity 59 from collateral etching during the removal of the non-metallic hard mask layer 50 .
  • the remaining lower portion of the second organic planarization layer 60 and the first organic planarization layer 40 are removed selective to the dielectric material in the dielectric material layer 20 .
  • the lower portion of the second organic planarization layer 60 and the first organic planarization layer 40 are removed simultaneously employing a same etch process.
  • the lower portion of the second organic planarization layer 60 and the first organic planarization layer 40 can be removed by an ashing process, in which the organic planarization materials of the first and second organic planarization layers ( 40 , 60 ) combine with oxygen, become volatilized, and are removed in a gas phase out of a processing chamber.
  • the lower portion of the second organic planarization layer 60 and the first organic planarization layer 40 can be removed by a dry etch.
  • the dry etch can be an anisotropic etch such as a reactive ion etch, or an isotropic etch as chemical downstream etch.
  • the simultaneous removal of the lower portion of the second organic planarization layer 60 and the first organic planarization layer 40 can be performed employing a process that is selective to the material of the dielectric material layer 20 .
  • the height of the recessed top surface of the second organic planarization layer 60 during the recess etch at the processing step of FIG. 4 can be selected such that the top surface of the dielectric material layer 20 and the top surface of the metallic material layer 30 become physically exposed simultaneously, or with minimal differences in time.
  • the overetch time needed to remove bottommost portions of the first and second organic planarization layers ( 40 , 60 ) can be minimized, thereby minimizing any collateral damage to the physically exposed top surface of the dielectric material layer 20 .
  • a surface clean process may be performed to remove any residual material derived from the first and second organic planarization layers ( 40 , 60 ).
  • a wet clean employing the SC1 etch chemistry can be performed to remove organic residues from the top surfaces of the dielectric material layer 20 and the metallic material layer 30 .
  • the SC1 etch chemistry can employ, for example, a 1:1:5 solution of 27 volume % of ammonium hydroxide in water, 30 volume % of hydrogen peroxide in water, and deionized water at a temperature range about 80° C. The duration of the wet etch can be optimized based on the thickness of the metallic material layer 30 .
  • Additional material stacks can be subsequently deposited on the exemplary structure illustrated in FIG. 6 .
  • Such additional material stacks can include another metallic material layer and/or a doped or undoped semiconductor material layer and/or another dielectric material layer as known in the art.
  • a vertical cross-sectional view of a variation of the exemplary structure is shown at the processing step corresponding to the processing step of FIG. 3 for the exemplary structure.
  • the patterned photoresist layer 57 may not be completely consumed during the processing steps of FIG. 2 .
  • the second organic planarization layer 60 is deposited into the cavity 59 and directly on a top surface and sidewalls of the patterned photoresist layer 57 , the sidewalls of the non-metallic hard mask layer 50 , the sidewalls of the first organic planarization layer 40 , the sidewalls of the metallic material layer 30 , and the top surface of the dielectric material layer 20 .
  • FIGS. 4-6 can be performed to provide the exemplary structure illustrated in FIG. 6 .
  • the remaining portions of the patterned photoresist layer 57 can be removed collaterally during the processing step of FIG. 4 , i.e., during the recessing of the second organic planarization layer 60 .
  • the various methods of the present disclosure can be employed to provide a dielectric material layer 20 in contact with a bottom surface of a patterned metallic material layer 30 while minimizing structural or chemical damages to the physically exposed portions of the dielectric material layer 20 .
  • the methods of the present disclosure can be advantageously employed in any device structure that requires a dielectric material layer with structural and chemical integrity, i.e., a dielectric material layer with no, or minimal, structural and chemical changes in the dielectric material in regions that do not contact the metallic material layer 30 .
  • An exemplary application of the methods of the present disclosure is patterning of a work function material layer formed directly on a top surface of a high-k dielectric material layer during formation of gate electrodes for field effect transistors.
  • the high-k dielectric material layer can be the dielectric material layer 20 of the present disclosure
  • the work function material layer can be the metallic material layer 30 of the present disclosure.
  • the high-k dielectric material layer can be a predominant portion of gate dielectrics for the field effect transistors. As such, any structural or chemical damage to the high-k dielectric material layer can be detrimental to performance and/or reliability of the field effect transistors that employ the high-k dielectric material layer as gate dielectrics.
  • the methods of the present disclosure enhances the performance and/or the reliability of semiconductor devices employing the dielectric material layer 20 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A stack of a dielectric material layer and a metallic material layer are formed on a substrate. A first organic planarization layer, a non-metallic hard mask layer, and a photoresist layer are sequentially deposited over the metallic material layer. The photoresist layer is lithographically patterned, and the pattern in the photoresist layer is transferred through the non-metallic hard mask layer, the first organic planarization layer, and the metallic material layer to form a cavity. A second organic planarization layer is deposited within the cavity and over remaining portions of the photoresist layer. The second organic planarization layer and the photoresist layer are recessed, and the non-metallic hard mask layer is subsequently removed. Remaining portions of the first and second organic planarization layers are simultaneously removed to provide physically exposed surfaces of the patterned metallic material layer and a top surface of the dielectric material layer.

Description

    BACKGROUND
  • The present disclosure relates to methods of patterning a metallic material layer on a dielectric material layer and structures for effecting the same.
  • Patterning of a metallic material layer overlying a dielectric layer can result in collateral damages of the underlying dielectric layer. In case the functionality of the dielectric layer is affected by collateral damages as in the case of a gate dielectric layer, minimizing the collateral damages during the processing steps is critical in providing high performance and/or reliability in the device employing the dielectric layer.
  • For example, a patterning process for a stack of a high dielectric constant (high-k) gate dielectric layer including a dielectric metal oxide and a metallic material layer can employ an etch mask stack including a second metallic material layer in addition to a photoresist layer. While the second metallic material layer can be advantageously employed to generate a high fidelity replica of the pattern in the photoresist layer, removal of the second metallic material layer can result in collateral etch of the high-k gate dielectric layer and metallic contamination in a processing tool. Further, removal of additional materials in the etch mask stack can result in further collateral etching of the metallic material layer. Thus, a method is desired for patterning a metallic material layer while minimizing collateral etches of an underlying dielectric layer and avoiding metallic contamination.
    • SUMMARY
  • A stack of a dielectric material layer and a metallic material layer are formed on a substrate. A first organic planarization layer, a non-metallic hard mask layer, and a photoresist layer are sequentially deposited over the metallic material layer. The photoresist layer is lithographically patterned, and the pattern in the photoresist layer is transferred through the non-metallic hard mask layer, the first organic planarization layer, and the metallic material layer to form a cavity. A second organic planarization layer is deposited within the cavity and over remaining portions of the photoresist layer. The second organic planarization layer and the photoresist layer are recessed, and the non-metallic hard mask layer is subsequently removed. Remaining portions of the first and second organic planarization layers are simultaneously removed to provide physically exposed surfaces of the patterned metallic material layer and a top surface of the dielectric material layer.
  • According to an aspect of the present disclosure, a method of forming a patterned structure is provided. A vertical stack is formed over a dielectric material layer on a substrate. The vertical stack includes, from bottom to top, a metallic material layer, a first organic planarization layer, and a non-metallic hard mask layer. A cavity is formed though the non-metallic hard mask layer, the first organic planarization layer, and the metallic material layer. A top surface of the dielectric material layer is physically exposed underneath the cavity. A second organic planarization layer is applied in the cavity and over the non-metallic hard mask layer. An upper portion of the second organic planarization layer is recessed. The non-metallic hard mask layer is removed. A lower portion of the second organic planarization layer and the first organic planarization layer are removed. The top surface of the dielectric material layer is physically exposed again.
    • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • FIG. 1 is a vertical cross-sectional view of an exemplary structure after formation of a stack including a dielectric material layer, a metallic material layer, a first organic planarization layer, a dielectric mask layer, and a patterned photoresist layer on a substrate according to an embodiment of the present disclosure.
  • FIG. 2 is a vertical cross-sectional view of the exemplary structure after transfer of the pattern of in the photoresist layer into the dielectric mask layer, the first organic planarization layer, and the first metallic material layer by a set of at least one etch according to an embodiment of the present disclosure.
  • FIG. 3 is a vertical cross-sectional view of the exemplary structure after application of a second organic planarization layer according to an embodiment of the present disclosure.
  • FIG. 4 is a vertical cross-sectional view of the exemplary structure after recessing the second organic planarization layer and collateral removal of any remaining portion of the photoresist layer according to an embodiment of the present disclosure.
  • FIG. 5 is a vertical cross-sectional view of the exemplary structure after removal of the dielectric mask layer according to an embodiment of the present disclosure.
  • FIG. 6 is a vertical cross-sectional view of the exemplary structure after removal of the first and second organic planarization layers according to an embodiment of the present disclosure.
  • FIG. 7 is a vertical cross-sectional view of a variation of the exemplary structure after application of a second organic planarization layer according to an embodiment of the present disclosure.
    •  DETAILED DESCRIPTION
  • As stated above, the present disclosure relates to methods of patterning a metallic material layer on a dielectric material layer and structures for effecting the same, which are now described in detail with accompanying figures. It is noted that like and corresponding elements are referred to by like reference numerals. The drawings are not in scale. As used herein, ordinals such as “first” and “second” are employed merely to distinguish similar elements, and different ordinals may be employed to designate a same element in the specification and/or claims.
  • Referring to FIG. 1, an exemplary structure according to an embodiment of the present disclosure includes a material stack formed on a substrate 10. The material stack includes, from bottom to top, of a dielectric material layer 20, a metallic material layer 30, a first organic planarization layer 40, a dielectric mask layer 50, and a patterned photoresist layer 57.
  • The substrate 10 can include any solid material. The substrate 10 can include at least one semiconductor material, at least one conductive material, at least one dielectric material, or a combination or a stack thereof. Semiconductor materials that can be included in the substrate 10 include, but are not limited to, an elemental semiconductor material such as silicon or germanium; an alloy of Group IV elements such as a silicon-germanium alloy, a silicon-carbon alloy, and a silicon-germanium-carbon alloy; a compound semiconductor material; an organic semiconductor material; and combinations thereof. Metallic material that can be included in the substrate 10 include, but are not limited to, an elemental metal, an intermetallic alloy, a conductive metallic nitride, a conductive metallic carbide, and combinations and alloys thereof. Dielectric materials that can be included in the substrate 10 include, but are not limited to, a dielectric oxide of at least one semiconductor element such as silicon oxide, a dielectric nitride of at least one semiconductor element such as silicon nitride, a dielectric metal oxide, a dielectric metal nitride, and combinations and alloys thereof.
  • In one embodiment, the substrate 10 can be sufficiently thick to provide mechanical support for the material stack thereupon. In one embodiment, the thickness of the substrate 10 can be in a range from 30 microns to 1 mm, although lesser and greater thicknesses can also be employed.
  • In one embodiment, the topmost portion of the substrate 10 can include a semiconductor layer embedding various doped semiconductor material portions. For example, the substrate 10 can include source and drain regions of field effect transistors that are formed in a semiconductor material portion. The semiconductor material portion can be a planar semiconductor portion laterally surrounded by a shallow trench isolation structure (not shown) and having a top surface that is coplanar with the topmost surface of the substrate 10, or can be a semiconductor fin as known in the art.
  • In one embodiment, the topmost portion of the substrate 10 can include a metal interconnect structure including at least one interlayer dielectric (ILD) material layer and at least one metal line structure and/or at least one metal via structure as known in the art. In this case, the topmost portions of the substrate can include a dielectric material such as silicon oxide, silicon nitride, porous or non-porous organosilicate glass, or combinations thereof. Further, at least one metal line structure and/or at least one metal via structure, if present, can include a metallic material such as copper, aluminum, tungsten, a metallic nitride, a metallic carbide, or a combination thereof.
  • The dielectric material layer 20 can include any dielectric material. In one embodiment, the dielectric material layer 20 can include a dielectric material that is known to be suitable for a gate dielectric of a field effect transistor. The thickness of the dielectric material layer 20 can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed. In one embodiment, the dielectric material layer 20 can include a dielectric oxide of at least one semiconductor element such as silicon oxide or a silicon-germanium oxide, or a dielectric oxynitride of at least one semiconductor element such as silicon oxynitride or a silicon-germanium oxynitride.
  • In another embodiment, the dielectric material layer 20 can include a high dielectric constant (high-k) dielectric material. As used herein, a high-k dielectric material refers to a dielectric material having a dielectric constant greater than 7.9. In one embodiment, the high-k dielectric material of the dielectric material layer 20 can include a dielectric metal oxide. Exemplary high-k dielectric materials that can be employed for dielectric material layer 20 include, but are not limited to, HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, HfOxNy, ZrOxNy, La2OxNy, Al2OxNy, TiOxNy, SrTiOxNy, LaAlOxNy, Y2OxNy, a silicate thereof, and an alloy thereof. Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2. In one embodiment, the high-k dielectric material can be selected from HfO2, ZrO2, and TiO2. In one embodiment, the first high-k dielectric material can be HfO2. The first high-k dielectric material can be deposited by methods well known in the art including, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), atomic layer deposition (ALD), etc.
  • In one embodiment, the dielectric material layer 20 can include a dielectric material that is known to be suitable for an interlayer dielectric (ILD) material. For example, the dielectric material layer 20 can include porous or non-porous organosilicate glass (OSG), doped silicate glass, undoped silicate glass, silicon nitride, silicon oxynitride, nitrogen-doped organosilicate glass, or combinations thereof. In this case, the dielectric constant of the material of the dielectric material layer 20 can be in a range from 2.0 to 3.9. The interlayer dielectric material can be deposited, for example, by chemical vapor deposition, spin-coating, or a combination thereof. The thickness of the dielectric material layer 20 can be in a range from 10 nm to 300 nm, although lesser and greater thicknesses can also be employed.
  • The metallic material layer 30 can include an elemental metal, an alloy of at least two elemental metals, a compound of at least one metal and nitrogen, a compound of at least one metal and carbon, or a stack thereof. In one embodiment, the metallic material layer 30 can include any elemental metal, which can be an elemental transition metal, a Lanthanide, an Actinide, an alkali metal, or an alkaline earth metal. In another embodiment, the metallic material layer 30 can include an intermetallic alloy of at least two elemental metals. In one embodiment, the metallic material layer includes a metallic nitride, a metallic carbide, or an alloy or a stack thereof. Exemplary metallic nitride materials that can be employed for the metallic material layer 30 include, but are not limited to, titanium nitride, tantalum nitride, tungsten nitride, aluminum nitride, yttrium nitride, zirconium nitride, vanadium nitride, niobium nitride, and other nitrides of at least one metallic element. Exemplary metallic carbide materials that can be employed for the metallic material layer 30 include, but are not limited to, titanium carbide, tantalum carbide, tungsten carbide, zirconium carbide, vanadium carbide, niobium carbide, hafnium carbide, chromium carbide, molybdenum carbide, and other carbides of at least one metallic element. In one embodiment, the metallic material layer 30 can include a stack of multiple metallic layers having different compositions.
  • The metallic material layer 30 can be deposited, for example, by physical vapor deposition (sputtering), chemical vapor deposition, atomic layer deposition, or a combination thereof. The thickness of the metallic material layer 30 can be in a range from 1 nm to 30 nm, although lesser and greater thicknesses can also be employed.
  • The first organic planarization layer 40 includes an organic planarization material as known in the art. The organic planarization material of the first organic planarization layer 40 is herein referred to as a first organic planarization material. In one embodiment, the first organic planarization layer 40 can include a non-photosensitive organic polymer material. As used herein, a “non-photosensitive” material refers to a material that does not change chemical property upon irradiation for lithographic exposure employing a conventional light wavelength and a conventional dose level for exposure as known in the art. Exemplary materials that can be employed for the first organic planarization layer 40 include ODL-102, commercially available from ShinEtsu Chemical Co. Ltd.; HM8006 and HM8014, commercially available from JSR Corporation; and CHM701B, commercially available from Cheil Chemical Co. Ltd.
  • The first organic planarization layer 40 can be formed, for example, by a spin-on coating. The thickness of the first organic planarization layer 40 can be in a range from 30 nm to 600 nm, although lesser and greater thicknesses can also be employed.
  • The non-metallic hard mask layer 50 includes a non-metallic non-photosensitive material. In one embodiment, the non-metallic hard mask layer 50 can include a dielectric oxide, a dielectric nitride, or a dielectric oxynitride including a group IV element. For example, the non-metallic hard mask layer 50 can include a silicon oxide material, a silicon nitride material, or a silicon oxynitride material. In this case, the non-metallic hard mask layer 50 can be deposited by chemical vapor deposition, atomic layer deposition, spin coating, or a combination thereof.
  • In another embodiment, the non-metallic hard mask layer 50 can include a nitrogen-containing organosilicate glass (OSG), which includes Si, C, O, H, and N. An exemplary material for a nitrogen-containing OSG is NBLoK™ available from Applied Materials, Inc.
  • In yet another embodiment, the non-metallic hard mask layer 50 can include a silicon-containing antireflective coating (Si-ARC) material as known in the art. The Si-ARC material can be a polymer containing Si with organic units or halide bound to the silicon, which are generally polysiloxanes. The Si-ARC material can include more than 30% in atomic concentration of silicon. The Si-ARC material can be applied, for example, by spin coating, and can be cured at an elevated temperature around 220° C. during a post application bake (PAB) process.
  • In still another embodiment, the non-metallic hard mask layer 50 can include a dielectric metal oxide. Exemplary dielectric metal oxides include, but are not limited to, HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, HfOxNy, ZrOxNy, La2OxNy, Al2OxNy, TiOxNy, SrTiOxNy, LaAlOxNy, Y2OxNy, a silicate thereof, and an alloy thereof. Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2. The dielectric metal oxide material can be deposited by methods well known in the art including, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), atomic layer deposition (ALD), etc.
  • The thickness of the non-metallic hard mask layer 50 can be in a range from 1 nm to 30 nm, although lesser and greater thicknesses can also be employed. In one embodiment, the thickness of the non-metallic hard mask layer 50 can be in a range from 3 nm to 10 nm.
  • The patterned photoresist layer 57 includes a photoresist material. The patterned photoresist layer 57 can be formed by forming a blanket photoresist material layer over the top surface of the non-metallic hard mask layer 50 by spin coating, lithographically exposing the blanket photoresist material layer by electromagnetic radiation or by an electron beam, and developing the lithographically exposed photoresist material layer. The thickness of the blanket photoresist material layer can be in a range from 50 nm to 1,000 nm, although lesser and greater thicknesses can also be employed. The lithographic exposure of the blanket photoresist layer can be performed by deep ultraviolet (DUV) lithography, mid-ultraviolet lithography (MUV), grayscale lithography, electron beam lithography, or a combination thereof. Depending on the nature of the photoresist material, the development process can remove lithographically exposed portions selective to lithographically unexposed portions of the photoresist material, or can remove lithographically unexposed portions of the photoresist material selective to the lithographically exposed portions of the photoresist material.
  • The patterned photoresist layer 57 includes at least one opening therein. A portion of the top surface of the non-metallic hard mask layer 50 is physically exposed underneath each opening in the patterned photoresist layer 57. The pattern of the opening in the patterned photoresist layer 57 corresponds to the area from which removal of the metallic material layer 30 is desired. The area of the remaining portions of the patterned photoresist layer 57 corresponds to the area in which preservation of the metallic material layer 30 is desired after patterning of the metallic material layer 30.
  • Referring to FIG. 2, the pattern in the patterned photoresist layer 57 is transferred through the stack of the non-metallic hard mask layer 50, the first organic planarization layer 40, and the metallic material layer 30 by at least one etch. In one embodiment, at least one anisotropic etch can be employed among the at least one etch that transfers the pattern in the patterned photoresist layer 57 is transferred through the stack of the non-metallic hard mask layer 50, the first organic planarization layer 40, and the metallic material layer 30. A cavity 59 is formed though the non-metallic hard mask layer 50, the first organic planarization layer 40, and the metallic material layer 30. A top surface of the dielectric material layer 20 is physically exposed underneath the cavity 59.
  • The non-metallic hard mask layer 50 can be etched, for example, by an anisotropic etch or an isotropic etch. The etch chemistry for etching the non-metallic hard mask layer 50 can be selected based on the material of the non-metallic hard mask layer as known in the art. The patterned photoresist layer 57 is employed as an etch mask during the etching of unmasked portions of the non-metallic hard mask layer 50. In one embodiment, the non-metallic hard mask layer 50 can be etched by a reactive ion etch, which is an anisotropic etch. In another embodiment, the non-metallic hard mask layer 50 can be etched by a wet etch, which is an isotropic etch.
  • Subsequently, the portion(s) of the first organic planarization layer 40 underlying each opening in the patterned photoresist layer 57 can be etched by another etch. In one embodiment, the first organic planarization layer 40 can be etched employing an anisotropic etch process, which forms vertical sidewalls in the first organic planarization layer 40 as the etch process proceeds. The patterned photoresist layer 57 can be vertically recessed during the etching of the first organic planarization layer 40. A cavity 59 is formed in the first organic planarization layer 40 underneath each opening in the patterned photoresist layer 57. In one embodiment, the patterned photoresist layer 57 can be completely consumed before, or at the time of, the cavity 59 reaching the interface between the first organic planarization layer 40 and the metallic material layer. In one embodiment, the sidewalls of the non-metallic hard mask layer 50 and the sidewalls of the first organic planarization layer 40 can be vertically coincident among one another after formation of the cavity 59. As used herein, a first surface and a second surface are vertically coincident with each other if the first surface overlies, or underlies, the second surface and a vertical plane including the first surface and the second surface exists.
  • The physically exposed portion of the metallic material layer 30 underlying the cavity 59 can be subsequently removed by another etch, which can be an isotropic etch or an anisotropic etch. In one embodiment, the physical exposed portion of the metallic material layer 30 can be removed by a wet etch. In one embodiment, the chemistry of the etch process employed to etch the metallic material layer 30 can be selected to avoid damaging the material of the dielectric material layer 20. Suitable etch chemistries known in the art can be employed to etch the metallic material layer 30 while minimizing collateral etching of the dielectric material layer 20. Methods for selective wet etching of metal nitrides can be found, for example, in United States Patent Application No. 2006/0226122A1. In another example, if the metallic material layer 30 includes titanium nitride and if the dielectric material layer 20 includes a dielectric metal oxide, the metallic material layer 30 can be etched selective to the dielectric oxide material by a wet etch employing a mixture of hydrogen peroxide and ethylenediaminetetraacetic acid. In an illustrative example, a 1:1 mixture of hydrogen peroxide and ethylenediaminetetraacetic acid elevated to a temperature of 60° C. or higher can be employed to etch a titanium nitride film selective to a dielectric metal oxide material.
  • Referring to FIG. 3, a second organic planarization layer 60 is deposited in the cavity 59 (See FIG. 2) and over the non-metallic hard mask layer 50. Specifically, the second organic planarization layer 60 is deposited into the cavity 59 and over the non-metallic hard mask layer 50. The second organic planarization layer 60 can be formed directly on a top surface and sidewalls of the remaining portion of the non-metallic hard mask layer 50 that remains after the at least one anisotropic etch that forms the cavity 59 and the etch process that forms an opening in the metallic material layer 30.
  • The second organic planarization layer 60 can include any organic planarization material that can be employed as the first organic planarization layer 40. The organic planarization material of the second organic planarization layer 60 is herein referred to as a second organic planarization material. The first organic planarization material and the second organic planarization material may, or may not, be the same as the organic planarization material of the first organic planarization material layer 40. In one embodiment, each of the first and second organic planarization layers (40, 60) can include a non-photosensitive organic polymer material. In this case, the non-photosensitive organic polymer material of the second organic planarization layer 60 can be selected independent of the non-photosensitive organic polymer material of the first organic planarization layer 40.
  • The second organic planarization layer 60 can be applied, for example, by spin coating of an organic planarization material. In one embodiment, a dimple may be present on the top surface of the second organic planarization layer 60 over the volume of each cavity 59 (See FIG. 2) that is filled with the organic planarization material of the second organic planarization layer 60. The thickness of the second organic planarization layer 60, as measured above the top surface of the non-metallic hard mask layer 50, may be in a range from 1 nm to 300 nm, although lesser and greater thicknesses can also be employed. Alternatively, the topmost surface of the second organic planarization layer 60 may be formed below the horizontal plane including the top surface of the non-metallic hard mask layer 50.
  • The second organic planarization layer 60 can be employed to minimize additional collateral etching of the dielectric material layer 20 after the patterning of the metallic material layer 30 and during the removal of the non-metallic hard mask layer 59, and the first organic planarization layer 40. Specifically, the organic planarization material of the second organic planarization layer 60 that is present on the top surface of the dielectric material layer 20 protects the dielectric material layer 20 during subsequent processing steps for removal of the non-metallic hard mask layer 59, and during an initial portion of the processing step for removal of the first organic planarization layer 40.
  • Referring to FIG. 4, an upper portion of the second organic planarization layer 60 is recessed by an etch process or by an ashing process such that the recessed top surface of the second organic planarization layer 60 is present below the horizontal plane including the top surface of the non-metallic hard mask layer 50.
  • In one embodiment, the upper portion of the second organic planarization layer 60 can be removed by a dry etch. The dry etch can be an anisotropic etch such as a reactive ion etch, or an isotropic etch as chemical downstream etch. In one embodiment, the upper portion of the second organic planarization layer 60 can be removed by an ashing process, in which the organic planarization material of the second organic planarization layer 60 combines with oxygen, becomes volatilized, and is removed in a gas phase out of a processing chamber.
  • In one embodiment, the recessing of the upper portion of the second organic planarization layer 60 can be performed employing an etch process that is selective to the material of the non-metallic hard mask layer 50. In another embodiment, the recessing of the upper portion of the second organic planarization layer 60 can be performed employing an etch process that is not selective to the material of the non-metallic hard mask layer 50.
  • The second planarization layer 60 partially fills each cavity within the vertical stack of the metallic material layer 30, the first organic planarization layer 40, and the non-metallic hard mask layer 50 (if present). In one embodiment, the top surface of the remaining portion of the second organic planarization layer 60 within each cavity may have a concave top surface due to a dimple in the top surface of the second organic planarization layer 60 as formed at the processing step of FIG. 3 and due to the geometrical effects of the cavity 59 during the recessing of the second organic planarization layer 60.
  • Referring to FIG. 5, the dielectric mask layer 50, if not collaterally etched during the recessing of the second organic planarization layer 60 at the processing step of FIG. 4, can be removed. The removal of the dielectric mask layer 50 can be performed by an etch, which can be an anisotropic etch such as a reactive ion etch or an isotropic etch such as a wet etch. The etch process that is employed to remove the dielectric mask layer 50 may, or may not, be selective to the materials of the first organic planarization layer 40 and/or the second organic planarization layer 60. A suitable etch chemistry may be employed to remove the non-metallic hard mask layer 50 as known in the art. The presence of the organic planarization material of the second organic planarization layer 60 on the top surface of the dielectric material layer 20 provides protection for the top surface of the dielectric material layer 20 underlying the cavity 59 from collateral etching during the removal of the non-metallic hard mask layer 50.
  • Referring to FIG. 6, the remaining lower portion of the second organic planarization layer 60 and the first organic planarization layer 40 are removed selective to the dielectric material in the dielectric material layer 20. The lower portion of the second organic planarization layer 60 and the first organic planarization layer 40 are removed simultaneously employing a same etch process.
  • In one embodiment, the lower portion of the second organic planarization layer 60 and the first organic planarization layer 40 can be removed by an ashing process, in which the organic planarization materials of the first and second organic planarization layers (40, 60) combine with oxygen, become volatilized, and are removed in a gas phase out of a processing chamber. In another embodiment, the lower portion of the second organic planarization layer 60 and the first organic planarization layer 40 can be removed by a dry etch. The dry etch can be an anisotropic etch such as a reactive ion etch, or an isotropic etch as chemical downstream etch.
  • The simultaneous removal of the lower portion of the second organic planarization layer 60 and the first organic planarization layer 40 can be performed employing a process that is selective to the material of the dielectric material layer 20. In one embodiment, the height of the recessed top surface of the second organic planarization layer 60 during the recess etch at the processing step of FIG. 4 can be selected such that the top surface of the dielectric material layer 20 and the top surface of the metallic material layer 30 become physically exposed simultaneously, or with minimal differences in time. In this case, the overetch time needed to remove bottommost portions of the first and second organic planarization layers (40, 60) can be minimized, thereby minimizing any collateral damage to the physically exposed top surface of the dielectric material layer 20.
  • After removal of the remaining lower portion of the second organic planarization layer 60 and the first organic planarization layer 40, the top surface of the dielectric material layer 20 within the region of the cavity 59 becomes physically exposed again. Optionally, a surface clean process may be performed to remove any residual material derived from the first and second organic planarization layers (40, 60). For example, a wet clean employing the SC1 etch chemistry can be performed to remove organic residues from the top surfaces of the dielectric material layer 20 and the metallic material layer 30. The SC1 etch chemistry can employ, for example, a 1:1:5 solution of 27 volume % of ammonium hydroxide in water, 30 volume % of hydrogen peroxide in water, and deionized water at a temperature range about 80° C. The duration of the wet etch can be optimized based on the thickness of the metallic material layer 30.
  • Additional material stacks can be subsequently deposited on the exemplary structure illustrated in FIG. 6. Such additional material stacks can include another metallic material layer and/or a doped or undoped semiconductor material layer and/or another dielectric material layer as known in the art.
  • Referring to FIG. 7, a vertical cross-sectional view of a variation of the exemplary structure is shown at the processing step corresponding to the processing step of FIG. 3 for the exemplary structure. In the variation of the exemplary structure, the patterned photoresist layer 57 may not be completely consumed during the processing steps of FIG. 2. The second organic planarization layer 60 is deposited into the cavity 59 and directly on a top surface and sidewalls of the patterned photoresist layer 57, the sidewalls of the non-metallic hard mask layer 50, the sidewalls of the first organic planarization layer 40, the sidewalls of the metallic material layer 30, and the top surface of the dielectric material layer 20.
  • Subsequently, the processing steps of FIGS. 4-6 can be performed to provide the exemplary structure illustrated in FIG. 6. The remaining portions of the patterned photoresist layer 57 can be removed collaterally during the processing step of FIG. 4, i.e., during the recessing of the second organic planarization layer 60.
  • The various methods of the present disclosure can be employed to provide a dielectric material layer 20 in contact with a bottom surface of a patterned metallic material layer 30 while minimizing structural or chemical damages to the physically exposed portions of the dielectric material layer 20. The methods of the present disclosure can be advantageously employed in any device structure that requires a dielectric material layer with structural and chemical integrity, i.e., a dielectric material layer with no, or minimal, structural and chemical changes in the dielectric material in regions that do not contact the metallic material layer 30.
  • An exemplary application of the methods of the present disclosure is patterning of a work function material layer formed directly on a top surface of a high-k dielectric material layer during formation of gate electrodes for field effect transistors. In this case, the high-k dielectric material layer can be the dielectric material layer 20 of the present disclosure, and the work function material layer can be the metallic material layer 30 of the present disclosure. The high-k dielectric material layer can be a predominant portion of gate dielectrics for the field effect transistors. As such, any structural or chemical damage to the high-k dielectric material layer can be detrimental to performance and/or reliability of the field effect transistors that employ the high-k dielectric material layer as gate dielectrics. By minimizing the collateral etching during the processing steps for removal of the non-metallic hard mask layer 50, the methods of the present disclosure enhances the performance and/or the reliability of semiconductor devices employing the dielectric material layer 20.
  • While the disclosure has been described in terms of specific embodiments, it is evident in view of the foregoing description that numerous alternatives, modifications and variations will be apparent to those skilled in the art. Each of the various embodiments of the present disclosure can be implemented alone, or in combination with any other embodiments of the present disclosure unless expressly disclosed otherwise or otherwise impossible as would be known to one of ordinary skill in the art. Accordingly, the disclosure is intended to encompass all such alternatives, modifications and variations which fall within the scope and spirit of the disclosure and the following claims.

Claims (20)

What is claimed is:
1. A method of forming a patterned structure comprising:
forming a vertical stack including, from bottom to top, a metallic material layer, a first organic planarization layer, and a non-metallic hard mask layer over a dielectric material layer on a substrate;
forming a cavity though said non-metallic hard mask layer, said first organic planarization layer, and said metallic material layer, wherein a top surface of said dielectric material layer is physically exposed underneath said cavity;
applying a second organic planarization layer in said cavity and over said non-metallic hard mask layer;
recessing an upper portion of said second organic planarization layer;
removing said non-metallic hard mask layer; and
removing a lower portion of said second organic planarization layer and said first organic planarization layer, wherein said top surface of said dielectric material layer is physically exposed again.
2. The method of claim 1, wherein said lower portion of said second organic planarization layer and said first organic planarization layer are removed simultaneously.
3. The method of claim 1, further comprising:
forming a patterned photoresist layer over said non-metallic hard mask layer; and
transferring a pattern in said patterned photoresist layer through said non-metallic hard mask layer, said first organic planarization layer, and said metallic material layer employing at least one anisotropic etch.
4. The method of claim 3, wherein said pattern in said patterned photoresist layer includes an opening, and said cavity is formed in a region underlying said opening in said patterned photoresist layer.
5. The method of claim 3, wherein said second organic planarization layer is formed directly on a top surface and sidewalls of a remaining portion of said patterned photoresist layer that remains after said at least one anisotropic etch.
6. The method of claim 5, further comprising removing said remaining portion of said patterned photoresist layer during recessing of said upper portion of said second organic planarization layer.
7. The method of claim 3, wherein said second organic planarization layer is formed directly on a top surface of said non-metallic hard mask layer.
8. The method of claim 3, wherein said second organic planarization layer is formed by spin coating of an organic planarization material.
9. The method of claim 1, wherein sidewalls of said non-metallic hard mask layer and sidewalls of said first organic planarization layer are vertically coincident among one another after formation of said cavity.
10. The method of claim 1, wherein said first organic planarization layer is etched by a dry etch, and said metallic material layer is etched by a wet etch during formation of said trench.
11. The method of claim 1, wherein said upper portion and said lower portion of said second organic planarization layer are removed by dry etches.
12. The method of claim 1, wherein said recessing of said upper portion of said second organic planarization layer is performed employing an anisotropic etch process that is selective to a material of said non-metallic hard mask layer.
13. The method of claim 1, wherein removal of said lower portion of said second organic planarization layer and said first organic planarization layer is performed employing a dry etch that is selective to said dielectric material layer.
14. The method of claim 1, wherein removal of said lower portion of said second organic planarization layer and said first organic planarization layer is performed employing an ashing process.
15. The method of claim 1, wherein said dielectric material layer includes a dielectric material having a dielectric constant greater than 7.9.
16. The method of claim 15, wherein said dielectric material layer includes a dielectric metal oxide.
17. The method of claim 1, wherein said non-metallic hard mask layer includes a silicon oxide material, a silicon nitride material, or a silicon oxynitride material, and is deposited by chemical vapor deposition.
18. The method of claim 1, wherein said non-metallic hard mask layer includes a silicon-containing antireflective coating material.
19. The method of claim 1, wherein said metallic material layer comprises a material selected from an elemental metal, an alloy of at least two elemental metals, a compound of at least one metal and nitrogen, a compound of at least one metal and carbon, and a stack thereof.
20. The method of claim 1, wherein each of said first and second organic planarization layer includes a non-photosensitive organic polymer material.
US14/149,898 2014-01-08 2014-01-08 Metallic mask patterning process for minimizing collateral etch of an underlayer Expired - Fee Related US9093387B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/149,898 US9093387B1 (en) 2014-01-08 2014-01-08 Metallic mask patterning process for minimizing collateral etch of an underlayer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/149,898 US9093387B1 (en) 2014-01-08 2014-01-08 Metallic mask patterning process for minimizing collateral etch of an underlayer

Publications (2)

Publication Number Publication Date
US20150194320A1 true US20150194320A1 (en) 2015-07-09
US9093387B1 US9093387B1 (en) 2015-07-28

Family

ID=53495764

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/149,898 Expired - Fee Related US9093387B1 (en) 2014-01-08 2014-01-08 Metallic mask patterning process for minimizing collateral etch of an underlayer

Country Status (1)

Country Link
US (1) US9093387B1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150214068A1 (en) * 2014-01-24 2015-07-30 United Microelectronics Corp. Method of performing etching process
US11383269B2 (en) * 2019-06-10 2022-07-12 Bfly Operations, Inc. Curved micromachined ultrasonic transducer membranes
WO2023226106A1 (en) * 2022-05-24 2023-11-30 长鑫存储技术有限公司 Semiconductor structure and forming method therefor
EP4303910A4 (en) * 2022-05-24 2024-10-16 Changxin Memory Tech Inc Semiconductor structure and forming method therefor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018053487A1 (en) * 2016-09-19 2018-03-22 Tokyo Electron Limited Method of in situ hard mask removal

Citations (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323121B1 (en) * 2000-05-12 2001-11-27 Taiwan Semiconductor Manufacturing Company Fully dry post-via-etch cleaning method for a damascene process
US6448177B1 (en) * 2001-03-27 2002-09-10 Intle Corporation Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure
US6455411B1 (en) * 2000-09-11 2002-09-24 Texas Instruments Incorporated Defect and etch rate control in trench etch for dual damascene patterning of low-k dielectrics
US20020182874A1 (en) * 2001-06-01 2002-12-05 Chih-Jung Wang Method for forming hybrid low-k film stack to avoid thermal stress effect
US6514860B1 (en) * 2001-01-31 2003-02-04 Advanced Micro Devices, Inc. Integration of organic fill for dual damascene process
US20040043586A1 (en) * 2002-08-29 2004-03-04 Fawad Ahmed Sacrificial deposition layer as screening material for implants into a wafer during the manufacture of a semiconductor device
US6720256B1 (en) * 2002-12-04 2004-04-13 Taiwan Semiconductor Manufacturing Company Method of dual damascene patterning
US20040127016A1 (en) * 2002-12-30 2004-07-01 Texas Instruments Incorporated Dual cap layer in damascene interconnection processes
US6774028B2 (en) * 2001-06-14 2004-08-10 Nec Electronics Corporation Method of forming wiring structure by using photo resist having optimum development rate
US6797633B2 (en) * 2000-11-09 2004-09-28 Texas Instruments Incorporated In-situ plasma ash/treatment after via etch of low-k films for poison-free dual damascene trench patterning
US20040259355A1 (en) * 2003-06-17 2004-12-23 Zhiping Yin Boron-doped amorphous carbon film for use as a hard etch mask during the formation of a semiconductor device
US20050014361A1 (en) * 2003-05-19 2005-01-20 Nguyen Son Van Dielectric materials to prevent photoresist poisoning
US6881678B2 (en) * 2002-12-30 2005-04-19 Anam Semiconductor, Inc. Method for forming a dual damascene structure in a semiconductor device
US20050118800A1 (en) * 2003-09-19 2005-06-02 Brakensiek Nickolas L. Method of filling structures for forming via-first dual damascene interconnects
US20050233572A1 (en) * 2004-04-14 2005-10-20 Yi-Nien Su Dual damascene structure formed of low-k dielectric materials
US20060154400A1 (en) * 2005-01-10 2006-07-13 Yang-Kyu Choi Method of forming a nanogap and method of manufacturing a nano field effect transitor for molecular device and bio-sensor, and molecular device and bio-sensor manufactured using the same
US7176123B2 (en) * 2003-05-30 2007-02-13 Hynix Semiconductor Inc. Method for manufacturing metal line of semiconductor device
US7214609B2 (en) * 2002-12-05 2007-05-08 Texas Instruments Incorporated Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities
US20070218679A1 (en) * 2006-03-20 2007-09-20 Applied Materials, Inc. Organic BARC etch process capable of use in the formation of low k dual damascene integrated circuits
US20080014533A1 (en) * 2006-07-14 2008-01-17 Keller David J Semiconductor device fabrication and dry develop process suitable for critical dimension tunability and profile control
US20080142988A1 (en) * 2006-12-15 2008-06-19 Tokyo Electron Limited Method for selective removal of damaged multi-stack bilayer films
US20080149992A1 (en) * 2006-12-20 2008-06-26 Commissariat A L'energie Atomique Storage device with multi-level structure
US7435676B2 (en) * 2006-01-10 2008-10-14 International Business Machines Corporation Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity
US7470616B1 (en) * 2008-05-15 2008-12-30 International Business Machines Corporation Damascene wiring fabrication methods incorporating dielectric cap etch process with hard mask retention
US7564136B2 (en) * 2006-02-24 2009-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Integration scheme for Cu/low-k interconnects
US7569486B2 (en) * 2007-05-09 2009-08-04 Texas Instruments Incorporated Spin on glass (SOG) etch improvement method
US7637269B1 (en) * 2009-07-29 2009-12-29 Tokyo Electron Limited Low damage method for ashing a substrate using CO2/CO-based process
US20100048011A1 (en) * 2008-08-22 2010-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method of patterning a metal gate of semiconductor device
US20100203709A1 (en) * 2009-02-12 2010-08-12 Wolodymyr Czubatyj Deposition of chalcogenide materials via vaporization process
US20100258881A1 (en) * 2009-04-14 2010-10-14 International Business Machines Corporation Dual metal and dual dielectric integration for metal high-k fets
US7838415B2 (en) * 2007-01-16 2010-11-23 United Microelectronics Corp. Method of fabricating dual damascene structure
US7910477B2 (en) * 2007-12-28 2011-03-22 Texas Instruments Incorporated Etch residue reduction by ash methodology
US20110092069A1 (en) * 2009-10-20 2011-04-21 International Business Machines Corporation Self-aligned patterned etch stop layers for semiconductor devices
US20120006396A1 (en) * 2010-07-08 2012-01-12 International Business Machines Corporation Method to evaluate effectiveness of substrate cleanness and quantity of pin holes in an antireflective coating of a solar cell
US8106455B2 (en) * 2009-04-30 2012-01-31 International Business Machines Corporation Threshold voltage adjustment through gate dielectric stack modification
US20130001750A1 (en) * 2011-06-29 2013-01-03 International Business Machines Corporation Film stack including metal hardmask layer for sidewall image transfer fin field effect transistor formation
US20130099295A1 (en) * 2011-10-25 2013-04-25 Globalfoundries Inc. Replacement gate fabrication methods
US20130216776A1 (en) * 2012-02-22 2013-08-22 International Business Machines Corporation Dual hard mask lithography process
US20130214391A1 (en) * 2012-02-17 2013-08-22 International Business Machines Corporation Lateral-Dimension-Reducing Metallic Hard Mask Etch
US20140024191A1 (en) * 2012-07-23 2014-01-23 International Business Machines Corporation Method of multiple patterning to form semiconductor devices
US20140256145A1 (en) * 2013-03-11 2014-09-11 International Business Machines Corporation Dsa grapho-epitaxy process with etch stop material
US20140264685A1 (en) * 2013-03-13 2014-09-18 Taiwan Semiconductors Manufacturing Company Limited Image sensor with stacked grid structure
US8906794B1 (en) * 2013-08-01 2014-12-09 Globalfoundries Inc. Gate silicidation
US20150004760A1 (en) * 2013-06-26 2015-01-01 Samsung Display Co., Ltd. Manufacturing method of liquid crystal display having touch sensor
US20150076586A1 (en) * 2013-09-15 2015-03-19 SanDisk Technologies, Inc. Single-semiconductor-layer channel in a memory opening for a three-dimensional non-volatile memory device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000002235A1 (en) 1998-07-06 2000-01-13 Strasbaugh Method of planarizing integrated circuits
KR100512167B1 (en) 2001-03-12 2005-09-02 삼성전자주식회사 Method of forming trench type isolation layer
US6743713B2 (en) 2002-05-15 2004-06-01 Institute Of Microelectronics Method of forming dual damascene pattern using dual bottom anti-reflective coatings (BARC)
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
ATE511702T1 (en) 2005-03-22 2011-06-15 Nxp Bv SIDEWALL PORE SEALING FOR NONCONDUCTORS WITH LOW DILECTRIC CONSTANT
US7781332B2 (en) 2007-09-19 2010-08-24 International Business Machines Corporation Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer
KR20100046406A (en) 2008-10-27 2010-05-07 주식회사 동부하이텍 Semiconductor device and method for manufacturing the same
EP2378557B1 (en) 2010-04-19 2015-12-23 Imec Method of manufacturing a vertical TFET
US8461043B2 (en) 2011-04-11 2013-06-11 Micron Technology, Inc. Barrier layer for integrated circuit contacts

Patent Citations (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323121B1 (en) * 2000-05-12 2001-11-27 Taiwan Semiconductor Manufacturing Company Fully dry post-via-etch cleaning method for a damascene process
US6455411B1 (en) * 2000-09-11 2002-09-24 Texas Instruments Incorporated Defect and etch rate control in trench etch for dual damascene patterning of low-k dielectrics
US6797633B2 (en) * 2000-11-09 2004-09-28 Texas Instruments Incorporated In-situ plasma ash/treatment after via etch of low-k films for poison-free dual damascene trench patterning
US6514860B1 (en) * 2001-01-31 2003-02-04 Advanced Micro Devices, Inc. Integration of organic fill for dual damascene process
US6448177B1 (en) * 2001-03-27 2002-09-10 Intle Corporation Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure
US20020182874A1 (en) * 2001-06-01 2002-12-05 Chih-Jung Wang Method for forming hybrid low-k film stack to avoid thermal stress effect
US6774028B2 (en) * 2001-06-14 2004-08-10 Nec Electronics Corporation Method of forming wiring structure by using photo resist having optimum development rate
US20040043586A1 (en) * 2002-08-29 2004-03-04 Fawad Ahmed Sacrificial deposition layer as screening material for implants into a wafer during the manufacture of a semiconductor device
US6720256B1 (en) * 2002-12-04 2004-04-13 Taiwan Semiconductor Manufacturing Company Method of dual damascene patterning
US7214609B2 (en) * 2002-12-05 2007-05-08 Texas Instruments Incorporated Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities
US20040127016A1 (en) * 2002-12-30 2004-07-01 Texas Instruments Incorporated Dual cap layer in damascene interconnection processes
US6881678B2 (en) * 2002-12-30 2005-04-19 Anam Semiconductor, Inc. Method for forming a dual damascene structure in a semiconductor device
US20050014361A1 (en) * 2003-05-19 2005-01-20 Nguyen Son Van Dielectric materials to prevent photoresist poisoning
US7176123B2 (en) * 2003-05-30 2007-02-13 Hynix Semiconductor Inc. Method for manufacturing metal line of semiconductor device
US20040259355A1 (en) * 2003-06-17 2004-12-23 Zhiping Yin Boron-doped amorphous carbon film for use as a hard etch mask during the formation of a semiconductor device
US20050118800A1 (en) * 2003-09-19 2005-06-02 Brakensiek Nickolas L. Method of filling structures for forming via-first dual damascene interconnects
US20050233572A1 (en) * 2004-04-14 2005-10-20 Yi-Nien Su Dual damascene structure formed of low-k dielectric materials
US20060154400A1 (en) * 2005-01-10 2006-07-13 Yang-Kyu Choi Method of forming a nanogap and method of manufacturing a nano field effect transitor for molecular device and bio-sensor, and molecular device and bio-sensor manufactured using the same
US7435676B2 (en) * 2006-01-10 2008-10-14 International Business Machines Corporation Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity
US7564136B2 (en) * 2006-02-24 2009-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Integration scheme for Cu/low-k interconnects
US20070218679A1 (en) * 2006-03-20 2007-09-20 Applied Materials, Inc. Organic BARC etch process capable of use in the formation of low k dual damascene integrated circuits
US20080014533A1 (en) * 2006-07-14 2008-01-17 Keller David J Semiconductor device fabrication and dry develop process suitable for critical dimension tunability and profile control
US20080142988A1 (en) * 2006-12-15 2008-06-19 Tokyo Electron Limited Method for selective removal of damaged multi-stack bilayer films
US20080149992A1 (en) * 2006-12-20 2008-06-26 Commissariat A L'energie Atomique Storage device with multi-level structure
US7838415B2 (en) * 2007-01-16 2010-11-23 United Microelectronics Corp. Method of fabricating dual damascene structure
US7569486B2 (en) * 2007-05-09 2009-08-04 Texas Instruments Incorporated Spin on glass (SOG) etch improvement method
US7910477B2 (en) * 2007-12-28 2011-03-22 Texas Instruments Incorporated Etch residue reduction by ash methodology
US7470616B1 (en) * 2008-05-15 2008-12-30 International Business Machines Corporation Damascene wiring fabrication methods incorporating dielectric cap etch process with hard mask retention
US20100048011A1 (en) * 2008-08-22 2010-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method of patterning a metal gate of semiconductor device
US20100203709A1 (en) * 2009-02-12 2010-08-12 Wolodymyr Czubatyj Deposition of chalcogenide materials via vaporization process
US20100258881A1 (en) * 2009-04-14 2010-10-14 International Business Machines Corporation Dual metal and dual dielectric integration for metal high-k fets
US8106455B2 (en) * 2009-04-30 2012-01-31 International Business Machines Corporation Threshold voltage adjustment through gate dielectric stack modification
US7637269B1 (en) * 2009-07-29 2009-12-29 Tokyo Electron Limited Low damage method for ashing a substrate using CO2/CO-based process
US20110092069A1 (en) * 2009-10-20 2011-04-21 International Business Machines Corporation Self-aligned patterned etch stop layers for semiconductor devices
US20120006396A1 (en) * 2010-07-08 2012-01-12 International Business Machines Corporation Method to evaluate effectiveness of substrate cleanness and quantity of pin holes in an antireflective coating of a solar cell
US20130001750A1 (en) * 2011-06-29 2013-01-03 International Business Machines Corporation Film stack including metal hardmask layer for sidewall image transfer fin field effect transistor formation
US20130099295A1 (en) * 2011-10-25 2013-04-25 Globalfoundries Inc. Replacement gate fabrication methods
US20130214391A1 (en) * 2012-02-17 2013-08-22 International Business Machines Corporation Lateral-Dimension-Reducing Metallic Hard Mask Etch
US20130216776A1 (en) * 2012-02-22 2013-08-22 International Business Machines Corporation Dual hard mask lithography process
US20140024191A1 (en) * 2012-07-23 2014-01-23 International Business Machines Corporation Method of multiple patterning to form semiconductor devices
US20140256145A1 (en) * 2013-03-11 2014-09-11 International Business Machines Corporation Dsa grapho-epitaxy process with etch stop material
US20140264685A1 (en) * 2013-03-13 2014-09-18 Taiwan Semiconductors Manufacturing Company Limited Image sensor with stacked grid structure
US20150004760A1 (en) * 2013-06-26 2015-01-01 Samsung Display Co., Ltd. Manufacturing method of liquid crystal display having touch sensor
US8906794B1 (en) * 2013-08-01 2014-12-09 Globalfoundries Inc. Gate silicidation
US20150076586A1 (en) * 2013-09-15 2015-03-19 SanDisk Technologies, Inc. Single-semiconductor-layer channel in a memory opening for a three-dimensional non-volatile memory device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150214068A1 (en) * 2014-01-24 2015-07-30 United Microelectronics Corp. Method of performing etching process
US9385000B2 (en) * 2014-01-24 2016-07-05 United Microelectronics Corp. Method of performing etching process
US11383269B2 (en) * 2019-06-10 2022-07-12 Bfly Operations, Inc. Curved micromachined ultrasonic transducer membranes
WO2023226106A1 (en) * 2022-05-24 2023-11-30 长鑫存储技术有限公司 Semiconductor structure and forming method therefor
EP4303910A4 (en) * 2022-05-24 2024-10-16 Changxin Memory Tech Inc Semiconductor structure and forming method therefor

Also Published As

Publication number Publication date
US9093387B1 (en) 2015-07-28

Similar Documents

Publication Publication Date Title
US20180076132A1 (en) Self-Aligned Interconnection Structure and Method
KR102108234B1 (en) Patterning Method for Semiconductor Device and Structures resulting therefrom
KR102296810B1 (en) Self-aligned patterning using directed self-assembly of block copolymers
US10867846B2 (en) Fin field effect transistor (finFET) device structure with protection layer and method for forming the same
US7759239B1 (en) Method of reducing a critical dimension of a semiconductor device
US20170365676A1 (en) Device for improving performance through gate cut last process
US9093387B1 (en) Metallic mask patterning process for minimizing collateral etch of an underlayer
KR101813765B1 (en) Semiconductor structure and manufacturing process thereof
JPH07335674A (en) Iii-v family semiconductor gate structure and its preparation
US20060199370A1 (en) Method of in-situ ash strip to eliminate memory effect and reduce wafer damage
US10276378B1 (en) Method of forming funnel-like opening for semiconductor device structure
CN110931354B (en) Semiconductor structure and method for manufacturing semiconductor structure
US20170170308A1 (en) Semiconductor device and method of manufacturing same
US10957552B2 (en) Extreme ultraviolet lithography patterning with directional deposition
TW202114068A (en) Method for forming semiconductor device
US9324793B2 (en) Method for controlling the profile of an etched metallic layer
US9054025B2 (en) Process for controlling shallow trench isolation step height
EP2988322B1 (en) Method for selective oxide removal
US9437712B2 (en) High performance self aligned contacts and method of forming same
US7538025B2 (en) Dual damascene process flow for porous low-k materials
US20170170016A1 (en) Multiple patterning method for substrate
US20230154753A1 (en) Patterned Semiconductor Device and Method
US11869772B2 (en) Method for silicidation of semiconductor device, and corresponding semiconductor device
US20240030299A1 (en) Semiconductor device and manufacturing method thereof
CN108155150B (en) Semiconductor structure and forming method thereof

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ALLEN, SCOTT D;CHEN, KUANG-JUNG;DONG, HUIHANG;AND OTHERS;SIGNING DATES FROM 20131204 TO 20131212;REEL/FRAME:031914/0395

STCF Information on status: patent grant

Free format text: PATENTED CASE

AS Assignment

Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001

Effective date: 20150629

AS Assignment

Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001

Effective date: 20150910

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

AS Assignment

Owner name: ALSEPHINA INNOVATIONS INC., CANADA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:049612/0211

Effective date: 20181126

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20190728

AS Assignment

Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:054636/0001

Effective date: 20201117