US20030113947A1 - Electrical/optical integration scheme using direct copper bonding - Google Patents

Electrical/optical integration scheme using direct copper bonding Download PDF

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US20030113947A1
US20030113947A1 US10/020,911 US2091101A US2003113947A1 US 20030113947 A1 US20030113947 A1 US 20030113947A1 US 2091101 A US2091101 A US 2091101A US 2003113947 A1 US2003113947 A1 US 2003113947A1
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Prior art keywords
contact pads
wafer
optical
further including
release layer
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Abandoned
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US10/020,911
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Gilroy Vandentop
Jun-Fei Zheng
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Intel Corp
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Intel Corp
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Priority to US10/020,911 priority Critical patent/US20030113947A1/en
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ZHENG, JUN-FEI, VANDENTOP, GILROY J.
Priority to AU2002359506A priority patent/AU2002359506A1/en
Priority to PCT/US2002/038027 priority patent/WO2003054954A2/en
Priority to CNA028251865A priority patent/CN1605123A/en
Priority to EP02794048A priority patent/EP1456879A2/en
Publication of US20030113947A1 publication Critical patent/US20030113947A1/en
Priority to US11/488,389 priority patent/US7359591B2/en
Priority to US12/002,274 priority patent/US7826694B2/en
Abandoned legal-status Critical Current

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    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
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    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present invention generally relates to semiconductor packages. More particularly, the invention relates to a semiconductor package and fabrication method that uses direct copper bonding to enhance performance and provide electro-optic connectivity.
  • an integrated circuit such as a processor is encapsulated in a dielectric material to form a semiconductor die (or IC wafer).
  • the IC wafer often has various IC contact pads that connect to the components of the IC by way of vertically extending vias and horizontally extending wires or traces.
  • PWB printed wiring board
  • One approach is to connect an intermediate wafer such as a chip interposer or host wafer to the IC wafer in order to form a larger and more manageable semiconductor package.
  • the intermediate wafer has one or more intermediate contact pads providing through-connection to the board side of the intermediate wafer.
  • Metalized vias are typically used to provide the above-described through-connection.
  • One conventional approach to connecting the two wafers is to use an indirect connection approach such as controlled collapse chip connection (C4).
  • C4 controlled collapse chip connection
  • the intermediate wafer has a socketable interconnection mechanism such as pins or ball grid array (BGA) balls, the semiconductor package can be directly mated with a socket that is hardwired to the PWB. Otherwise, a socketable interface is disposed between the semiconductor package and the socket.
  • BGA ball grid array
  • One particular difficulty relates to the placement of the optical detector on the IC wafer. Specifically, it has been determined that C4 bonding results in a “gap” between the wafers, and that the gap can lead to a number of problems from an optical standpoint. For example, aligning the optical arrangement with the photodetector requires a significant amount of precision in order to adequately couple the optical energy across the interface between the two wafers. Furthermore, the indirect bonding approach results in gaps on the order of 60 microns that can allow optical energy to escape regardless of how well the wafers are aligned.
  • FIG. 1 is a sectional view of an example of an electro-optic semiconductor package before direct copper bonding in accordance with one embodiment of the present invention
  • FIG. 2 is a sectional view of an example of an electro-optic semiconductor package after direct copper bonding in accordance with one embodiment of the present invention
  • FIG. 3 is a flowchart of an example of a method of fabricating an electro-optic semiconductor package in accordance with one embodiment of the present invention
  • FIG. 4 is a flowchart of an example of a process of direct copper bonding IC contacts pads to intermediate contact pads in accordance with one embodiment of the present invention; and is a flowchart of an example of a method of fabricating an intermediate wafer in accordance with one embodiment of the present invention.
  • Embodiments of an electro-optic semiconductor package and fabrication method provide enhanced performance.
  • an integrated circuit (IC) wafer having one or more IC contact pads is provided, where the IC contact pads are connected to an IC on the IC wafer.
  • An intermediate wafer having one or more intermediate contact pads is provided, where the intermediate contact pads are connected to an electro-optic arrangement on the intermediate wafer.
  • the method further provides for direct copper bonding the IC contact pads to adjacent intermediate contact pads such that an electro-optic semiconductor package results.
  • a method of fabricating an intermediate wafer provides for disposing a waveguide within the intermediate wafer.
  • An optical coupler is positioned adjacent to the waveguide within the intermediate wafer, where the coupler enables transport of an optical signal and one or more intermediate contact pads of the intermediate wafer enable transport of an electrical signal.
  • the method further provides for positioning an electro-optic converter between the optical coupler and the intermediate contact pads such that the converter enables conversion between the optical signal and the electrical signal.
  • the converter may be either an optical detector or an optical emitter.
  • an electro-optic semiconductor package includes an IC wafer having one or more IC contact pads, where the IC contact pads are connected to an IC on the IC wafer.
  • An intermediate wafer has one or more intermediate contact pads, where the intermediate contact pads are connected to an electro-optic arrangement on the intermediate wafer.
  • the contact pads form a plurality of direct copper bonds.
  • the completed semiconductor package 10 includes an IC wafer 12 having one or more IC contact pads 14 .
  • the IC contact pads 14 are connected to an IC (not shown) on the IC wafer 12 by way of vertically extending vias 16 and horizontally extending wires or traces 18 . It will be appreciated that only two levels of interconnection are shown in the IC wafer 12 , whereas typically as many as six or more levels may be used.
  • the package further includes an intermediate wafer 20 having one or more intermediate contact pads 22 .
  • the intermediate contact pads 22 are connected to an electro-optic arrangement 24 on the intermediate wafer 20 .
  • the contact pads 14 , 22 form a plurality of direct copper bonds such that the gap between the two wafers 12 , 20 is eliminated.
  • the gap between the two wafers 12 , 20 By eliminating the gap between the two wafers 12 , 20 , a number of performance difficulties can be obviated.
  • the illustrated embodiment of the electro-optic arrangement includes a first arrangement 24 a and a second arrangement 24 b .
  • the first arrangement 24 a has a waveguide 26 disposed within the intermediate wafer 20 .
  • An optical coupler 28 is positioned adjacent to the waveguide 26 within the intermediate wafer 20 such that the coupler 28 enables receipt of an optical signal from the waveguide 26 .
  • the optical signal can be obtained from any source such as a laser, light emitting diode (LED) or another waveguide. It will be appreciated that the source of the optical signal may also originate from within the intermediate wafer 20 or from an external source.
  • An electro-optic converter such as optical detector 30 is positioned between the optical coupler 28 and one or more of the intermediate contact pads 22 such that the optical detector 30 enables transfer of an electrical signal to the intermediate contact pads based on the optical signal.
  • Optical detectors are well documented in the semiconductor industry and any number of commercially available detectors can be used.
  • the optical detector 30 enables transfer of the electrical signal to intermediate contact pads 22 b and 22 c .
  • the resulting electrical signal may be a clock signal, input/output (I/O) signal, or any other type of signal suitable for transmission in the optical domain. It should be noted, however, that clock and I/O signals typically contain higher frequencies and therefore lend themselves to optical transmission due to bandwidth concerns.
  • the second arrangement 24 b similarly includes a waveguide 32 disposed within the intermediate wafer 20 , and an optical coupler 34 .
  • the optical coupler 34 is positioned adjacent to the waveguide 32 within the intermediate wafer 20 and enables transmission of an optical signal to the waveguide 32 .
  • An electro-optic converter such as optical emitter 36 is positioned between the optical coupler 34 and intermediate contact pads 22 e and 22 f such that the optical emitter 36 enables transfer of an optical signal to the waveguide 32 based on the electrical signal transported by the intermediate contact pads 22 e and 22 f .
  • the waveguide 32 extends to an external surface of the intermediate wafer 20 in order to demonstrate the possibility of sending optical signals to external components.
  • Waveguide 26 is shown as extending in a direction that is perpendicular to the waveguide 32 and illustrates the possibility of using other internal light sources.
  • the electro-optic arrangement 24 can include optical detectors 30 , optical emitters 36 , or any combination thereof without parting from the spirit and scope of the invention.
  • the illustrated intermediate wafer 20 further includes vias 38 , 40 that extend through the intermediate wafer 20 to intermediate contact pads 22 a and 22 d .
  • the vias 38 , 40 provide a mechanism for testing certain locations or interconnecting the semiconductor package 10 with other structures such as pin grid arrays (PGAs), ball grid arrays , (BGAs), etc.
  • the semiconductor package 10 provides a mechanism for facilitating manipulation of the package 10 by personnel, fabrication machinery and other external elements.
  • the intermediate wafer 20 may be built upon or attached to a handle wafer 44 , by means of a release layer 42 .
  • the handle 44 is removable by etching away the release layer 42 after the direct copper bonding process as best shown in FIG. 2.
  • FIG. 3 a method of fabricating an electro-optic semiconductor package is shown at 50 in accordance with one embodiment of the present invention.
  • an IC wafer having one or more IC contact pads is provided at processing block 52 .
  • the IC contact pads are connected to an IC on the IC wafer.
  • An intermediate wafer having one or more intermediate contact pads is provided at block 54 , where the intermediate contact pads are connected to an electro-optic arrangement on the intermediate wafer.
  • Processing block 56 provides for direct copper bonding the IC contact pads to adjacent intermediate contact pads such that the electro-optic semiconductor package results.
  • the release layer is removed at block 58 in order to facilitate connection to any vias that may be present.
  • FIG. 4 illustrates the preferred approach to direct copper bonding the contact pads in greater detail at block 56 .
  • the IC contact pads and the intermediate contact pads are cleaned at block 60 .
  • One approach to the cleaning process is to use an acid bath followed by a water rinse and spin-dry. Applicable cleaning processes are discussed in greater detail in “Copper Wafer Bonding”, A. Fan et al., Electrochemical and Solid State Letters, 2 (10), pp. 534-36(1999).
  • the purpose of the acid bath is to remove any native oxide that exists on the metal surface of the contact pads, it has been determined that wafer bonding without surface preparation can also be achieved with reproducible results.
  • processing block 62 provides for disposing the IC contact pads adjacent to the intermediate contact pads in an oxidation-resistant environment (such as nitrogen) having a predetermined ambient temperature. While the appropriate ambient temperature varies based on a number of factors, temperatures on the order of 390° C. have been demonstrated as being sufficient to support the bonding process.
  • the IC contact pads are forced into direct contact with the adjacent intermediate contact pads at a predetermined pressure for a predetermined period of time at processing block 64 such that a direct copper bond results. It should be noted that as a result of the above-described process, adjacent contact pads become a single, continuous layer of copper as opposed to the copper-solder-copper interface obtained from C4 bonding and other conventional approaches.
  • FIG. 5 demonstrates that the direct copper bond enables a unique approach to fabricating the intermediate wafer.
  • fabrication method 66 includes the processing block 68 of disposing a waveguide within the intermediate wafer.
  • An optical coupler is positioned adjacent to the waveguide within the intermediate wafer at block 70 such that the coupler enables receipt of an optical signal from the waveguide.
  • Processing block 72 provides for positioning an optical detector between the optical coupler and one or more intermediate contact pads of the intermediate wafer such that optical detector enables transfer of an electrical signal to the intermediate contact pads based on the optical signal.
  • the optical detector can be placed on the intermediate wafer as opposed to the conventional approach of placing the detector on the IC wafer. By so doing, a number of advantages can be achieved.
  • the optical losses that normally occur as a result of the C4 gap between the wafers are minimized.
  • the electrical losses associated with transmitting electrical signals across the C4 bond are significantly reduced. Such losses include unwanted interconnect delay, resistance, capacitance, and loop inductance. It can further be seen that vias are extended through the intermediate wafer to one or more of the intermediate contact pads at block 74 .
  • the order in which many of the processes described herein are preformed may vary depending on the circumstances. For example, manufacturing concerns may dictate that the vias be created before disposition of the waveguide, or that the optical detector be positioned before placement of the waveguide and optical coupler. It is also possible that the release layer is deposited on the handle wafer and the intermediate wafer 20 is built up over the handle wafer. In this approach, a base cladding layer would first be deposited, followed by deposition and definition of the waveguide material. The optical coupler 34 is defined, followed by the deposition and definition of the optical detector, and finally through via 40 definition and intermediate contact pad 22 definition.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Optical Integrated Circuits (AREA)
  • Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)
  • Wire Bonding (AREA)
  • Optical Modulation, Optical Deflection, Nonlinear Optics, Optical Demodulation, Optical Logic Elements (AREA)
  • Optical Couplings Of Light Guides (AREA)

Abstract

An electro-optic semiconductor package and fabrication method provides enhanced performance. An integrated circuit (IC) having one or more IC contact pads is provided, where the IC contact pads are connected to an IC on the IC wafer. An intermediate wafer having one or more intermediate contact pads is provided, where the intermediate contact pads are connected to an electro-optic arrangement on the intermediate wafer. The method further provides for direct copper bonding the IC contact pads to adjacent intermediate contact pads such that an electro-optic semiconductor package results.

Description

    BACKGROUND OF THE INVENTION
  • 1. Technical Field [0001]
  • The present invention generally relates to semiconductor packages. More particularly, the invention relates to a semiconductor package and fabrication method that uses direct copper bonding to enhance performance and provide electro-optic connectivity. [0002]
  • 2. Discussion [0003]
  • In the highly competitive computer industry, the trend toward higher processing speeds and increased functionality is well documented. While this trend is desirable to the consumer, it presents significant challenges to circuit designers as well as manufacturers. A particular area of concern relates to the design of semiconductor packages. [0004]
  • In a typical computing environment, an integrated circuit (IC) such as a processor is encapsulated in a dielectric material to form a semiconductor die (or IC wafer). The IC wafer often has various IC contact pads that connect to the components of the IC by way of vertically extending vias and horizontally extending wires or traces. In order to electrically connect the closely spaced IC contact pads to the various traces of an adjacent printed wiring board (PWB) such as a motherboard, a number of techniques have been used. One approach is to connect an intermediate wafer such as a chip interposer or host wafer to the IC wafer in order to form a larger and more manageable semiconductor package. The intermediate wafer has one or more intermediate contact pads providing through-connection to the board side of the intermediate wafer. Metalized vias are typically used to provide the above-described through-connection. One conventional approach to connecting the two wafers is to use an indirect connection approach such as controlled collapse chip connection (C4). If the intermediate wafer has a socketable interconnection mechanism such as pins or ball grid array (BGA) balls, the semiconductor package can be directly mated with a socket that is hardwired to the PWB. Otherwise, a socketable interface is disposed between the semiconductor package and the socket. As processing speeds continue to increase and computing devices continue to shrink in size, the effects of packaging designs on signal throughput have drawn more attention. [0005]
  • One of the more recent developments has been to capitalize upon the bandwidth advantages provided by transmitting signals in the optical domain. Specifically, it has been determined that the use of optics to transfer high speed clock signals as well as input/output (I/O) signals can significantly enhance performance. Conventional semiconductor packages that make use of optics often provide an IC wafer and an intermediate wafer that has an optical arrangement. The optical arrangement will typically include a waveguide and a coupler such as a Bragg grating. The waveguide and coupler therefore provide a mechanism for transporting optical signals between an optical source such as a laser or light emitting diode (LED) and the adjacent IC wafer. It is important to note, however, that processing of the signal often occurs in the electrical domain. This is particularly true in the case of computer processors widely used in the industry. In such cases, it is common to provide a photodetector on the IC wafer that is aligned with the optical coupler during the fabrication process. [0006]
  • While the above-described conventional approach has been satisfactory in some circumstances, certain difficulties remain. One particular difficulty relates to the placement of the optical detector on the IC wafer. Specifically, it has been determined that C4 bonding results in a “gap” between the wafers, and that the gap can lead to a number of problems from an optical standpoint. For example, aligning the optical arrangement with the photodetector requires a significant amount of precision in order to adequately couple the optical energy across the interface between the two wafers. Furthermore, the indirect bonding approach results in gaps on the order of 60 microns that can allow optical energy to escape regardless of how well the wafers are aligned. While the above-described optical losses could be avoided to some degree by placing the optical detector on the intermediate wafer, it has been determined that C4 bonding can also present problems from an electrical standpoint. For example, unwanted interconnect delay, resistance, capacitance, and loop inductance can all result from the C4 balls that are disposed between the IC contact pads and the intermediate contact pads. Thus, manufacturers and designers of conventional electro-optic semiconductor packages are faced with the difficult choice between the optical losses associated with IC wafer placement of the optical detector and the electrical losses associated with intermediate wafer placement of the optical detector.[0007]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a sectional view of an example of an electro-optic semiconductor package before direct copper bonding in accordance with one embodiment of the present invention; [0008]
  • FIG. 2 is a sectional view of an example of an electro-optic semiconductor package after direct copper bonding in accordance with one embodiment of the present invention; [0009]
  • FIG. 3 is a flowchart of an example of a method of fabricating an electro-optic semiconductor package in accordance with one embodiment of the present invention; [0010]
  • FIG. 4 is a flowchart of an example of a process of direct copper bonding IC contacts pads to intermediate contact pads in accordance with one embodiment of the present invention; and is a flowchart of an example of a method of fabricating an intermediate wafer in accordance with one embodiment of the present invention.[0011]
    • DETAILED DESCRIPTION
  • Embodiments of an electro-optic semiconductor package and fabrication method provide enhanced performance. In accordance with one embodiment of the fabrication method, an integrated circuit (IC) wafer having one or more IC contact pads is provided, where the IC contact pads are connected to an IC on the IC wafer. An intermediate wafer having one or more intermediate contact pads is provided, where the intermediate contact pads are connected to an electro-optic arrangement on the intermediate wafer. The method further provides for direct copper bonding the IC contact pads to adjacent intermediate contact pads such that an electro-optic semiconductor package results. [0012]
  • In another embodiment, a method of fabricating an intermediate wafer provides for disposing a waveguide within the intermediate wafer. An optical coupler is positioned adjacent to the waveguide within the intermediate wafer, where the coupler enables transport of an optical signal and one or more intermediate contact pads of the intermediate wafer enable transport of an electrical signal. The method further provides for positioning an electro-optic converter between the optical coupler and the intermediate contact pads such that the converter enables conversion between the optical signal and the electrical signal. The converter may be either an optical detector or an optical emitter. [0013]
  • Further in accordance with embodiments of the present invention, an electro-optic semiconductor package is provided. The semiconductor package includes an IC wafer having one or more IC contact pads, where the IC contact pads are connected to an IC on the IC wafer. An intermediate wafer has one or more intermediate contact pads, where the intermediate contact pads are connected to an electro-optic arrangement on the intermediate wafer. The contact pads form a plurality of direct copper bonds. [0014]
  • It is to be understood that both the foregoing general description and the following detailed description are merely exemplary of the invention, and are intended to provide an overview or framework for understanding the nature and character of the invention as it is claimed. The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute part of this specification. The drawings illustrate various features and embodiments of the invention, and together with the description serve to explain the principles and operation of the invention. [0015]
  • Turning now to FIGS. 1 and 2, an electro-optic semiconductor package is shown before and after the bonding process, respectively. Generally, the completed [0016] semiconductor package 10 includes an IC wafer 12 having one or more IC contact pads 14. The IC contact pads 14 are connected to an IC (not shown) on the IC wafer 12 by way of vertically extending vias 16 and horizontally extending wires or traces 18. It will be appreciated that only two levels of interconnection are shown in the IC wafer 12, whereas typically as many as six or more levels may be used. The package further includes an intermediate wafer 20 having one or more intermediate contact pads 22. The intermediate contact pads 22 are connected to an electro-optic arrangement 24 on the intermediate wafer 20. As will be discussed in greater detail below, after fabrication is complete, the contact pads 14, 22 form a plurality of direct copper bonds such that the gap between the two wafers 12, 20 is eliminated. By eliminating the gap between the two wafers 12, 20, a number of performance difficulties can be obviated.
  • Specifically, the illustrated embodiment of the electro-optic arrangement includes a [0017] first arrangement 24 a and a second arrangement 24 b. The first arrangement 24 a has a waveguide 26 disposed within the intermediate wafer 20. An optical coupler 28 is positioned adjacent to the waveguide 26 within the intermediate wafer 20 such that the coupler 28 enables receipt of an optical signal from the waveguide 26. The optical signal can be obtained from any source such as a laser, light emitting diode (LED) or another waveguide. It will be appreciated that the source of the optical signal may also originate from within the intermediate wafer 20 or from an external source. An electro-optic converter such as optical detector 30 is positioned between the optical coupler 28 and one or more of the intermediate contact pads 22 such that the optical detector 30 enables transfer of an electrical signal to the intermediate contact pads based on the optical signal. Optical detectors are well documented in the semiconductor industry and any number of commercially available detectors can be used. In the illustrated embodiment, the optical detector 30 enables transfer of the electrical signal to intermediate contact pads 22 b and 22 c. The resulting electrical signal may be a clock signal, input/output (I/O) signal, or any other type of signal suitable for transmission in the optical domain. It should be noted, however, that clock and I/O signals typically contain higher frequencies and therefore lend themselves to optical transmission due to bandwidth concerns.
  • It will further be appreciated that the number, orientation and positioning of the [0018] intermediate contact pads 22 depends upon the architecture of the electro-optic arrangement 24 and the particular application in which the semiconductor package 10 is used. It can further be seen that the second arrangement 24 b similarly includes a waveguide 32 disposed within the intermediate wafer 20, and an optical coupler 34. The optical coupler 34 is positioned adjacent to the waveguide 32 within the intermediate wafer 20 and enables transmission of an optical signal to the waveguide 32. An electro-optic converter such as optical emitter 36 is positioned between the optical coupler 34 and intermediate contact pads 22 e and 22 f such that the optical emitter 36 enables transfer of an optical signal to the waveguide 32 based on the electrical signal transported by the intermediate contact pads 22 e and 22 f. It can be seen that the waveguide 32 extends to an external surface of the intermediate wafer 20 in order to demonstrate the possibility of sending optical signals to external components. Waveguide 26, on the other hand, is shown as extending in a direction that is perpendicular to the waveguide 32 and illustrates the possibility of using other internal light sources. Thus, the electro-optic arrangement 24 can include optical detectors 30, optical emitters 36, or any combination thereof without parting from the spirit and scope of the invention.
  • It can further be seen that the illustrated [0019] intermediate wafer 20 further includes vias 38, 40 that extend through the intermediate wafer 20 to intermediate contact pads 22 a and 22 d. The vias 38, 40 provide a mechanism for testing certain locations or interconnecting the semiconductor package 10 with other structures such as pin grid arrays (PGAs), ball grid arrays , (BGAs), etc. Additionally, the semiconductor package 10 provides a mechanism for facilitating manipulation of the package 10 by personnel, fabrication machinery and other external elements. Specifically, the intermediate wafer 20 may be built upon or attached to a handle wafer 44, by means of a release layer 42. The handle 44 is removable by etching away the release layer 42 after the direct copper bonding process as best shown in FIG. 2.
  • Turning now to FIG. 3, a method of fabricating an electro-optic semiconductor package is shown at [0020] 50 in accordance with one embodiment of the present invention. Generally, an IC wafer having one or more IC contact pads is provided at processing block 52. As already discussed, the IC contact pads are connected to an IC on the IC wafer. An intermediate wafer having one or more intermediate contact pads is provided at block 54, where the intermediate contact pads are connected to an electro-optic arrangement on the intermediate wafer. Processing block 56 provides for direct copper bonding the IC contact pads to adjacent intermediate contact pads such that the electro-optic semiconductor package results. In the preferred embodiment, the release layer is removed at block 58 in order to facilitate connection to any vias that may be present.
  • FIG. 4 illustrates the preferred approach to direct copper bonding the contact pads in greater detail at [0021] block 56. Specifically, the IC contact pads and the intermediate contact pads are cleaned at block 60. One approach to the cleaning process is to use an acid bath followed by a water rinse and spin-dry. Applicable cleaning processes are discussed in greater detail in “Copper Wafer Bonding”, A. Fan et al., Electrochemical and Solid State Letters, 2 (10), pp. 534-36(1999). Although the purpose of the acid bath is to remove any native oxide that exists on the metal surface of the contact pads, it has been determined that wafer bonding without surface preparation can also be achieved with reproducible results. Notwithstanding, processing block 62 provides for disposing the IC contact pads adjacent to the intermediate contact pads in an oxidation-resistant environment (such as nitrogen) having a predetermined ambient temperature. While the appropriate ambient temperature varies based on a number of factors, temperatures on the order of 390° C. have been demonstrated as being sufficient to support the bonding process. The IC contact pads are forced into direct contact with the adjacent intermediate contact pads at a predetermined pressure for a predetermined period of time at processing block 64 such that a direct copper bond results. It should be noted that as a result of the above-described process, adjacent contact pads become a single, continuous layer of copper as opposed to the copper-solder-copper interface obtained from C4 bonding and other conventional approaches. It should also be noted that the use of such a bond to reduce both optical and electrical losses represents a significant improvement over traditional approaches. Key performance metrics associated with direct copper bonding are discussed in “Comparison of Key Performance Metrics in Two- and Three-Dimensional Integrated Circuits”, A. Rahman et al., Microsystems Technology, MIT, Cambridge, Mass.
  • Indeed, FIG. 5 demonstrates that the direct copper bond enables a unique approach to fabricating the intermediate wafer. For example, [0022] fabrication method 66 includes the processing block 68 of disposing a waveguide within the intermediate wafer. An optical coupler is positioned adjacent to the waveguide within the intermediate wafer at block 70 such that the coupler enables receipt of an optical signal from the waveguide. Processing block 72 provides for positioning an optical detector between the optical coupler and one or more intermediate contact pads of the intermediate wafer such that optical detector enables transfer of an electrical signal to the intermediate contact pads based on the optical signal. Thus, the optical detector can be placed on the intermediate wafer as opposed to the conventional approach of placing the detector on the IC wafer. By so doing, a number of advantages can be achieved. For example, the optical losses that normally occur as a result of the C4 gap between the wafers are minimized. Furthermore, the electrical losses associated with transmitting electrical signals across the C4 bond are significantly reduced. Such losses include unwanted interconnect delay, resistance, capacitance, and loop inductance. It can further be seen that vias are extended through the intermediate wafer to one or more of the intermediate contact pads at block 74.
  • It should be noted that the order in which many of the processes described herein are preformed may vary depending on the circumstances. For example, manufacturing concerns may dictate that the vias be created before disposition of the waveguide, or that the optical detector be positioned before placement of the waveguide and optical coupler. It is also possible that the release layer is deposited on the handle wafer and the [0023] intermediate wafer 20 is built up over the handle wafer. In this approach, a base cladding layer would first be deposited, followed by deposition and definition of the waveguide material. The optical coupler 34 is defined, followed by the deposition and definition of the optical detector, and finally through via 40 definition and intermediate contact pad 22 definition.
  • Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modification will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims. [0024]

Claims (30)

It is claimed that:
1. A method of fabricating an electro-optic semiconductor package, the method comprising:
providing an integrated circuit (IC) wafer having one or more IC contact pads, the IC contact pads being connected to an IC on the IC wafer;
providing an intermediate wafer having one or more intermediate contact pads, the intermediate contact pads being connected to an electro-optic arrangement on the intermediate wafer; and
direct copper bonding the IC contact pads to adjacent intermediate contact pads, the electro-optic semiconductor package resulting.
2. The method of claim 1 further including:
cleaning the contact pads;
disposing the IC contact pads adjacent to the intermediate contact pads in an oxidation-resistant environment having a predetermined ambient temperature; and
forcing the IC contact pads into direct contact with the adjacent intermediate contact pads at a predetermined pressure, a direct copper bond resulting.
3. The method of claim 2 further including cleaning the contact pads in an acid bath.
4. The method of claim 2 further including disposing the IC contact pads adjacent to the intermediate contact pads in a nitrogen environment.
5. The method of claim 1 further including:
disposing a waveguide within the intermediate wafer;
positioning an optical coupler adjacent to the waveguide within the intermediate wafer, the coupler enabling transport of an optical signal and the intermediate contact pads enabling transport of an electrical signal; and
positioning an electro-optic converter between the optical coupler and one or more of the intermediate pads, the converter enabling conversion between the optical signal and the electrical signal.
6. The method of claim 5 further including positioning an optical detector between the optical coupler and one or more of the intermediate pads, the detector enabling conversion of the optical signal into the electrical signal.
7. The method of claim 5 further including positioning an optical emitter between the optical coupler and one or more of the intermediate pads, the emitter enabling conversion of the electrical signal into the optical signal.
8. The method of claim 5 further including extending a via through the intermediate wafer to one or more of the intermediate contact pads.
9. The method of claim 5 further including:
coupling a release layer to a surface of the intermediate wafer; and
coupling a handle to the release layer.
10. The method of claim 9 further including removing the release layer after direct copper bonding the IC contact pads to the intermediate contact pads.
11. The method of claim 10 further includes etching away the release layer.
12. The method of claim 5 further including enabling conversion between the optical signal and a clock signal.
13. The method of claim 5 further including enabling conversion between the optical signal and an input/output (I/O) signal.
14. The method of claim 1 further including providing a computer processor wafer having one or more IC contact pads.
15. The method of claim 1 further including providing a chip interposer as the intermediate wafer.
16. The method of claim 1 further including providing a host wafer as the intermediate wafer.
17. A method of fabricating an intermediate wafer, the method comprising:
disposing a waveguide within the intermediate wafer;
positioning an optical coupler adjacent to the waveguide within the intermediate wafer, the coupler enabling transport of an optical signal and one or more intermediate contact pads of the intermediate wafer enabling transport of an electrical signal; and
positioning an electro-optic converter between the optical coupler and the intermediate contact pads, the converter enabling conversion between the optical signal and the electrical signal.
18. The method of claim 17 further including positioning an optical detector between the optical coupler and one or more of the intermediate pads, the detector enabling conversion of the optical signal into the electrical signal.
19. The method of claim 17 further including positioning an optical emitter between the optical coupler and one or more of the intermediate pads, the emitter enabling conversion of the electrical signal into the optical signal.
20. The method of claim 17 further including:
coupling a release layer to a surface of the intermediate wafer; and
coupling a handle to the release layer.
21. The method of claim 20 further including removing the release layer after direct copper bonding one or more IC contact pads to the intermediate contact pads.
22. The method of claim 21 further including etching away the release layer.
23. A method of fabricating an electro-optic semiconductor package, the method comprising:
providing a processor wafer having one or more IC contact pads, the IC contact pads being connected to a computer processor on the processor wafer;
coupling a release layer to a surface of an intermediate wafer;
coupling a handle to the release layer;
disposing a waveguide within the intermediate wafer;
positioning an optical coupler adjacent to the waveguide within the intermediate wafer, the coupler enabling receipt of an optical signal from the waveguide;
positioning optical detector between the optical coupler and one or more intermediate contact pads, the optical detector enabling transfer of an electrical signal to the intermediate contact pads based on the optical signal;
cleaning the contact pads in an acid bath;
disposing the IC contact pads adjacent to the intermediate contact pads in an oxidation-resistant environment having a predetermined ambient temperature; and
forcing the IC contact pads into direct contact with the intermediate contact pads at a predetermined pressure, a direct copper bond resulting.
24. The method of claim 23 further including removing the release layer after direct copper bonding the IC contact pads to the intermediate contact pads.
25. The method of claim 24 further including etching away the release layer.
26. An electro-optic semiconductor package comprising:
an integrated circuit (IC) wafer having one or more IC contact pads, the IC contact pads being connected to an IC on the IC wafer;
an intermediate wafer having one or more intermediate contact pads, the intermediate contact pads being connected to an electro-optic arrangement on the intermediate wafer; and
said contact pads forming a plurality of direct copper bonds.
27. The package of claim 26 wherein the electro-optic arrangement of the intermediate wafer includes:
a waveguide disposed within the intermediate wafer;
an optical coupler positioned adjacent to the waveguide within the intermediate wafer, the coupler enabling receipt of an optical signal from the waveguide; and
an optical detector positioned between the optical coupler and one or more of the intermediate contact pads, the optical detector enabling transfer of an electrical signal to the intermediate contact pads based on the optical signal.
28. The package of claim 27 wherein the intermediate wafer further includes a via extending through the intermediate wafer to one or more of the intermediate contact pads.
29. The package of claim 26 further including:
a release layer coupled to a surface of the intermediate wafer; and
a handle coupled to the release layer.
30. The package of claim 29 wherein the handle is removable by etching away the release layer.
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060258120A1 (en) * 2001-12-19 2006-11-16 Gilroy Vandentop J Electrical/optical integration scheme using direct copper bonding
US20080181558A1 (en) * 2007-01-31 2008-07-31 Hartwell Peter G Electronic and optical circuit integration through wafer bonding
FR2990565A1 (en) * 2012-05-09 2013-11-15 Commissariat Energie Atomique METHOD FOR PRODUCING INFRARED DETECTORS
CN103579030A (en) * 2013-10-30 2014-02-12 深圳市志金电子有限公司 Novel chip encapsulation method and chip encapsulation structure
US8778773B2 (en) 2010-12-16 2014-07-15 Soitec Methods for directly bonding together semiconductor structures, and bonded semiconductor structures formed using such methods
EP3141941A1 (en) * 2015-09-10 2017-03-15 ams AG Semiconductor device with photonic and electronic functionality and method for manufacturing a semiconductor device
US9933577B2 (en) * 2016-03-11 2018-04-03 Globalfoundries Inc. Photonics chip
CN112486892A (en) * 2020-12-15 2021-03-12 泰和电路科技（惠州）有限公司 Computing method of binding IC (integrated circuit) control calculator

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6962835B2 (en) 2003-02-07 2005-11-08 Ziptronix, Inc. Method for room temperature metal direct bonding
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
JP4933370B2 (en) * 2007-07-17 2012-05-16 株式会社リコー Method for assembling array type semiconductor laser device
US20110267598A1 (en) * 2010-04-30 2011-11-03 Vestas Wind Systems A/S Optical sensor system and detecting method for an enclosed semiconductor device module
CN101863657B (en) * 2010-06-23 2012-08-22 横店集团东磁股份有限公司 Mn-Zn ferrite material with wide temperature and high initial magnetoconductivity and preparation method thereof
US8803269B2 (en) 2011-05-05 2014-08-12 Cisco Technology, Inc. Wafer scale packaging platform for transceivers
US9748214B2 (en) 2011-10-21 2017-08-29 Santa Barbara Infrared, Inc. Techniques for tiling arrays of pixel elements and fabricating hybridized tiles
US8431436B1 (en) 2011-11-03 2013-04-30 International Business Machines Corporation Three-dimensional (3D) integrated circuit with enhanced copper-to-copper bonding
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US10025033B2 (en) 2016-03-01 2018-07-17 Advanced Semiconductor Engineering, Inc. Optical fiber structure, optical communication apparatus and manufacturing process for manufacturing the same
US9806061B2 (en) * 2016-03-31 2017-10-31 Altera Corporation Bumpless wafer level fan-out package
US10241264B2 (en) 2016-07-01 2019-03-26 Advanced Semiconductor Engineering, Inc. Semiconductor device packages
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
JP7030825B2 (en) * 2017-02-09 2022-03-07 インヴェンサス ボンディング テクノロジーズ インコーポレイテッド Joined structure
US10508030B2 (en) 2017-03-21 2019-12-17 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US10923408B2 (en) 2017-12-22 2021-02-16 Invensas Bonding Technologies, Inc. Cavity packages
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US11004757B2 (en) 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
KR20210009426A (en) 2018-06-13 2021-01-26 인벤사스 본딩 테크놀로지스 인코포레이티드 TV as a pad
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11609391B2 (en) * 2020-05-19 2023-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die
US20240105704A1 (en) * 2022-09-22 2024-03-28 Apple Inc. 3D Package with Chip-on-Reconstituted Wafer or Reconstituted Wafer-on-Reconstituted Wafer Bonding
US20240103238A1 (en) * 2022-09-22 2024-03-28 Apple Inc. 3D System and Wafer Reconstitution with Mid-layer Interposer

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3744120A (en) * 1972-04-20 1973-07-10 Gen Electric Direct bonding of metals with a metal-gas eutectic
US5107118A (en) * 1990-10-01 1992-04-21 Uop Measurement of water levels in liquid hydrocarbon media
US5426849A (en) * 1991-01-09 1995-06-27 Nec Corporation Method of producing a polyimide multilayer wiring board
US6097609A (en) * 1998-12-30 2000-08-01 Intel Corporation Direct BGA socket
US6107118A (en) * 1995-08-10 2000-08-22 Elke Zakel Chip-contacting method requiring no contact bumps, and electronic circuit produced in this way
US6204164B1 (en) * 1995-08-21 2001-03-20 Mitel Corporation Method of making electrical connections to integrated circuit
US6204165B1 (en) * 1999-06-24 2001-03-20 International Business Machines Corporation Practical air dielectric interconnections by post-processing standard CMOS wafers
US6243509B1 (en) * 1999-08-27 2001-06-05 Board Of Regents - The University Of Texas System Packaging enhanced board level opto-electronic interconnects
US20020076130A1 (en) * 2000-12-14 2002-06-20 Gregory Pandraud Integrated optical device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4937653A (en) * 1988-07-21 1990-06-26 American Telephone And Telegraph Company Semiconductor integrated circuit chip-to-chip interconnection scheme
US5097609A (en) * 1990-12-14 1992-03-24 Swaggert Patrick J Portable draft bar
SE467344B (en) 1990-12-19 1992-07-06 Nike Luftverktyg Ab HANDHAALLEN ELDRIVEN CIRCLE SAW WITH A PULLABLE AND LOADABLE BUSINESS
US5418002A (en) * 1990-12-24 1995-05-23 Harris Corporation Direct bonding of copper to aluminum nitride substrates
US5757989A (en) * 1992-09-10 1998-05-26 Fujitsu Limited Optical circuit system capable of producing optical signal having a small fluctuation and components of same
EP0801423B1 (en) * 1996-04-08 2008-09-17 Raytheon Company Hdmi decal and fine line flexible interconnect forming methods
US5977567A (en) * 1998-01-06 1999-11-02 Lightlogic, Inc. Optoelectronic assembly and method of making the same
US6060795A (en) * 1998-03-18 2000-05-09 Intersil Corporation Semiconductor power pack
JP2000199827A (en) * 1998-10-27 2000-07-18 Sony Corp Optical wave guide device and its manufacture
TW460717B (en) * 1999-03-30 2001-10-21 Toppan Printing Co Ltd Optical wiring layer, optoelectric wiring substrate mounted substrate, and methods for manufacturing the same
US6902987B1 (en) * 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US6512861B2 (en) * 2001-06-26 2003-01-28 Intel Corporation Packaging and assembly method for optical coupling
US20030113947A1 (en) 2001-12-19 2003-06-19 Vandentop Gilroy J. Electrical/optical integration scheme using direct copper bonding

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3744120A (en) * 1972-04-20 1973-07-10 Gen Electric Direct bonding of metals with a metal-gas eutectic
US5107118A (en) * 1990-10-01 1992-04-21 Uop Measurement of water levels in liquid hydrocarbon media
US5426849A (en) * 1991-01-09 1995-06-27 Nec Corporation Method of producing a polyimide multilayer wiring board
US6107118A (en) * 1995-08-10 2000-08-22 Elke Zakel Chip-contacting method requiring no contact bumps, and electronic circuit produced in this way
US6204164B1 (en) * 1995-08-21 2001-03-20 Mitel Corporation Method of making electrical connections to integrated circuit
US6097609A (en) * 1998-12-30 2000-08-01 Intel Corporation Direct BGA socket
US6204165B1 (en) * 1999-06-24 2001-03-20 International Business Machines Corporation Practical air dielectric interconnections by post-processing standard CMOS wafers
US6243509B1 (en) * 1999-08-27 2001-06-05 Board Of Regents - The University Of Texas System Packaging enhanced board level opto-electronic interconnects
US20020076130A1 (en) * 2000-12-14 2002-06-20 Gregory Pandraud Integrated optical device

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7359591B2 (en) 2001-12-19 2008-04-15 Intel Corporation Electrical/optical integration scheme using direct copper bonding
US20080135965A1 (en) * 2001-12-19 2008-06-12 Gilroy Vandentop J Electrical/optical integration scheme using direct copper bonding
US7826694B2 (en) 2001-12-19 2010-11-02 Intel Corporation Electrical/optical integration scheme using direct copper bonding
US20060258120A1 (en) * 2001-12-19 2006-11-16 Gilroy Vandentop J Electrical/optical integration scheme using direct copper bonding
US20080181558A1 (en) * 2007-01-31 2008-07-31 Hartwell Peter G Electronic and optical circuit integration through wafer bonding
US8778773B2 (en) 2010-12-16 2014-07-15 Soitec Methods for directly bonding together semiconductor structures, and bonded semiconductor structures formed using such methods
US9318527B2 (en) 2012-05-09 2016-04-19 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for producing photosensitive infrared detectors
FR2990565A1 (en) * 2012-05-09 2013-11-15 Commissariat Energie Atomique METHOD FOR PRODUCING INFRARED DETECTORS
CN103579030A (en) * 2013-10-30 2014-02-12 深圳市志金电子有限公司 Novel chip encapsulation method and chip encapsulation structure
EP3141941A1 (en) * 2015-09-10 2017-03-15 ams AG Semiconductor device with photonic and electronic functionality and method for manufacturing a semiconductor device
WO2017042035A1 (en) * 2015-09-10 2017-03-16 Ams Ag Semiconductor device with photonic and electronic functionality and method for manufacturing a semiconductor device
US10684412B2 (en) 2015-09-10 2020-06-16 Ams Ag Semiconductor device with photonic and electronic functionality and method for manufacturing a semiconductor device
US9933577B2 (en) * 2016-03-11 2018-04-03 Globalfoundries Inc. Photonics chip
US10409006B2 (en) 2016-03-11 2019-09-10 Globalfoundries Inc. Photonics chip
CN112486892A (en) * 2020-12-15 2021-03-12 泰和电路科技（惠州）有限公司 Computing method of binding IC (integrated circuit) control calculator

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US7826694B2 (en) 2010-11-02
US20080135965A1 (en) 2008-06-12
EP1456879A2 (en) 2004-09-15
WO2003054954A2 (en) 2003-07-03
US20060258120A1 (en) 2006-11-16
AU2002359506A8 (en) 2003-07-09
US7359591B2 (en) 2008-04-15
AU2002359506A1 (en) 2003-07-09
WO2003054954A3 (en) 2004-04-08

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