TWI731773B - Semiconductor package and method for forming the same - Google Patents

Abstract

A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.

Description

Semiconductor package and its forming method

The embodiment of the present invention relates to a semiconductor package. More specifically, the embodiment of the present invention relates to a semiconductor package with encapsulant.

Due to the continuous improvement of the integrated density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.), the semiconductor industry has experienced rapid growth. In most cases, the improvement in integrated density has been derived from repeated reductions in the smallest feature size, which reduction allows more components to be integrated into a given area. Because of the growing demand for downsizing electronic devices, there has been a demand for smaller and more innovative semiconductor chip packaging technologies. An example of such a packaging system is a package-on-package (PoP) technology. In the stacked package stacking device, the top semiconductor package is stacked on top of the bottom semiconductor package to provide a high degree of integration and element density. The stacked package stacking technology can generally produce semiconductor devices with enhanced functionality and small footprints on a printed circuit board (PCB).

An embodiment of the present invention provides a method for forming a semiconductor package, including forming a first element, and forming the first element includes: forming a first redistribution structure on a first substrate; A through hole is formed thereon; a first chip is attached to the first redistribution structure, and the active side of the first chip is facing and electrically coupled to the first redistribution structure. The method of forming the semiconductor package further includes attaching a second element to the through hole, the second element including a second rewiring structure attached to a second substrate, and after attaching the second element, the first A molding material is deposited between the redistribution structure and the second redistribution structure, and a part of the molding material surrounds the side edge of the second redistribution structure.

The embodiment of the present invention also provides a semiconductor package, which includes a first element, a second element, and an encapsulant. The first component includes a first rewiring structure, a through hole, and a first chip. The through hole is provided on the first rewiring structure. The first chip is attached to the first redistribution structure, and the active side surface of the first chip faces the first redistribution structure. The second component includes a second rewiring structure, a connector, and a second chip. The connector couples the through hole to the second redistribution structure. The second chip is attached to a first side of the second redistribution structure, and the active side surface of the second chip faces the second redistribution structure. The packaging glue is arranged between the first rewiring structure and the second rewiring structure.

The embodiment of the present invention further provides a semiconductor package, including a first rewiring structure, a second rewiring structure, a first chip, a second chip, a packaging compound, and a through hole. The first rewiring structure has a first width. The second rewiring structure is disposed on the first rewiring structure and includes a conductive via extending from a first metal trace to a second metal trace. The first metal trace is disposed along a first side of the second rewiring structure, and the second metal trace is disposed along a second side of the second rewiring structure. The second rewiring structure has a second width, and the first width is greater than the second width. The first chip is attached to the first redistribution structure, and a first active side of the first chip is facing and electrically coupled to the first redistribution structure. The second chip is attached to the second redistribution structure, and a second active side of the second chip faces and is electrically coupled to the second redistribution structure. The packaging glue is directly inserted between the first rewiring structure and the second rewiring structure. The through hole extends through the packaging glue, and the through hole electrically couples the first redistribution structure to the second redistribution structure.

The following disclosure provides many different embodiments or examples to implement different features of this case. The following disclosure describes specific examples of each component and its arrangement to simplify the description. Of course, these specific examples are not meant to be limiting. For example, if this disclosure describes that a first feature is formed on or above a second feature, it means that it may include an embodiment in which the first feature and the second feature are in direct contact, or it may include additional The feature is formed between the first feature and the second feature, and the first feature and the second feature may not be in direct contact with each other. In addition, the same reference symbols and/or marks may be used repeatedly in different examples of the following disclosure. These repetitions are for the purpose of simplification and clarity, and are not used to limit the specific relationship between the different embodiments and/or structures described.

Furthermore, in order to facilitate the description of the relationship between one element or feature and another (plural) element or (plural) feature in the diagram, spatially related terms such as "below", "below", "below", "above" can be used ", "above" and similar terms, etc. In addition to the orientations shown in the diagrams, space-related terms cover different orientations of the device in use or operation. The device can also be positioned separately (rotated by 90 degrees or in other orientations), and the spatial description used here can also be correspondingly interpreted.

According to some embodiments, one or more integrated circuit chips or other devices are attached to multiple dual-sided redistribution structures and embedded in the package to form a semiconductor system-in-package (system-in-package). -in-package, SiP) structure. One of the redistribution structures may have a fan-out design, and the other redistribution structure may be formed as a carrier-type substrate. The placement of integrated circuit chips and the placement of rewiring structures provide diversity throughout the package. In addition, the design of the package and rewiring structure, and the design method (methodology) enable the thinner system-in-package structure to have better strength and reduce overall package warpage.

FIG. 1 shows a cross-sectional view of an integrated circuit chip 50 according to some embodiments. The integrated circuit chip 50 will be packaged in a subsequent process to form an integrated circuit package. The integrated circuit chip 50 may be a logic chip (for example, a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip, SoC), an application Processor (application processor, AP), microcontroller (microcontroller), etc.), a memory chip (such as dynamic random access memory (DRAM) chip, static random access memory) , SRAM) chip, etc.), a power management chip (such as power management integrated circuit (PMIC) chip), a radio frequency (RF) chip, a sensor chip, a microelectromechanical system (micro -electro-mechanical-system, MEMS) chip, a signal processing chip (e.g. digital signal processing (DSP) chip), a front-end chip (e.g. analog front-end (AFE) chip), the like , Or a combination thereof.

The integrated circuit chip 50 may be formed in a wafer, and the wafer may include a plurality of different device regions singulated in a subsequent step to form a plurality of integrated circuit chips. The integrated circuit chip 50 can be processed according to an applicable manufacturing process to form a crystal circuit. For example, the integrated circuit chip 50 includes a semiconductor substrate 52, such as an active layer of silicon, doped or undoped, or a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 may include other semiconductor materials, such as germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide), alloy semiconductors (including germanium silicide ( SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), gallium indium phosphide (GaInP), and/or indium arsenic phosphide Gallium (GaInAsP)), or a combination thereof. Other substrates such as multilayer or gradient substrates can also be used. The semiconductor substrate 52 has an active surface (for example, the surface facing upward in FIG. 1) and an inactive surface (for example, the surface facing downward in FIG. 1). The active surface is sometimes referred to as a front side and is inactive. The surface is sometimes referred to as a dorsal side.

A plurality of devices (one shown in FIG. 1) 54 may be formed on the front surface of the semiconductor substrate 52. The device 54 may be an active device (for example, transistors, diodes, etc.), capacitors, resistors, and the like. An inter-layer dielectric (ILD) 56 is on the front surface of the semiconductor substrate 52. The interlayer dielectric 56 surrounds the device 54 and can cover the device 54. The interlayer dielectric 56 may include one or more dielectric layers, and the material for forming the dielectric layer is, for example, Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG) ), Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG), or the like.

The conductive plug 58 extends through the interlayer dielectric 56 and is physically coupled with the device 54. For example, when the device 54 is a transistor, the conductive plug 58 may be coupled with the gate and source/drain regions of the transistor. The conductive plug 58 may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, the like, or a combination thereof. The interconnect structure 60 is above the interlayer dielectric 56 and the conductive plug 58. The interconnect structure 60 and the device 54 are interconnected to form an integrated circuit. For example, the interconnect structure 60 may be formed by a metallization pattern in the dielectric layer of the interlayer dielectric 56. The metallization pattern includes metal lines and vias formed by one or more low-k dielectric layers. The metallization pattern of the interconnect structure 60 is electrically coupled to the device 54 through the conductive plug 58.

The integrated circuit chip 50 further includes a plurality of pads 62 to establish external connections, such as aluminum pads. The pad 62 is located on the active side of the integrated circuit chip 50, for example, in and/or on the interconnect structure 60. One or more passivation films 64 are located on the integrated circuit wafer 50, for example, on the interconnection structure 60 and the pad 62. The opening extends through the passivation film 64 to the liner 62. The chip connector 66 extends through the opening in the passivation film 64 and is physically and electrically coupled to each pad 62. The aforementioned chip connector 66 is, for example, a conductive post (for example, formed of a metal such as copper). In some embodiments, the chip connector 66 includes an under-bump metallization (UBM) structure. Although only four chip connectors 66 are shown in Figure 1, there may be more, which will be shown in subsequent drawings of the integrated circuit chip 50. For example, the chip connector 66 (e.g., copper pillar) may be formed by electroplating or the like. The chip connector 66 electrically couples each integrated circuit of the integrated circuit chip 50.

Optionally, solder regions (such as solder balls or solder bumps, not shown) may be provided on the pad 62 and/or the chip connector 66. The solder area can be used to perform a chip probe (CP) test on the integrated circuit chip 50. The die pin test can be performed on the integrated circuit chip 50 to confirm whether the integrated circuit chip 50 is a known good die (KGD). Therefore, only the integrated circuit chip 50 with a good bare die will be packaged in the subsequent manufacturing process, and the integrated circuit chip 50 that fails the bare die pin test test will not be packaged. After the test, the solder area can be removed in a subsequent process step.

A dielectric layer 68 may (or may not) be provided on the active side of the integrated circuit chip 50, for example, on the passivation film 64 and the chip connector 66. The dielectric layer 68 encapsulates the chip connector 66 laterally, and the dielectric layer 68 is laterally connected to the integrated circuit chip 50 after singulation. Initially, the dielectric layer 68 can bury the chip connector 66 so that the topmost surface of the dielectric layer 68 will be above the topmost surface of the chip connector 66. In some embodiments where the solder area is provided on the chip connector 66, the dielectric layer can also bury the solder area. Alternatively, the solder area may be removed before the dielectric layer 68 is formed.

The dielectric layer 68 can be a polymer (such as PBO, polyimide, BCB, or the like), nitride (such as silicon nitride or the like), oxide (such as silicon oxide, PSG, BSG, BPSG, or Analogs), analogs, or combinations thereof. For example, the dielectric layer 68 can be formed by spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments, the die connector 66 is exposed through the dielectric layer 68 during the formation of the integrated circuit die 50. In some embodiments, the chip connector 66 remains buried and exposed during the subsequent process of packaging the integrated circuit chip 50. Exposing the chip connector 66 can remove any solder area present on the chip connector 66.

An adhesive layer 70 may be applied to the back side of the integrated circuit chip 50 at certain points in the manufacturing process. In some embodiments, the adhesive layer is formed on the backside of the integrated circuit die 50 before attaching the integrated circuit die to a semiconductor package component (to be described in detail below).

In some embodiments, the integrated circuit wafer 50 is a stacked device including a plurality of semiconductor substrates 52. For example, the integrated circuit chip 50 may be a memory device, such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, or include multiple memory chips The analogue. In these embodiments, the integrated circuit chip 50 includes a plurality of semiconductor substrates 52 interconnected by through-substrate vias (TSVs). Each semiconductor substrate 52 may (or may not) have an interconnect structure 60.

The formation of a semiconductor package including an integrated circuit die 50 according to some embodiments will be described below. Figures 2A to 2G illustrate various intermediate steps in the formation of a first element according to some embodiments. As will be discussed, the first component may include a fan-out rewiring structure with integrated circuit chip 50 attached. Figures 3A to 3H describe the formation of a second element according to some embodiments, where the second element can be attached to the first element described with reference to Figures 2A to 2G. As will be discussed, the second element may include a substrate type rewiring structure. Although not specifically described, the second element may also include a fan-out rewiring structure, and this fan-out rewiring structure is similar to the fan-out rewiring structure of the first element. FIGS. 4A to 4H describe the attachment of the second element to the first element and the further process to form a semiconductor package according to some embodiments.

First, referring to FIG. 2A, in the formation of a first element 100, a first carrier substrate 102 is provided, and a release layer 104 is formed on the first carrier substrate 102. The first carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The first carrier substrate 102 can be a wafer, so that multiple packages can be formed on the first carrier substrate 102 at the same time, and each package can include one or more chips. The release layer 104 may be formed of a polymer-based material, which can be removed from the overlying structure together with the first carrier substrate 102, and the overlying structure is formed in a subsequent step. In some embodiments, the release layer 104 is an epoxy-based material, which loses its adhesiveness when heated, such as a light-to-heat-conversion (LTHC) release coating. In some embodiments, the release layer 104 may be an ultraviolet (UV) glue, which loses its adhesiveness when exposed to ultraviolet light. The release layer 104 may be dispensed and cured in a liquid form, may be a laminated film laminated on the first carrier substrate 102, or may be the like.

In FIGS. 2B to 2E, a first focused wiring structure 106 may be formed on the release layer 104. In the illustrated embodiment, the first focused wiring structure 106 includes one or more dielectric layers and metallization patterns (sometimes referred to as redistribution layers or redistribution lines). The first side rewiring structure 106 will be described as having a three-layer metallization pattern. More or fewer dielectric layers and metallization patterns can also be formed in the first focused wiring structure 106. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be repeated.

Now referring to FIG. 2B, a dielectric layer 110 is formed on the release layer 104. The bottom surface of the dielectric layer 110 may contact the top surface of the release layer 104. In some embodiments, the dielectric layer 110 may be formed of a photosensitive material (photo-sensitive material), such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or Similarly, it can be patterned using a lithography mask. In some embodiments, the dielectric layer 110 is formed of nitride, such as silicon nitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (boron-doped phosphosilicate glass, BPSG), or similar. The dielectric layer 110 may be formed by spin coating, lamination, chemical vapor deposition, similar methods, or a combination thereof. The dielectric layer 110 is patterned to form an opening exposing a portion of the release layer 104. Patterning can be done by acceptable processes, such as by exposing the dielectric layer 110 to light, developing, and curing when the dielectric layer 110 is a photosensitive material, or by etching, for example, using anisotropic Etching.

The metallization pattern 112 is then formed on the dielectric layer 110. The metallization pattern 112 includes a circuit portion (also referred to as a wire), which is located on the main surface of the dielectric layer 110 and extends along the main surface of the dielectric layer 110. The metallization pattern 112 further includes a via portion (also referred to as a conductive via), which extends through the dielectric layer 110 so that the first focused wiring structure 106 is physically and electrically coupled to an external connector. The external connection The device can be formed in a later step. As an example of forming the metallization pattern 112, a seed layer is formed on the dielectric layer 110 and in the opening extending through the dielectric layer 110. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer, and the copper layer is located on the titanium layer. For example, the seed layer can be formed by physical vapor deposition (PVD) or similar methods. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like, and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 112. The patterning will form an opening through the photoresist to expose the seed layer. A conductive material is then formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by electroplating (for example, electroplating or electroless plating) or the like. The conductive material may include metals such as copper, titanium, tungsten, aluminum, or the like. The part of the photoresist and the seed layer where no conductive material is formed will be removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. Once the photoresist is removed, the exposed portion of the seed layer will be removed, for example by using an acceptable etching process, such as by wet etching or dry etching. The remaining part of the conductive material and the bottom part of the seed layer form the metallization pattern 112.

In FIG. 2C, a dielectric layer 114 is deposited on the metallization pattern 112 and the dielectric layer 110. The dielectric layer 114 may be formed and patterned in a similar manner to the dielectric layer 110.

Next, a metallization pattern 116 is formed. The metallization circuit 116 includes a circuit portion, which is located on the main surface of the dielectric layer 114 and extends along the main surface of the dielectric layer 114. The metallization pattern 116 further includes a via hole portion extending through the dielectric layer 114 to physically and electrically couple the metallization pattern 112. The metallization pattern 116 may be formed in a similar manner and similar materials to the metallization pattern 112. In some embodiments, the metallization pattern 116 has a different size from the metallization pattern 112. For example, the wires and/or vias of the metallization pattern 112 may be wider or thicker than the wires and/or vias of the metallization pattern 116. Furthermore, the metallization pattern 112 can be formed to have a larger pitch than the metallization pattern 116.

In FIG. 2D, a dielectric layer 118 is deposited on the metallization pattern 116 and the dielectric layer 114. The dielectric layer 118 may be formed and patterned in a similar manner to the dielectric layer 110 and/or the dielectric layer 114.

Next, the metallization pattern 120 is formed. The metallization pattern 120 includes a circuit portion, which is located on the main surface of the dielectric layer 118 and extends along the main surface of the dielectric layer 118. The metallization pattern 120 further includes a via portion extending through the dielectric layer 118 to physically and electrically couple the metallization pattern 116. The metallization pattern 120 may be formed in a similar manner and similar materials to the metallization pattern 112 and/or the metallization pattern 116.

In FIG. 2E, a dielectric layer 122 is deposited on the metallization pattern 120 and the dielectric layer 118. The dielectric layer 122 may be formed and patterned in a similar manner to the dielectric layer 110 to form the opening 124.

The dielectric layer 110 and the metallization pattern 112 are respectively the dielectric layer and the metallization pattern at the bottom of the first focused wiring structure 106. Therefore, all the intermediate dielectric layers and metallization patterns (for example, the dielectric layers 114, 118, 122, and the metallization patterns 116, 120) of the first focused wiring structure 106 are disposed on the dielectric layer 110/metallization pattern 112 And the components to be subsequently formed or attached on the first focused wiring structure 106. In some embodiments, the metallization pattern 112 has a different size from the metallization patterns 116 and 120. For example, the conductive lines of the metallization pattern 112 may have a thickness of about 0.5 micrometers to about 15 micrometers, or about 5 micrometers, and the conductive lines of the metalized patterns 116 and 120 may have a thickness of about 0.5 micrometers to about 15 micrometers, Or a thickness of about 5 microns. The ratio of the thickness of the metallization pattern 112 to the thickness of the metallization pattern 120 may be about 0.3 to about 3, or about 1. Furthermore, the metallization pattern 112 can be formed to have a larger pitch than the metallization patterns 116 and 120. For example, the conductive lines of the metallization pattern 112 may have a pitch of about 1 micron to about 100 micrometers, or a pitch of about 10 micrometers, and the conductive lines of the metalized lines 116 and 120 may have a pitch of about 1 micron to about 100 micrometers, Or a pitch of about 10 microns. The ratio of the pitch of the metallization pattern 112 to the pitch of the metallization pattern 120 may be about 0.1 to about 10, or about 1. It should be noted that the first focused wiring structure 106 may include any number of dielectric layers and metallization patterns. If more dielectric layers and metallization patterns are to be formed, the aforementioned steps and processes can be repeated.

In FIG. 2F, through vias 126 are formed in some openings 124 and extend away from the topmost dielectric layer (such as the dielectric layer 122) of the first weighted wiring structure 106. As an example of forming the through hole 126, a seed layer (not shown) is formed on the first focused wiring structure 106, for example, on the portion of the dielectric layer 122 and the metallization pattern 120 exposed through the opening. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer, and the copper layer is located on the titanium layer. In some embodiments, the seed layer is made of copper, titanium, nickel, gold, palladium, the like, or a combination thereof. For example, the seed layer can be formed by physical vapor deposition (PVD) or similar methods. A mask (such as a photoresist (not shown)) is formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like, and can be exposed to light for patterning. The pattern of the photoresist corresponds to the through hole 126 and exposes the seed layer. A conductive material is then formed in the opening of the photoresist and on the exposed portion of the seed layer. Conductive materials can be electroplated (e.g., electro-chemical plating process or electroless plating), chemical vapor deposition, atomic layer deposition (ALD), physical vapor deposition, etc. Way, or a combination thereof. The conductive material may include metals such as copper, titanium, tungsten, aluminum, or the like. The photoresist can be removed.

Please continue to refer to FIG. 2F, the bonding pads 128 are formed in some openings 124 and extend away from the dielectric layer 122. The bonding pad 128 may be formed in a similar manner to the through hole 126 and may be formed of the same material as the through hole 126. In addition, the bonding pad 128 may be formed before, after, or simultaneously with the through hole 126.

The photoresist used for the bonding pad 128 and the through hole 126 and the portion of the seed layer where the bonding pad 128 and the through hole 126 are not formed will be removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. Once the photoresist is removed, the exposed portion of the seed layer will be removed, for example by using an acceptable etching process, such as by wet etching or dry etching. The remaining portions of the seed layer and the conductive material form bonding pads 128 and through holes 126.

As mentioned above, an integrated circuit chip (for example, the integrated circuit chip 50 described above with reference to FIG. 1) can be attached to the bonding pad 128. In some embodiments, the bonding pad 128 is an under bump metallization structure (UBMs), for example, it may include three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. Other material and layer configurations can also be used to form the bonding pad 128, such as a chromium/chromium-copper alloy/copper/gold configuration, a titanium/titanium tungsten/copper configuration, or a copper/nickel/gold configuration. Any suitable material and material layer that can be used for the bonding pad 128 are fully included in the scope of the embodiments of the present invention.

In FIG. 2G, one or more semiconductor devices (such as the first integrated circuit chip 50) will be attached to the bonding pad 128 to establish an electrical connection with the first focused wiring structure 106. For example, the first integrated circuit chip 50 can be formed by forming solder joints 130 on the chip connector 66 (whether it is a conductive pillar or an under-bump metallization structure), pressing the chip connector 66 to the bonding pad 128, And the reflow solder joint 130 is used to bond the first integrated circuit chip 50 to the first focused wiring structure 106 for bonding. In some embodiments, the first integrated circuit die 50 may be attached by direct metal-to-metal bonding or hybrid bonding. FIG. 2G depicts that the integrated circuit chip 50 has a higher height than the through hole 126. However, it should be noted that the through hole 126 may have a height approximately equal to or higher than that of the integrated circuit chip 50. For example, the through hole 126 may have a height H _{TV of} about 10 micrometers to about 200 micrometers, and the integrated circuit chip 50 may have a height H _{IC1 of} about 30 micrometers to about 250 micrometers. The ratio of the height H _{TV to the} height H _IC1 may be about 0.04 to about 8.

It should be noted that, for the integrated circuit chip 50, the first focused wiring structure 106 may be a fan-out type rewiring structure. Therefore, the metallization patterns (for example, the metallization patterns 112, 116, 120) may extend more than the integrated circuit chip 50 in the lateral direction. The fan-out design allows a thinner rewiring structure and can also accommodate more external connectors, which can therefore extend more laterally than the integrated circuit chip 50. The first side rewiring structure 106 is formed to have a thickness T ₁ , and the thickness T ₁ may be about 20 μm to 100 μm.

An underfill material 132 may be distributed between the first integrated circuit chip 50 and the first focused wiring device 106. The underfill material 132 surrounds the solder joint 130 and the bonding pad 128. The underfill material 132 can be any acceptable material, such as polymer, epoxy, molding underfill, or the like. The underfill material 132 may be dispensed by a needle or jet dispenser, dispensed by a capillary flow process, or dispensed by other suitable processes. In some embodiments, a curing process may be performed to cure the underfill material 132. Although not explicitly shown in FIG. 2G, the underfill material 132 may extend along the sidewall of the first integrated circuit chip 50.

For illustrative purposes, FIG. 2G shows a single integrated circuit die 50 attached to the bonding pad 128. In some embodiments, two or more integrated circuit chips 50 (each integrated circuit chip 50 has the same or different functions) may be attached to the bonding pad 128.

3A to 3H are cross-sectional views showing intermediate steps during the process of forming a second element 200 according to some embodiments. As mentioned above, the second element 200 can then be attached to the first element 100 described in relation to FIGS. 2A-2G. The second device 200 can be formed as a separate package or can be formed by a wafer-level process. Only one individual packaged component 200 is shown, but it should be noted that the second component 200 can be part of the wafer. After formation, the individual second element 200 will be singulated. The final second device 200 can also be referred to as an integrated package.

In FIG. 3A, a second carrier substrate 202 is provided, and a second focused wiring structure can be formed on the second carrier substrate 202. The second carrier substrate 202 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The second carrier substrate 202 can be a wafer, so that multiple packages can be formed on the second carrier substrate 202 at the same time. A first metal film 204 is formed on the second carrier substrate 202. The first metal film 204 may include copper, such as a copper foil. The second carrier substrate 202 may have a thickness of about 10 micrometers to about 400 micrometers, or a thickness of about 200 micrometers. The first metal film 204 may have a thickness of about 1 micrometer to about 20 micrometers, or a thickness of about 3 micrometers. The first metal film 204 may include copper or other conductive materials.

In FIG. 3B, a photoresist 208 is then formed and patterned on the first metal film 204. The photoresist 208 can be formed by spin coating or the like, and can be exposed to light for patterning. The patterning will form an opening through the photoresist 208 to expose the first metal film 204.

In FIG. 3C, a second focused wiring structure 206 is formed on the first metal film 204. First, a first metal trace 210 is formed on the first metal film 204, and the photoresist 208 is removed. The first metal trace 210 may be formed by electroplating and may include one or more layers of conductive materials. For example, a layer of gold (Au) can be deposited first, a layer of nickel (Ni) second, and a layer of copper (Cu) last. Gold can be deposited to a thickness greater than or about 0.1 microns, for example, from about 0.01 microns to about 3 microns. Nickel can be deposited to a thickness greater than or about 3 microns, for example from about 0.1 microns to about 10 microns. Copper can be deposited to a thickness greater than or about 7 microns, for example, about 1 to about 25 microns. Therefore, the first metal trace 210 may have a thickness greater than or about 1 micrometer to 35 micrometers, for example, greater than or about 10 micrometers. Such a thickness is beneficial for adhering the first metal trace 210 to the first metal film 204, maintaining internal cohesiveness, and/or providing sufficient electrical conductivity. A thickness less than this may cause poor adhesion, cohesion, and/or conductivity. The photoresist 208 can be removed by any suitable stripping method.

In FIG. 3D, a dielectric layer 212 is formed on the first metal trace 210. The dielectric layer 212 may be formed by a thermal lamination process. The dielectric layer 212 may include prepreg or ABF film (Ajinomoto Build-up Film). In some embodiments, the dielectric layer 212 may be a prepreg having a thickness of about 10 microns to about 100 microns, such as about 30 microns, or may be an ABF film having a thickness of about 10 microns to about 100 microns, such as About 20 microns. The advantage of using prepreg or ABF film material as the dielectric layer 212 is that the second-focused wiring structure 206 will have a high level of strength and reliability. When coupled with the first focused wiring structure 106 later, the entire semiconductor package will not be easily warped.

In FIG. 3E, the dielectric layer 212 is patterned to form an opening exposing a portion of the first metal trace 210. The opening includes via openings 214 extending through the dielectric layer 212 to expose a portion of the first metal trace 210. The openings further include line openings 216, which are connected to the via openings 214 and provide routing capabilities. The dielectric layer 212 can be patterned by a single damascene or dual damascene process. Patterning can be performed by any suitable method, such as forming a photoresist and wet etching or dry etching the dielectric layer 212 and/or using a laser ablation (or laser drilling) technology. Although depicted as vertical sidewalls, it should be noted that the laser drilling technique can produce via openings 214 with non-vertical sidewalls. The via opening 214 may have a width of about 30 microns to about 150 microns, for example, about 65 microns.

In Figure 3F, the via opening 214 and the circuit opening 216 in the area above the dielectric layer 212 will be filled with a conductive material to form the conductive via 218 (in the via opening 214) and the second metal trace 220 ( In the line opening 216). The conductive material can be deposited by electroplating or electroless plating, or any suitable method. The second metal trace 220 may have a thickness of about 10 microns. Alternatively, the conductive via 218 may be initially formed before the dielectric layer 212 is patterned to form the second metal trace 220.

The second focused wiring structure 206 (including the first metal trace 210, the conductive via 218, and the second metal trace 220) is formed to have a thickness T ₂ , and the thickness T ₂ may be about 20 micrometers to about 150 micrometers. The thickness of the second focused wiring structure 206 may be greater than or equal to the thickness T _{1 of the} back focused wiring structure 106. The ratio of the thickness T _{2 to the} thickness T ₁ may be about 0.3 to about 3. The ratio within this range provides suitable rigidity to avoid or reduce the warpage caused by different coefficients of thermal expansions (CTEs). For example, when the second element 200 is then attached to the first element 100 At this time, the first focus is on the different thermal expansion coefficients of the dielectric layer and metallization pattern of the wiring structure 106 and the material including the integrated circuit chip 50. A ratio smaller than this value may not provide sufficient rigidity for the second element 200 to counteract the element expansion of the first element 100. A ratio greater than this value may increase the signal length, thereby reducing the performance of the packaged device.

In FIG. 3G, the solder resist material 222 is formed and patterned to form an opening 224 exposing the conductive via 218 and/or the second metal trace 220. In addition, for protection purposes, the exposed portions of the conductive via 218 and the second metal trace 220 may be processed. For example, eletroless nickel electroless palladium immersion glod (ENEPIG) treatment or organic solderability preservative (OSP) can be implemented on the exposed portions of the conductive via 218 and the second metal trace 220. The solder resist material may have a thickness of about 5 microns to about 40 microns, for example, about 10 microns. The solder resist material 222 can also be used to protect the protection area of the second focused wiring structure 206 from external damage.

In FIG. 3H, the connector 226 is formed on the exposed portion of the conductive via 218 and the second metal trace 220. The connector 226 may be a solder ball, formed in a method similar to the solder area on the first integrated circuit die 50, and may be formed in a material similar to the solder area on the first integrated circuit die 50.

For the wafer-level process to form the second device 200, a singulation process can be performed by sawing along the scribe area (dicing path) of the adjacent second device 200. As explained below, the resulting singularized second element 200 is coupled to the first element 100. In some embodiments, before the second element 200 is attached, the first element 100 is similarly singulated. In some embodiments, the first element 100 is singulated after being attached to the second element 200.

4A to 4H are cross-sectional views of intermediate steps of attaching the second device 200 to the first device 100 and additional manufacturing processes to form a package 400 according to some embodiments.

First, please refer to FIG. 4A. The package 400 is shown in which the first element 100 is a part of the wafer. In some embodiments (but not shown in FIG. 4A), the first element 100 has been singulated in the scribe area 404.

Each singulated second element 200 is mounted to the first element 100 using a connector 226. As mentioned above, the first element 100 includes a through hole 126 for attachment. Therefore, the connector 226 is coupled to the corresponding through hole 126. In some embodiments, the connector 226 is reflowed to attach the second component 200 to the through hole 126. The connector 226 electrically couples the second component 200 to the first focused wiring structure 106 of the first package component 100. The connector 226 may have epoxy flux (not shown) formed thereon, because after the second component 200 is attached to the first component 100, it will interact with the remaining epoxy flux. At least some of the epoxy part is reflowed. The remaining epoxy resin portion can act as an underfill to reduce stress and protect the contacts created by the reflow connector 226. After the second component 200 is attached to the first component 100, the first focused wiring structure 106 and the second focused wiring structure 206 can be separated from each other by a thickness T ₃ . The thickness T ₃ may be about 50 microns to about 500 microns. The ratio of the thickness T _{3 to the} thickness T ₁ may be about 0.4 to about 5. The ratio of the thickness T _{3 to the} thickness T ₂ may be about 0.3 to about 4.

In FIG. 4B, an encapsulant 310 is formed on the first element 100 and surrounds the second element 200. The encapsulant 310 further encapsulates the through hole 126, the first integrated circuit chip 50, and any other devices attached to the first device 100 and/or the second device 200 (if any). The encapsulant 310 is further formed in the gap area of the adjacent second element 200. The encapsulant 310 can be formed by a capillary flow process after the second package component 200 is attached, or can be formed by a suitable deposition method before the second package component 200 is attached. In some embodiments, the encapsulant 310 may be applied by compression molding, transfer molding, or similar methods. The encapsulant 310 may be applied in a liquid or semi-liquid form, and then subsequently cured. The encapsulant 310 may be a molding compound, epoxy resin, or the like.

As indicated by the illustrations 401 and 402 in FIG. 4B, the encapsulant 310 may be formed to surround the side edges of the second focused wiring structure 206 of the second component 200. The encapsulant 310 may partially or completely cover the side edges of the second element 200. For example, as depicted in the illustration 401, the encapsulant 310 may have a concave upper surface, the highest point of which is located at the side edge of the adjacent two devices 200. The encapsulant 310 may partially or completely cover the side edges of the two-sided wiring structure 206. In some embodiments, the encapsulant 310 can further cover the side edges of the second carrier substrate 202. In addition, the lowest point of the upper surface may be lower than the portion of the second focused wiring structure 206 that is closest to the second carrier substrate 202. As depicted in the illustration 402, the encapsulant 310 can be formed to cover all the side edges of the two-sided wiring structure 206 and all or part of the side edges of the second carrier substrate 202. In some embodiments, the encapsulant 310 may cover all the side edges of the second carrier substrate 202, and even a part of the upper surface of the second carrier substrate 202 (not specifically shown).

The encapsulant 310 provides additional support for the second-focused wiring structure 206, which makes the overall package 400 stronger, more reliable, and less likely to warp. As mentioned above, the increased strength and sturdiness comes from the adhesion of the upper part of the encapsulant 310 to the side edges of the second element 200. The encapsulant 310 may be inclined downward in a direction away from the side edge of the second element 200, as depicted in the inset 401 of FIG. 4B. The inclination can be at an angle θ to the horizontal. The angle θ may be about 0 degrees to about 45 degrees, or about 45 degrees to about 60 degrees.

In FIG. 4C, according to some embodiments, the second carrier substrate 202 is removed from the package 400, exposing the second focused wiring structure 206. The second carrier substrate 202 can use, for example, a heat treatment to change the adhesion of the release layer provided on the second carrier substrate 202, so as to be demounted, debonded, or mechanically peeled off from the second focused wiring structure 206 ( peeled off). In some embodiments, an energy source is used to irradiate and heat the release layer until the release layer loses at least some of its own adhesiveness, such as an ultraviolet (UV) laser, a carbon dioxide (carbon dioxide, CO ₂ ) laser, or an infrared (IR) laser. Once executed, the second carrier substrate 202 and the metal film 204 can be physically separated and removed from the second focused wiring structure 206. In some embodiments, a planarization process or a mechanical peeling process may be performed to remove the second carrier substrate 202 to expose the second focused wiring structure 206. The planarization structure can also remove some of the encapsulant 310 that may be formed on the upper layer of the second focused wiring structure 206. For example, the planarization structure can be a chemical-mechanical polish (CMP), a polishing process, or the like. It should be particularly noted that even in the present embodiment, the encapsulant 310 is formed to completely cover the side edges of the second component (and perhaps on the upper surface of the second carrier substrate 202 (for example, the illustration roughly depicted in Figure 4B) 402)), because of the protection of the second carrier substrate 202, the package body 400 is still not easy to mold the encapsulant 310 on the upper surface of the second focused wiring structure 206. Therefore, after the second carrier substrate 202 is removed, there is no encapsulant 310 on the upper surface of the second focused wiring structure 206. Therefore, the topmost surface of the encapsulant 310 may be flush with the upper surface of the second wiring structure 206 or recessed from the upper surface of the second wiring structure 206.

Please continue to refer to FIG. 4C. In some embodiments, the passivation layer 320 is formed and patterned on the exposed second focused wiring structure 206. The passivation layer 320 may be a dielectric material, and its formation method and material may be similar to any of the dielectric layers 110, 114, 118, and 122. Alternatively, the passivation layer 320 may be a solder resist material, and its formation method and material may be similar to the solder resist material 222.

In FIG. 4D, the package 400 can be turned over on the temporary substrate 406 and attached to the temporary substrate 406. The temporary substrate 406 is, for example, tape, wafer, panel, frame, ring, or the like. The first carrier substrate 102 is then removed. In some embodiments, detachment of the carrier substrate is performed to separate (or detach or de-glue) the first carrier substrate 102 from the first focused wiring structure 106, such as the dielectric layer 110. According to some embodiments, the removal includes projecting light (for example, laser light or ultraviolet light) on the release layer 104, so that the release layer 104 is decomposed under the thermal energy of the light, and the first carrier substrate 102 can be removed.

In FIG. 4E, the conductive connector 410 is formed on the first focused wiring structure 106. The conductive connector 410 can be formed by ball grid array (BGA) connectors, solder balls, metal pillars, C4 (controlled collapse chip connection) bumps, micro bumps, and nickel-palladium-gold technology (ENEPIG) Bumps, or the like. The conductive connector 410 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connector 410 is formed by initially forming a layer of solder by evaporation, electroplating, printing, solder transfer, ball placement, or the like Way to form. Once a layer of solder is formed on the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 410 includes a metal pillar (for example, a copper pillar), which is formed by sputtering, printing, electroplating, electroless plating, chemical vapor deposition, or the like. The metal pillar may not require solder and may have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof , And can be formed by electroplating process.

According to some embodiments, if it has not been singulated, the structure can then be singulated along the scribe area 404 (see, for example, Figure 4A). Alternatively, the structure may be singulated before the conductive connector 410 is formed. In some embodiments, the structure can be singulated using one or more saw blades to divide the package 400 into separate pieces to form one or more singulated packages 400. However, any suitable singulation method (including laser ablation or one or more wet etchings) can also be used.

After singulation, the first focused wiring structure 106 has a width W ₁ , and the width W ₁ may be about 3 mm to about 150 mm. The second element 200 and its second focused wiring structure 206 have a width W ₂ , and the width W ₂ may be about 3 mm to about 150 mm. The width W ₂ may be less than or equal to the width W ₁ (for example, the width of the first element and its first rewiring structure 106 ). The ratio of the width W _{1 to the} width W ₂ may be about 1 to about 3, or about 1. The ratio in this range can make the entire semiconductor package less likely to be warped when the second-focused wiring structure 206 is coupled to the first-focused wiring structure 106. In other words, the strength and width W _{2 of the} second wiring structure 206 will balance the warpage that may occur in the first wiring structure 106.

In Figures 4F and 4G, after singulation, the package 400 can be removed from the temporary substrate 406, turned over and attached to another substrate, such as a substrate 503 (for example, a carrier substrate, a package substrate, a printed circuit board (PCB), or the like). As shown in the figure, the package 400 may feature a passivation layer 320 (FIG. 4F) or the passivation layer 320 may be omitted (FIG. 4G). In some cases in the package 400, the through holes 126 may be aligned with the conductive through holes 218, as depicted in the expanded portion of FIG. 4G. Depending on the method of formation, the conductive via 218 may have inwardly inclined sidewalls. In some cases, the inwardly inclined sidewall may have a concave shape, so that the conductive via 218 has an hourglass shape. In addition, the conductive via 218 may have tooth-shaped sidewalls. Some parts of the dentate sidewalls are due to the laser ablation method of drilling through the dielectric layer 212, as previously explained with respect to FIG. 3F.

In Figure 4H, an embodiment is shown, similar to that previously described with respect to Figure 4F, in which an additional device 511 is attached to the substrate 503. The additional devices 511 may include active devices and/or passive devices, such as integrated passive devices and surface mount devices (SMD) (such as capacitors). In addition, the additional device 511 may include devices similar to the integrated circuit chip 50, and devices designed for the intended purpose, such as memory chips (such as dynamic random access memory (DRAM) chips, stacked memory chips). memory die), high bandwidth memory (HBM) chip, etc.), logic chip, central processing unit (CPU) chip, single chip system (SoC), a component on a wafer (CoW), integrated fan-out Type structure (integrated fan-out structure, InFO), package body, the like, or a combination thereof.

FIGS. 5A to 5H and FIGS. 6A to 6H describe the formation of a first element (including the first integrated circuit chip 50) and the formation of a second element (including the second integrated circuit chip 50) according to some embodiments. Attachment), and various intermediate steps of attaching the second element to the first element and forming the semiconductor package.

5A to 5H are cross-sectional views showing intermediate steps of forming the first element 501, the second element 502, and the package body 504 according to some embodiments. Specifically, the drawings depict some intermediate steps of forming the first element 501 and attaching the second element 502 to the first element 501 (and additional steps) to form the package 504.

In FIG. 5A, the first focused wiring structure 106 of the first element 501 is provided, and the through hole 126 and the bonding pad 128 are formed on the first focused wiring structure 106. Processes and materials similar to those previously described with respect to Figures 2A to 2F can be used. In FIG. 5B, the first integrated circuit chip 50 is attached together with one or more other semiconductor devices 550 (only one is shown, but there may be a plurality of additional semiconductor devices). Processes and materials similar to those previously described in Figure 2G can be used.

The first integrated circuit chip 50 and other devices 550 may include devices designed for the intended purpose, such as memory chips (such as dynamic random access memory (DRAM) chips, stacked memory chips (stacked memory die), high bandwidth) Memory (HBM) chip, etc.), logic chip, central processing unit (CPU) chip, single chip system (SoC), on-wafer component (CoW), integrated fan-out structure (InFO), package, and the like , Or a combination thereof. The first integrated circuit chip 50 and the other devices 550 may be formed in the same technology node (technology node) process, or may be formed in the process of a different technology node. For example, the first integrated circuit chip 50 may be a more advanced technology node than other devices 550. The first integrated circuit chip 50 and the other devices 550 may have different sizes (for example, different heights and/or surface areas), or may have the same size (for example, the same heights and/or surface areas). The advantage of the first side rewiring structure 106 is to provide electrical power between the integrated circuit chip 50, other devices 550, the second component 502 that is subsequently attached, and the components that are subsequently attached to the other side of the first rewiring structure 106. Sexual connection.

In some embodiments, the first integrated circuit chip 50 and other devices include transistors, capacitors, inductors, resistors, metallization layers, external connectors, and the like therein, designed for specific functions. In some embodiments, the first integrated circuit die 50 and other devices may include more than one device of the same type, or may include different devices. FIG. 5B shows a single integrated circuit chip 50, but in some embodiments, one, two, or more integrated circuit chips 50 or other devices may be attached to the first focused wiring structure 106. FIG. 5B depicts the integrated circuit chip 50 having a lower height than the through hole 126. This is to accommodate the second component 502, which will include another integrated circuit chip (as shown in the following figures). For example, the through hole 126 may have a height H _{TV of} about 10 micrometers to about 200 micrometers, and the integrated circuit chip 50 may have a height H _{IC1 of} about 30 micrometers to about 250 micrometers. The ratio of the height H _{TV to the} height H _IC1 may be about 0.04 to about 8.

In FIG. 5C, the second focused wiring structure 206 of the second element 502 is provided, and the solder resist material 222 can be formed and patterned to form an opening 228 in addition to the opening 224. Processes and materials similar to those previously described with respect to Figures 3A to 3H can be used. Some or all of the openings 228 may expose portions of the conductive via 218 and the second metal trace 220. The opening 228 and the opening 224 may be formed at the same time or at different time points using the same or different patterning methods.

In FIG. 5D, a second integrated circuit chip 50 can be attached to the second focused wiring structure 206 at the opening 228, and is electrically coupled to the conductive via 218 and the second metal trace 220. Processes and materials similar to those previously described with respect to FIGS. 2G to 5B can be used, including the formation of bonding pads 528, solder joints 530, and underfill material 532. In addition, the connector 226 may be formed in the opening 224.

In Figure 5E, the second component 502 (including the second focused wiring structure 206 and the second integrated circuit chip 50) is attached to the first component 501, and the second carrier substrate 202 is similar to the previous figure 4A to The process and material removal illustrated in Figure 4C. As previously described with respect to the package 400, the package 504 has a width W ₁ of the first wiring structure 106 that is greater than the width W _{2 of the} second wiring structure 206, and an encapsulant 310 can be formed to surround the second wiring structure 206 The side edges are similar to those shown in Figures 4B to 4H. As shown, the second component 502 is attached so that the back sides of the first integrated circuit chip 50 and the second integrated circuit chip 50 face each other. Either or both of the first and second integrated circuit chips 50 can have a dielectric layer 510 along the backside, which can then be directly inserted between the first and second integrated circuit chips 50.

Please continue to refer to FIG. 5E, the dielectric layer 510 can be similar to the adhesive layer 70 and can be applied in a similar manner. The first and second integrated circuit chips 50 can be arranged vertically, so that at least a part of the second integrated circuit chip 50 is directly above at least a part of the first integrated circuit chip. The first and second integrated circuit chips 50 may be located at the center of each other, or may be arranged asymmetrically.

The package 504 can then be completed, as shown in Figures 5F to 5H, and can be in a similar manner as described above, for example with respect to Figures 4D to 4H. As shown in FIG. 5G, the third integrated circuit chip 50 can be attached to the first focused wiring structure 106 by a process and materials similar to those previously described with respect to FIGS. 2G, 5B, and 5D. As shown in FIG. 5H, the fourth integrated circuit chip 50 and the additional device 550 can be attached to the second focused wiring structure 206 using processes and materials similar to those previously described in FIGS. 2G, 4H, 5B, and 5D. The advantages of the foregoing arrangement include providing a smaller package 504 in the horizontal direction and/or providing more space along the first focused wiring structure 106 for attaching additional devices.

As mentioned above, the first wiring structure 106 and the second wiring structure 206 are separated by a thickness T ₃ . In this embodiment, the thickness T ₃ may be about 60 micrometers to about 500 micrometers. The ratio of the thickness T _{3 to the} thickness T ₁ may be about 0.5 to about 25. The ratio of the thickness T _{3 to the} thickness T ₂ may be about 0.4 to about 25. In addition, the connector 226 may have a height H _{C of} about 10 micrometers to about 300 micrometers, or about 150 micrometers. Therefore, the total height of the through hole 126 and the connector 226 in the package 504 can be about 50 microns to about 500 microns, or about 250 microns (it should be noted that the total height can be less than the sum of the height H _C and the height H _TV Because the connector 226 is reflowed, the total height can be approximately equal to the thickness T ₃ of the region between the first focused wiring structure 106 and the second focused wiring structure 206. As shown in FIG. 5H, the total height of the first integrated circuit chip 50 and the second integrated circuit chip (height H _IC1 and height H _{IC2 respectively} , plus the thickness of the dielectric layer 510) may be approximately equal to the thickness T ₃ .

FIGS. 6A to 6H are cross-sectional views showing intermediate steps of forming the package body 604 according to some embodiments. Specifically, the drawings depict some intermediate steps of forming the first element 601 and attaching the second element 602 to the first element 601 (and additional steps) to form the package 604.

In FIG. 6A, the first focused wiring structure 106 of the first element 601 is provided, and the through hole 126 and the bonding pad 128 are formed on the first focused wiring structure 106. Processes and materials similar to those previously described with respect to Figures 2A to 2F and Figure 5A can be used. In FIG. 6B, the first integrated circuit chip 50 is attached together with one or more other semiconductor devices 650. Processes and materials similar to those previously described with respect to Figures 2G and 5B can be used. FIG. 6B depicts the integrated circuit chip 50 having a lower height than the through hole 126. This is to accommodate the second component 602, which will include another integrated circuit chip 50. For example, the through hole 126 may have a height H _{TV of} about 10 μm to about 300 μm, and the integrated circuit chip 50 may have a height H _{IC1 of} about 30 μm to about 300 μm. The ratio of the height H _{TV to the} height H _IC1 may be about 0.03 to about 10.

In FIG. 6C, the second focused wiring structure 206 of the second element 602 is provided, and the solder resist material 222 can be formed and patterned to form an opening 228 in addition to the opening 224. Processes and materials similar to those previously described with respect to FIGS. 3A to 3H and 5C can be used. Some or all of the openings 228 may expose portions of the conductive via 218 and the second metal trace 220. The opening 228 and the opening 224 may be formed at the same time or at different time points using the same or different patterning methods.

In FIG. 6D, a second integrated circuit chip 50 can be attached to the second focused wiring structure 206 at the opening 228, and is electrically coupled to the conductive via 218 and the second metal trace 220. Processes and materials similar to those previously described in FIGS. 2G, 5B, 5D, and 6B can be used, including the formation of bonding pads 628, solder joints 630, and underfill material 632.

In Figure 6E, the second component 602 (including the second focused wiring structure 206 and the second integrated circuit chip 50) is attached to the first component 601, and the second carrier substrate 202 is similar to the previous figures 4A to Figure 4C and Figure 5E illustrate the process and material removal. As previously described with respect to the packages 400 and 504, the package 604 has a width W ₁ of the first wiring structure 106 that is greater than the width W _{2 of the} second wiring structure 206, and an encapsulant 310 can be formed to surround the second wiring structure. The side edges of the structure 206 are similar to those shown in FIGS. 4B to 4H. As shown, the second component 602 is attached so that the second integrated circuit die 50 is laterally displaced from the first integrated circuit die 50. This lateral displacement allows the backside surface of the second integrated circuit chip 50 to be lower than the backside surface of the first integrated circuit chip 50, although the backside surface may be at the same level or on the backside of the second integrated circuit chip 50 The side surface may be higher than the backside surface of the first integrated circuit chip 50.

The package 604 can then be completed, as shown in FIGS. 6F to 6H, and in a similar manner as described above, for example with respect to FIGS. 4D to 4H and FIGS. 5F to 5H. As shown in FIG. 6G, the third integrated circuit chip 50 can be attached to the first focused wiring structure 106 by a process and materials similar to those previously described in FIGS. 2G, 5B, 5D, 6B, and 6D. In addition, the external connector 610 may be formed to provide components for subsequent attachment of other integrated circuit devices or packages. As shown in Fig. 6H, the fourth integrated circuit chip 50 and the additional device 650 can be attached to them using processes and materials similar to those previously described with respect to Figs. 2G, 4H, 5B, 5D, 5G, 5H, 6B, and 6D. The second emphasis is on the wiring structure 206. The advantages of the foregoing arrangement include providing a thinner package 604.

As mentioned above, the first wiring structure 106 and the second wiring structure 206 are separated by a thickness T ₃ . In this embodiment, the thickness T ₃ may be about 50 micrometers to about 500 micrometers. The ratio of the thickness T _{3 to the} thickness T ₁ may be about 0.4 to about 25. The ratio of the thickness T _{3 to the} thickness T ₂ may be about 0.0. to about 10. In addition, the connector 226 may have a height H _{C of} about 10 micrometers to about 300 micrometers, or about 150 micrometers. Therefore, the total height of the through hole 126 and the connector 226 in the package body 604 can be about 100 microns to about 600 microns, or about 300 microns (it should be noted that the total height can be less than the sum of the height H _C and the height H _TV Because the connector 226 is reflowed, the total height can be approximately equal to the thickness T ₃ of the region between the first focused wiring structure 106 and the second focused wiring structure 206. As shown in FIG. 6H again, the thickness T _{3 is} smaller than the total stack height of the first integrated circuit chip 50 and the second integrated circuit chip (height H _IC1 and height H _{IC2, respectively).} In other words, the lateral displacement of the first and second integrated circuit wafers 50 relative to each other allows a lower thickness T ₃ . In some embodiments, the thickness of the encapsulant 310 between the first focused wiring structure 106 and the backside surface of the second integrated circuit chip 50 may be about 30 μm to about 300 μm, for example, about 150 μm. In addition, the thickness of the encapsulant 310 between the second focused wiring structure 206 and the first integrated circuit chip 50 may be about 30 micrometers to about 300 micrometers, for example, 150 micrometers.

The embodiments can achieve many advantages for a system-in-package (SiP) structure used for integrated circuits. For example, the double-sided wiring (such as the second side and the first focused wiring structure) allows each side of the wiring to be thinner, and allows the overall semiconductor package to be thinner while reducing the overall package warpage. In addition, the carrier type substrate used in one of the wiring structures provides better structural support, which also reduces the overall package warpage. Furthermore, the design method described provides a variety of wiring for embedded integrated circuit chips and other devices. Of course, the vertically stacked integrated circuit chips can provide enough space for additional devices to attach to the first-focused wiring structure, while the laterally displaced integrated circuit chips can allow an overall thinner package structure. It should be noted that the first wiring-focused structure may be wider than the wiring-focused second structure, which allows the formation of an encapsulant to surround the second-focused wiring structure to strengthen the package and reduce the overall package warpage. Of course, the described design method provides that the encapsulant is applied in a manner that does not risk spreading along the outer surface of the second-focused wiring structure. This can ensure that additional devices can be attached to the outer surface of the second-focused wiring structure without being disturbed by trace amounts of packaging glue.

In one embodiment, a semiconductor package is manufactured by attaching a first device to a second device. The first component is assembled by forming a first rewiring structure on a substrate. A through hole is then formed on the first redistribution structure, and a chip is attached to the first redistribution structure with the active side facing down. The second component includes a second rewiring structure, which is then attached to the through hole. A molding material is deposited between the first redistribution structure and the second redistribution structure, and further surrounds the side of the second element.

In another embodiment, a semiconductor package is manufactured by forming a first element, forming a second package element, and attaching the second element to the first element. The first element is formed by forming a rewiring structure on a substrate, forming a through hole on the rewiring structure, and attaching a chip to the rewiring structure. The second element is formed by forming another redistribution structure on another substrate, forming a connector on the redistribution structure, and attaching another chip to the redistribution structure. The second component is attached by turning it over on the through hole and using a reflow connector to join the connector to the through hole. After attaching, the substrate is removed from the second element.

In another embodiment, a semiconductor package includes a first redistribution structure on a substrate, and a second redistribution structure stacked on top of the first redistribution structure. The second rewiring structure includes a conductive via. The first rewiring structure is wider than the second rewiring structure. A through hole electrically couples the first redistribution structure to the second redistribution structure. A chip is attached to the first redistribution structure, and the active side of the chip is facing and electrically coupled to the first redistribution structure. Another chip is attached to the second redistribution structure, and the active side of the chip is facing and electrically coupled to the second redistribution structure. An encapsulant is filled in the area between the first redistribution structure and the second redistribution structure.

An embodiment of the present invention provides a method for forming a semiconductor package, including forming a first element, and forming the first element includes: forming a first redistribution structure on a first substrate; A through hole is formed thereon; a first chip is attached to the first redistribution structure, and the active side of the first chip is facing and electrically coupled to the first redistribution structure. The method of forming the semiconductor package further includes attaching a second element to the through hole, the second element including a second rewiring structure attached to a second substrate, and after attaching the second element, the first A molding material is deposited between the redistribution structure and the second redistribution structure, and a part of the molding material surrounds the side edge of the second redistribution structure.

In some embodiments, the method for forming the semiconductor package further includes forming a second redistribution structure on the second substrate, attaching a second chip to the second redistribution structure, and the active side of the second chip is facing and electrically connected. It is sexually coupled to the second redistribution structure, and a solder ball is deposited on the second redistribution structure. In some embodiments, the step of attaching the second component includes reflowing solder balls to electrically couple the through hole to the second rewiring structure. In some embodiments, the step of attaching the second component includes attaching the second component such that the second wafer is directly on the first wafer, and the back side of the first wafer faces the back side of the second wafer. In some embodiments, the step of attaching the second component includes attaching the second component such that the second wafer is laterally displaced from the first wafer, and the side of the first wafer faces the side of the second wafer. In some embodiments, the step of forming the second rewiring structure includes forming a first metal trace on the first substrate, depositing an ABF film (Ajinomoto Build-up Film) on the first metal trace, and An opening is drilled in the ABF film by the laser, a conductive via is formed in the opening, and a second metal trace is formed on the conductive via. In some embodiments, the method for forming the semiconductor package further includes removing the second substrate, and after removing the second substrate, attaching a plurality of passive devices to the second rewiring structure.

The embodiment of the present invention also provides a semiconductor package, which includes a first element, a second element, and an encapsulant. The first component includes a first rewiring structure, a through hole, and a first chip. The through hole is provided on the first rewiring structure. The first chip is attached to the first redistribution structure, and the active side surface of the first chip faces the first redistribution structure. The second component includes a second rewiring structure, a connector, and a second chip. The connector couples the through hole to the second redistribution structure. The second chip is attached to a first side of the second redistribution structure, and the active side surface of the second chip faces the second redistribution structure. The packaging glue is arranged between the first rewiring structure and the second rewiring structure.

In some embodiments, the encapsulant encapsulates the side edges of the first chip and the second chip. In some embodiments, the encapsulant contacts the side edge of the second redistribution structure. In some embodiments, the semiconductor package further includes a passivation layer and a third wafer. The passivation layer is disposed on a second side of the second rewiring structure, and the second side is opposite to the first side. The third wafer is disposed on the passivation layer on the second side of the second rewiring structure. In some embodiments, from a plan view, a portion of the second wafer overlaps a portion of the first wafer. In some embodiments, the second wafer is displaced laterally from the first wafer. In some embodiments, the semiconductor package further includes a passive device attached to the second side of the second rewiring structure.

The embodiment of the present invention further provides a semiconductor package, including a first rewiring structure, a second rewiring structure, a first chip, a second chip, a packaging compound, and a through hole. The first rewiring structure has a first width. The second rewiring structure is disposed on the first rewiring structure and includes a conductive via extending from a first metal trace to a second metal trace. The first metal trace is disposed along a first side of the second rewiring structure, and the second metal trace is disposed along a second side of the second rewiring structure. The second rewiring structure has a second width, and the first width is greater than the second width. The first chip is attached to the first redistribution structure, and a first active side of the first chip is facing and electrically coupled to the first redistribution structure. The second chip is attached to the second redistribution structure, and a second active side of the second chip faces and is electrically coupled to the second redistribution structure. The packaging glue is directly inserted between the first rewiring structure and the second rewiring structure. The through hole extends through the packaging glue, and the through hole electrically couples the first redistribution structure to the second redistribution structure.

In some embodiments, the encapsulant contacts the entire side edge of the first chip, the entire side edge of the second chip, and at least a part of the side edge of the second rewiring structure. In some embodiments, the first rewiring structure is a fan-out rewiring structure. In some embodiments, the conductive via is directly disposed on the through hole and electrically coupled to the through hole. In some embodiments, the first chip includes a first back side opposite to the first active side, and the second chip includes a second back side opposite to the second active side, and the second back side is greater than the first back side. Closer to the first rewiring structure. In some embodiments, the semiconductor package further includes a passive device attached and electrically coupled to the side of the second redistribution structure opposite to the first redistribution structure.

The above briefly describes the features of the several embodiments of the present disclosure, so that those with ordinary knowledge in the relevant technical field can more clearly understand the various aspects of the present disclosure. Anyone with ordinary knowledge in the relevant technical field should understand that the present disclosure can be used as a basis for design or modification of other structures or processes to perform the same purpose and/or obtain the same advantages as the embodiments of the present disclosure. Anyone with ordinary knowledge in the relevant technical field can also understand that the structure or process equivalent to the above-mentioned structure or process does not depart from the spirit and protection scope of this disclosure, and can be changed or substituted without departing from the spirit and scope of this disclosure. And retouch.

50: Integrated circuit chip/first integrated circuit chip/second integrated circuit chip/third integrated circuit chip/fourth integrated circuit chip 52: semiconductor substrate 54: device 56: interlayer dielectric 58: conductive Plug 60: Interconnect structure 62: Pad 64: Passivation film 66: Chip connector 68: Dielectric layer 70: Adhesive layer 100: First element/first package element 102: First carrier substrate 104: Release layer 106 : First-focused wiring structure/back-focused wiring structure 110: Dielectric layer 112: Metallization pattern 114: Dielectric layer 116: Metallization pattern 118: Dielectric layer 120: Metallization pattern 122: Dielectric layer 124: Opening 126 : Through hole 128: Bonding pad 130: Solder joint 132: Underfill material 200: Second component/Second package component/Packaging component 202: Second carrier substrate 204: First metal film/Metal film 206: Second focus on wiring Structure 208: photoresist 210: first metal trace 212: dielectric layer 214: via opening 216: circuit opening 218: conductive via 220: second metal trace 222: solder mask material 224: opening 226: connector 228: Opening 310: Encapsulation glue 320: Passivation layer 400: Package body 401: Illustration 402: Illustration 404: Scribe area 406: Temporary substrate 410: Conductive connector 501: First element 502: Second element 503: Substrate 504: Package 510: Dielectric layer 511: Additional device 528: Bonding pad 530: Solder joint 532: Underfill material 550: Other semiconductor device/other device/additional device 601: First component 602: Second component 604: Package Body 610: External connector 628: Bonding pad 630: Solder joint 632: Underfill material 650: Other semiconductor devices/extra devices H _C : Connector height H _IC1 : Integrated circuit chip/first integrated circuit chip the height H _IC2: H _TV height of the second integrated circuit wafer: a through-hole height T _1: thickness of the first wiring structure of the focus T _2: thickness of the second wiring structure focused T _3: the first focus and the second wiring structure between two focuses wiring structure thickness W _1: width W ₂ of the first wiring structure focused: a second focus width θ wiring structure: angle

Figure 1 shows a cross-sectional view of an integrated circuit chip according to some embodiments. 2A to 2G are cross-sectional views showing intermediate steps during the process of forming a packaged device according to some embodiments. 3A to 3H are cross-sectional views showing intermediate steps during the process of forming a packaged device according to some embodiments. 4A to 4H are cross-sectional views showing intermediate steps during the process of forming a packaged device according to some embodiments. 5A to 5H are cross-sectional views showing intermediate steps during the process of forming a packaged device according to some embodiments. FIGS. 6A to 6H are cross-sectional views showing intermediate steps during the process of forming a package component according to some embodiments.

50: Integrated circuit chip/first integrated circuit chip/second integrated circuit chip/third integrated circuit chip/fourth Integrated circuit chip

100: The first component / the first package component

106: First focus on wiring structure / back focus on wiring structure

200: second component/second package component/package component

202: second carrier substrate

206: The second focus on wiring structure

310: Encapsulation glue

400: Package body

401: illustration

402: illustration

T ₁ : The first focus is on the thickness of the wiring structure

T ₂ : The second focus is on the thickness of the wiring structure

T ₃ : The thickness between the first-focused wiring structure and the second-focused wiring structure

θ: Angle

Claims (10)

A method for forming a semiconductor package, the method comprising: forming a first element, and forming the first element includes: forming a first redistribution structure on a first substrate; on the first redistribution structure Forming a through hole; attaching a first chip to the first redistribution structure, the active side of the first chip is facing and electrically coupled to the first redistribution structure; attaching a second component to the through Hole, the second element includes a second redistribution structure attached to a second substrate; and after attaching the second element, a deposit is deposited between the first redistribution structure and the second redistribution structure A molding material, a part of the molding material surrounds the side edge of the second redistribution structure, wherein a part of the side edge of the second redistribution structure is exposed from the molding material. Such as the forming method of claim 1, further comprising: forming the second redistribution structure on the second substrate; attaching a second chip to the second redistribution structure, the active side of the second chip facing and Electrically coupled to the second rewiring structure; and depositing a solder ball on the second rewiring structure. Such as the forming method of claim 2, wherein the step of attaching the second element includes attaching the second element so that the second chip is directly on the first chip, and the back side of the first chip faces the first chip. The back side of the second chip. The forming method of claim 2, wherein the step of attaching the second element includes attaching the second element so that the second chip is laterally displaced from the first chip, and the side of the first chip faces the The side of the second wafer. A semiconductor package includes: a first element, including: a first redistribution structure; a through hole arranged on the first redistribution structure; and a first chip attached to the first redistribution Structure, the active side of the first chip faces the first redistribution structure; a second element includes: a second redistribution structure; a connector for coupling the through hole to the second redistribution structure And a second chip attached to a first side of the second redistribution structure, the active side of the second chip facing the second redistribution structure; and a encapsulant disposed on the first redistribution structure And the second redistribution structure, wherein a part of the encapsulation glue surrounds the side edge of the second redistribution structure, and a part of the side edge of the second redistribution structure is exposed from the encapsulation glue. For example, the semiconductor package of claim 5, further comprising: a passivation layer disposed on a second side of the second rewiring structure, the second side being opposite to the first side; and a third chip disposed On the passivation layer on the second side of the second rewiring structure. For example, the semiconductor package of claim 5 further includes a passive device attached to a second side of the second rewiring structure, the second side being opposite to the first side. A semiconductor package includes: A first rewiring structure, the first rewiring structure has a first width; a second rewiring structure is disposed on the first rewiring structure, the second rewiring structure includes a first metal The wire extends to a conductive via of a second metal trace, the first metal trace is disposed along a first side of the second redistribution structure, and the second metal trace is along the second redistribution structure Is arranged on a second side of the second rewiring structure, the second rewiring structure has a second width, and the first width is greater than the second width; a first chip attached to the first rewiring structure, a portion of the first chip The first active side is oriented and electrically coupled to the first rewiring structure; a second chip is attached to the second rewiring structure, and a second active side of the second chip is oriented and electrically coupled to the first rewiring structure. A double wiring structure; an encapsulation glue directly inserted between the first rewiring structure and the second rewiring structure; and a through hole extending through the encapsulation glue, the through hole electrically connecting the first rewiring structure It is sexually coupled to the second redistribution structure, wherein a part of the encapsulant surrounds the side edge of the second redistribution structure, and a part of the side edge of the second redistribution structure is exposed from the encapsulant. The semiconductor package of claim 8, wherein the encapsulant contacts the entire side edge of the first chip, the entire side edge of the second chip, and at least a part of the side edge of the second rewiring structure . The semiconductor package of claim 8, wherein the first chip includes a first back side opposite to the first active side, wherein the second chip includes a second back side opposite to the second active side, and The second backside is closer to the first redistribution structure than the first backside.

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