RU2313128C1 - Information finding device - Google Patents

Abstract

FIELD: electric communications, possible use for finding and operative identification of information in data transfer networks with packet commutation.

SUBSTANCE: device consists of N, where N≥2, selection blocks, search strategy register, time interval generator, indication block, frequency divider, N mask storage blocks, transition mask address generation block. Device ensures possible identification of packets by means of parallel analysis of identification signs. Independency of device functioning process from standard values of identification signs and content of rules which determine order of packet exchange ensures higher speed of analysis and allows to expand the area of possible usage for the device.

EFFECT: development of information finding device, which ensures area of its usage and increases speed of operation due to identification of packets by means of parallel analysis of values of identification signs and control of sign exchange sequence to determine compliance with any, a priori defined rules.

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Description

The invention relates to the field of telecommunications and can be used for searching and online identification of information in packet-switched data networks.

Known information retrieval devices - see, for example, Aut. St. USSR No. 1621049 "Information Search Device", IPC G06F 15/40, declared 09.01.89, Auth. USSR No. 1711185 "Information Search Device", IPC G06F 15/40, claimed 05.04.89.

Known analogues contain boundary registers, summing and subtracting counters, comparison circuits, memory blocks, calculation blocks and a number of other elements that allow you to search for information. When receiving a digital message and searching for a specific digital sequence in it, it is necessary to determine its parameters and the correspondence of the transmission sequence to the data exchange rules established for this protocol. Known analogues do not fully comply with these requirements.

In the first analogue, the definition of network packets is implemented with a probability of correct recognition of less than 0.1, since recognition is performed in a statistical way and does not take into account the signs of sequential transmission of information.

In the second analogue, the disadvantage is the impossibility of obtaining an unambiguous solution due to the low level of reliability and probability of identification of the communication protocol (less than 0.3), since the search for information blocks is implemented by the dichotomous method without taking into account the presence of an acceptable sequence of packets.

Of the known closest analogue (prototype) in its technical essence to the claimed device is a device according to RF Patent No. 2115952 "Information Search Device", IPC G06F 17/40 published July 20, 1998.

The prototype device includes a memory unit, a search strategy register and a subtracting counter, a frequency divider, a switch, first, second, third and fourth selection units, a time interval former and an indication unit.

Moreover, in the prototype device, the output of the frequency divider is connected to the first inputs of the memory block, subtracting the counter, the first, second, third and fourth blocks of selection, the search strategy register. The outputs of the memory block are connected respectively to the fourth to eleventh inputs of the switch, and the first output of the subtracting counter is connected to the tenth input of the memory block, the twelfth input of the switch, the eleventh input of the first selection block, the tenth inputs of the second, third, and fourth selection blocks, the third input of the search strategy register and is the command output of the device. The second output of the subtracting counter is connected to the eleventh inputs of the second, third and fourth selection blocks, and the third output of the subtracting counter is connected to the twelfth input of the first selection block. The outputs of the switch are connected to the second to ninth inputs of the first, second, third and fourth selection blocks, respectively, and the first and second outputs of the first selection block are connected respectively to the first and second inputs of the switch. The third output of the first selection block is connected to the fourth input of the search strategy register and the fourteenth input of the subtracting counter, and the fourth output of the first selection block is connected to the fifth input of the search strategy register, the fourteenth input of the subtracting counter and the input of the time interval shaper. The fifth output of the first selection block is connected to the third input of the switch. The sixth output of the first selection block and the first outputs of the second, third and fourth selection blocks, the output of the search strategy register are connected to the first input of the display unit, the tenth input of the first selection block and the fourteenth input of the subtracting counter. The second output of the second selection block is connected to the second input of the search strategy register, and the second output of the third selection block is connected to the third input of the search strategy register. In this case, the second output of the fourth selection block and the output of the shaper of the time intervals are connected to the second input of the display unit and the fourteenth input of the subtracting counter. The input of the frequency divider, the second to ninth inputs of the memory unit and the second to thirteenth inputs of the subtracting counter are, respectively, the input of the clock frequency, signal and information inputs of the device.

Such a scheme, in comparison with analog devices, makes it possible to make an unambiguous decision on the presence in the data stream of elements of the TFTP application layer protocol (Trivial File Transfer Protocol) due to the syntactic recognition of this protocol based on the operation of identifying packets transmitted through the channel and the rules for exchanging them in communication session.

However, this device has a number of significant disadvantages:

1. The relatively large time required to identify the packages, as the identification is carried out by sequential analysis of the values of the characteristics. This limits the use of the prototype device for protocol analysis in modern high-speed computer networks.

2. A narrow scope, namely, only for the analysis of the TFTP protocol for compliance of the observed sequence of packets with the rules established for this protocol.

The purpose of the claimed technical solution is to develop an information retrieval device that expands its scope and improves performance by identifying packets by parallel analysis of the values of identification signs and monitoring the sequence of their exchange for compliance with any a priori specified rules.

The goal in the claimed information retrieval device is achieved by the fact that in the known information retrieval device containing N≥2 selection blocks, a search strategy register, a time interval shaper, an indication unit, a frequency divider, the clock input of which is the first clock input of the device, the outputs "Result comparing "selection blocks are connected to the corresponding inputs" Comparison result "of the search strategy register, N mask storage blocks and a transition mask address generating unit are additionally introduced.

Moreover, in the claimed device is K-bit, where K = (log ₂ N) +1, the "Event code" output of the transition mask address generation unit is connected to the K-bit "Event code" inputs of the search strategy register and display unit. The recording permission inputs of all mask storage units are interconnected and are the recording permission input of the device. The corresponding bits of the L-bit information inputs, where L≥2, of the selection blocks are combined and are the corresponding bits of the L-bit information input of the device. The first L-bit inputs "Mask 1" and "Mask 2" of the j-th mask storage block, where j = 1, 2, ..., N, are the j-th first L-bit inputs, respectively, "Mask 1" and " Mask 2 "device. The second L-bit outputs "Mask 1" and "Mask 2" of the j-th mask storage unit are connected to the corresponding second L-bit outputs "Mask 1" and "Mask 2" of the j-th selection block. The outputs "Comparison Result" of the selection blocks are connected to the corresponding inputs "Comparison Result" of the block forming the address of the transition mask. The output of the frequency divider is connected to the clock input of the shaper time intervals. The “Initial reset” input of the time interval generator is connected to the “Initial reset” input of the transition mask address generating unit and is the “Initial reset” input of the device. In this case, the M-bit input "Time-out code" of the time slot generator, where M≥2 is the bit depth of the time-out code, is the M-bit input "Time-out code" of the device, and the output of the time interval generator is connected to the "Reset" input of the forming unit transition mask addresses. The signal output of the search strategy register is connected to the signal inputs of the time slot generator and the transition mask address generation unit. The K-bit address input, the control input, the N-bit information input, and the search register enable input are the K-bit address input, the control input, the N-bit information input, and the device enable input. The “Choice of crystal” and “Read / write” inputs of the search strategy register are respectively the “Choice of crystal" and "Read / write" inputs of the device. The N-bit input "Search completion rule" and the output "Search result" of the display unit are respectively the N-bit input "Search completion rule" and the output "Search result" of the device.

The mask storage unit consists of the first and second registers. The information outputs of the first register are the corresponding bits of the second L-bit output of Mask 1 of the mask storage unit, and the information outputs of the second register are the corresponding bits of the second L-bit output of Mask 1 of the mask storage unit. The recording permission inputs of the first and second registers are interconnected and are the recording permission input of the mask storage unit. The information inputs of the first register are the corresponding bits of the first L-bit input "Mask 1" of the mask storage unit, and the information inputs of the second register are the corresponding bits of the first L-bit input "Mask 1" of the mask storage unit.

The selection block consists of the first and second groups of two-input elements AND L elements in each group, a comparator, an inverter, the inverse output of which is the output "Comparison result" of the selection block. The inverter input is connected to the comparator equality output. In this case, the i-th, where i = 1, 2, ..., L, the input of the first group of information inputs of the comparator is connected to the output of the i-th two-input element And the first group of two-input elements And, and the i-th input of the second group of information inputs of the comparator connected to the output of the i-th two-input element And the second group of two-input elements I. The first input of the i-th two-input element And the first group of two-input elements And is the i-th bit of the L-bit information input of the selection block. The second input of the i-th two-input element And the first group of two-input elements And is connected to the first input of the i-th two-input element And the second group of two-input elements And is the i-th bit of the second L-bit input "Mask 1" of the selection block. The second input of the i-th two-input element And the second group of two-input elements And is the i-th bit of the second L-bit input "Mask 2" of the selection block.

The time interval shaper consists of a first two-input element OR, a JK-trigger, a first two-input element AND, an inverter, a second two-input element AND, a second two-input element OR, a counter. The counter overflow output is connected to the second inputs of the second two-input AND element and the first two-input OR element. The first input of the first two-input OR element is connected to the first input of the second two-input OR element and is the input "Initial reset" of the shaper time intervals. The output of the first two-input OR element is connected to the second information input of the JK trigger, the first information input of which is connected to the counter recording enable input and is the signal input of the time slot former. In this case, the e-th, where e = 1, 2, ..., M, the information input of the counter is the e-th bit of the M-bit input "Code timeout" of the shaper time intervals. The counter reset input is connected to the output of the second two-input OR element. The counter input of the counter is connected to the output of the first two-input element And, the first input of which is the second clock input of the shaper time intervals. The output of the JK trigger is connected to the second input of the first two-input element And and the input of the inverter, the output of which is connected to the first input of the second two-input element I. The output of the second two-input element And is connected to the second input of the second two-input element OR and is the "Reset" output of the time interval shaper.

The search strategy register consists of a multiplexer selector, random access memory, N three-input OR-NOT elements, an N-input OR element. The output of the N-input OR element is the signal output of the search strategy register. In this case, the j-th input of the N-input OR element is connected to the inverse output of the j-th three-input OR-NOT element. The first input of the j-th three-input element OR NOT is the j-th input "Result of comparison" of the search strategy register. The second input of the j-th three-input OR-NOT element is connected to the j-th information output of the random access memory, and the third inputs of all three-input OR-NOT elements are interconnected and are an enable input of the search strategy register. In this case, the rth, where r = 1, 2, ..., K, the address input of the random access memory is connected to the rth output of the multiplexer selector, and the jth information input of the random access memory is the jth bit N- bit information input register search strategy. Inverse inputs "Choice of crystal" and "Read / write" of random access memory are respectively the inputs "Choice of crystal" and "Read / write" register search strategy. In this case, the rth input of the first group of information inputs of the multiplexer selector is the rth bit of the K-bit input "Event code" of the search strategy register, and the rth input of the second group of information inputs of the selector of the multiplexer is the rth bit of the K-bit address input search strategy register. The control input of the multiplexer selector is the control input of the search strategy register.

The transition mask address generating unit consists of an encoder, K inverters, a two-input OR element, a register whose rth information output is the rth digit of the K-bit output "Event code" of the transition mask address generating unit. In this case, the rth information input of the register is connected to the inverse output of the rth inverter. The register write enable input is the signal input of the transition mask address generation unit. The register reset input is connected to the output of a two-input OR element. The first and second input of the two-input OR element are respectively the "Reset" input and the "Initial reset" input of the transition mask address generation unit. The input of the r-th inverter is connected to the r-th inverse output of the encoder, the j-th inverse input of which is the j-th input "Comparison result" of the transition vector address generation unit.

The display unit consists of a decoder, N two-input OR elements, an N-input AND element, the output of which is the "Search Result" output of the display unit. In this case, the j-th input of the N-input element AND is connected to the output of the j-th two-input element OR. The first input of the j-th two-input OR element is connected to the j-th inverse output of the decoder, and the second input of the j-th two-input OR element is the j-th bit of the N-bit input "Search termination rule" of the display unit. The r-th input of the decoder is the r-th bit of the K-bit address input "Event code" of the display unit.

Thanks to a new set of essential features and the introduction of N mask storage units and a transition mask address generating unit, the device provides the possibility of identifying packets by parallel analysis of identification signs and the independence of the functioning of the device from the reference values of identification signs and the content of the rules that determine the order of packet exchange, which higher speed of analysis, provides an extension of the scope of the device.

The analysis of the prior art by the applicant made it possible to establish that there are no analogues that are characterized by sets of features identical to all the features of the claimed information retrieval device. Therefore, the claimed invention meets the condition of patentability "Novelty."

Search results for known solutions in this and related fields of technology in order to identify features that match the distinctive features of the claimed invention from the prototype have shown that they do not follow explicitly from the prior art. From the prior art determined by the applicant, the influence of the provided by the essential features of the claimed invention on the achievement of the specified technical result is not known. Therefore, the claimed invention meets the condition of patentability "Inventive step".

The claimed objects of the invention are illustrated by drawings, in which

figure 1 - device information retrieval;

figure 2 - register storage mask;

figure 3 - block selection;

figure 4 - shaper time intervals;

figure 5 - register search strategy;

figure 6 - block forming the address of the transition vector;

in Fig.7 - display unit;

on Fig - an example of a search script;

Fig. 9 is an example of filling transition masks, script start masks and script end masks.

The device (see Fig. 1) consists of N, where N≥2, selection blocks 2 ₁ -2 _N , search strategy register 5, time interval shaper 4, display unit 7, frequency divider 3, N mask storage blocks 1 ₁ - 1 _N , block forming the address of the transition mask 6.

The elements are interconnected as follows (see figure 1). K-bit, where K = (log ₂ N) +1, the “Event Code” output 21 of which is connected to the K-bit “Event Code” inputs 21 of the search strategy register 5 and display unit 7. Recording permission inputs 10 of all mask storage units interconnected and are the input of the recording permission 10 of the device. The corresponding bits of the L-bit information inputs 11, where L≥2, of the selection blocks 2 ₁ -2 _{N are} combined and are the corresponding bits of the L-bit information input of the device. The first L-bit inputs are Mask 1 12 ₁ -12 _N and Mask 2 13 ₁ -13 _{N of the} j-th mask storage unit 1 ₁ -1 _N , where j = 1, 2, ..., N are j the first L-bit inputs, respectively, "Mask 1" and "Mask 2" of the device. The second L-bit outputs of Mask 1 14 ₁ -14 _N and Mask 2 15 ₁ -15 _{N of the} j-th mask storage unit 1 ₁ -1 _{N are} connected to the corresponding second L-bit inputs of Mask 1 and Mask 2 "j-th block of selection 2 ₁ -2 _N. The outputs "Comparison Result" 16 ₁ -16 _N selection blocks 2 ₁ -2 _{N are} connected to the corresponding inputs "Comparison Result" of the search strategy register 5 and the block for generating the transition mask address 6. The clock input of the frequency divider 3 is the first clock input 8 of the device, and its output is connected to the clock input 9 of the time interval shaper 4. The “Initial reset” input 18 of the time interval shaper is connected to the “Initial reset” input 18 of the transition mask address generating unit 6 and is the “Initial reset” input of the device. In this case, the M-bit input "Time-out code" 19 of the time slot generator 4, where M≥2 is the bit depth of the time-out code is the M-bit input "Time-out code" 19 of the device, and the output of the time-gap generator 4 is connected to the "Reset" input "20 of the transition mask address generating unit 6. The signal output 17 of the search strategy register 5 is connected to the signal inputs 17 of the time slot generator 4 and the transition mask address generating unit 6. K-bit address input 22, control input 24, N-bit information the input 23 and the enable input 29 of the search strategy register 5 are respectively the K-bit address input 22, the control input 24, the N-bit information input 23 and the enable input 29 of the device. The inputs "Crystal Select" 25 and "Read / Write" 26 of the search strategy register 5 are respectively the inputs "Crystal Select" 25 and "Read / Write" 26 of the device. The N-bit input “Search termination rule” 27 and the “Search result” output 28 of the display unit 7 are respectively the N-bit input “Search termination rule” 27 and the “Search result” output 28 of the device.

The frequency divider 8 is designed to increase the period following the pulse train arriving at its input. Implementation schemes for such a frequency divider are known. In particular, the frequency divider can be built on the counter. See, for example, P.P. Maltsev, N.S. Dolidze et al., Reference book "Digital Integrated Circuits". - M .: "Radio and Communications", 1994, p. 62-74. In this case, the input of the divider will be the counter input of the counter, and the output of the divider will be one of the outputs of the counter.

Mask storage blocks 1 ₁ -1 _N are designed to store bit masks used to identify elements of the incoming data stream. The mask storage unit can be implemented according to any known scheme taking into account the described functions. In particular, its circuit shown in FIG. 2 consists of the first 1.1 and the second 1.2 registers. The information outputs of the first register 1.1 are the corresponding bits of the second L-bit output of Mask 1 of the mask storage unit, and the information outputs of the second register 1.2 are the corresponding bits of the second L-bit output of Mask 1 of the mask storage unit. The recording permission inputs of the first 1.1 and second 1.2 registers are interconnected and are the recording permission input 10 of the mask storage unit. The information inputs of the first register 1.1 are the corresponding bits of the first L-bit input "Mask 1" of the mask storage unit, and the information inputs of the second register 1.2 are the corresponding bits of the first L-bit input "Mask 1" of the mask storage unit.

The first 1.1 and second 1.2 registers are designed to store the first and second bit masks, respectively. The description of the operation and the scheme of such registers are known and are given, for example, in the book: P.P. Maltsev, N.S. Dolidze et al., "Digital Integrated Circuits: A Reference Book". - M .: "Radio and Communications", 1994, p. 57-62.

The selection blocks 2 ₁ -2 _N are designed to identify the corresponding elements of the incoming data stream and the formation of the identification result. The selection block can be implemented according to any known scheme, taking into account the described functions. In particular, its circuit shown in Fig. 3 consists of the first and second groups of two-input elements AND 2.1 ₁ -2.1 _L , 2.2 ₁ 1-2.2 _L of L elements in each group, a comparator 2.3, an inverter 2.4, whose inverse output is an output "Comparison Result" 16 ₁ selection block. The inverter input is connected to the comparator equality output. Moreover, the i-th one, where i = 1, 2, ..., L, the input of the first group of information inputs of the comparator is connected to the output of the i-th two-input element And the first group of two-input elements AND 2.1 ₁ - 2.1 _L , and the i-th input the second group of information inputs of the comparator is connected to the output of the i-th two-input element And the second group of two-input elements And 2.2 ₁ -2.2 _L. The first input of the i-th two-input element And the first group of two-input elements And 2.1 ₁ -2.1 _L is the i-th bit of the L-bit information input 11 of the selection block. The second input of the i-th two-input element And the first group of two-input elements And 2.1 ₁ -2.1 _{L is} connected to the first input of the i-th two-input element And the second group of two-input elements And 2.2 ₁ -2.2 _L and is the i-th bit of the second L-bit input " Mask 1 "14 ₁ selection block, and the second input of the i-th two-input element And the second group of two-input elements And 2.2 ₁ -2.2 _L is the i-th bit of the second L-bit input" Mask 2 "15 ₁ selection block.

Comparator 2.3 is intended for comparing binary codes installed on its inputs and generating a comparison result. A description of the work and the comparator circuit are given, for example, in the book: V.L.Shilo "Popular TTL microcircuits." M .: "ARGUS", 1993, p.183-184.

Shaper time intervals 4 is intended to control the time interval between the elements of the incoming data stream and the formation of the signal after it. Shaper time intervals can be implemented by any known scheme, taking into account the described functions. In particular, its circuit shown in Fig. 4 consists of a first two-input element OR 4.1, a JK trigger 4.2, a first two-input element AND 4.3, an inverter 4.4, a second two-input element AND 4.5, a second two-input element OR 4.5, a counter 4.7. The counter overflow output 4.7 is connected to the second inputs of the second two-input element AND 4.5 and the first two-input element OR 4.1. The first input of the first two-input element OR 4.1 is connected to the first input of the second two-input element OR 4.6 and is the input "Initial reset" 18 of the shaper time intervals. The output of the first two-input element OR 4.1 is connected to the second information input of the JK trigger 4.2. The first information input of the JK trigger 4.2 is connected to the counter enable input and is a signal input 17 of the time slot generator. In this case, the e-th, where e = 1, 2, ..., M, the information input of the counter is the e-th bit of the M-bit input "Code timeout" 19 of the shaper time intervals. The counter reset input is connected to the output of the second two-input element OR 4.6, and the counting input of the counter is connected to the output of the first two-input element OR 4.3. The first input of the first two-input element And 4.3 is the second clock input 9 of the shaper time intervals. The output of the JK trigger is connected to the second input of the first two-input element And 4.3 and the input of the inverter 4.4, the output of which is connected to the first input of the second two-input element And 4.5. The output of the second two-input element AND 4.5 is connected to the second input of the second two-input element OR 4.6 and is the output "Reset" 20 of the shaper time intervals.

JK-trigger 4.2 is designed to store a logical value that determines the mode of operation of the shaper of time intervals, and can be built according to any known scheme. See, for example, in the book: B.V. Tarabrin, L.F. Lunin, Yu.N. Smirnov et al. "Integrated circuits: a reference book". - M .: "Energoatomizdat", 1985, p. 67.

The counter 4.7 is intended for counting the pulses arriving at its input and generating a control signal after a time interval determined by the value of the code for the initial filling of the counter and the repetition period of the clock pulses, that is, it performs the function of a custom timer. The description of the operation and the circuit of such a counter are known and are given, for example, in the book: P. P. Maltsev, N. S. Dolidze et al., "Digital Integrated Circuits: A Reference". - M .: "Radio and Communications", 1994, p. 71.

The search strategy register 5 is intended to check the correspondence of the sequence of identified elements of the incoming data stream to the given rules and the formation of a signal upon receipt of the element expected in accordance with the rules. The search strategy register can be implemented according to any known scheme taking into account the described functions. In particular, its circuit shown in Fig. 5 consists of a selector of a multiplexer 5.1, random access memory 5.2, N three-input elements OR-NOT 5.3 ₁ -5.3 _N , an N-input element OR 5.4, the output of which is a signal output 17 of the strategy register search. In this case, the j-th input of the N-input OR element 5.4 is connected to the inverse output of the j-th three-input element OR-NOT. The first input of the j-th three-input element OR NOT is the j-th input "Comparison Result" 16 of the search strategy register. The second input of the j-th three-input OR-NOT element is connected to the j-th information output of the random access memory 5.2, and the third inputs of all three-input OR-NOT elements are interconnected and are the enable input 29 of the search strategy register. Moreover, the rth, where r = 1, 2, ..., K, the address input of the random access memory 5.2 is connected to the rth output of the selector of the multiplexer 5.1, and the jth information input of the random access memory is the jth bit N -bit information input 23 register search strategy. Inverse inputs "Choice of crystal" and "Read / write" of random access memory are respectively the inputs "Choice of crystal" 25 and "Read / write" 26 of the search strategy register. In this case, the rth input of the first group of information inputs of the multiplexer selector is the rth bit of the K-bit input "Event code" 21 of the search strategy register, and the rth input of the second group of information inputs of the multiplexer selector is the rth bit of the K-bit address input 22 register search strategy. The control input of the multiplexer selector is the control input 24 of the search strategy register.

The multiplexer selector 5.1 is designed for switching one of two groups of information inputs to its outputs. Implementation schemes for such a selector-multiplexer are known. See, for example, in the book: P. P. Maltsev, N. S. Dolidze et al., “Digital Integrated Circuits: A Reference Book”. - M .: "Radio and Communications", 1994, p. 33-40.

Random access memory 5.2 is designed to store masks containing rules that determine the required sequence of identified elements of the incoming data stream. A random access memory implementation scheme is known. See, for example, in the book: VL Shiloh "Popular Digital Circuits." - M .: "Radio and Communications", 1987, p.164-166.

The transition mask address generating unit is intended for generating and storing a code corresponding to a mask defining the next element to be identified in the incoming data stream. The unit for generating the address of the transition vector can be implemented according to any known scheme taking into account the described functions. In particular, its circuit shown in FIG. 6 consists of a encoder 6.1, K inverters 6.2 ₁ -6.2 _K , a two-input element OR 6.3, register 6.4, the r-th information output of which is the r-th bit of the K-bit output "Code event "21 block formation address mask transitions. In this case, the rth information input of the register 6.4 is connected to the inverse output of the rth inverter. The register write enable input is a signal input 17 of the transition mask address generating unit. The register reset input is connected to the output of the two-input OR 6.3 element, the first and second input of which are respectively the input "Reset" 20 and the input "Initial reset" 18 of the transition mask address generating unit. The input of the r-th inverter is connected to the r-th inverse output of the encoder, the j-th inverse input of which is the j-th input "Comparison result" 16 of the transition vector address generation unit.

The encoder 6.1 is designed to generate a code corresponding to a mask defining the next element that should be identified in the incoming data stream by converting a low-level signal at one of its inputs into the corresponding binary code at its outputs. Priority scrambler implementation scheme is known. See, for example, in the book: P. P. Maltsev, N. S. Dolidze et al., “Digital Integrated Circuits: A Reference Book”. - M .: "Radio and Communications", 1994, p.40-41.

Register 6.4 is intended for storing code corresponding to a mask defining the next element to be identified in the incoming data stream. The description of the operation and the scheme of such registers are known and are given, for example, in the book: P.P. Maltsev, N.S. Dolidze et al., "Digital Integrated Circuits: A Reference Book". - M .: "Radio and Communications", 1994, p. 57-62.

The display unit is designed to detect signs indicating the completion of the sequence of elements of the incoming data stream specified by the rules and the formation of the corresponding signal. The display unit can be implemented according to any known scheme, taking into account the described functions. In particular, its circuit shown in Fig. 7 consists of a decoder 7.1, N two-input elements OR 7.2 ₁ -7.2 _N , N-input element AND 7.3, the output of which is the “Search Result” output 28 of the display unit. In this case, the j-th input of the N-input element AND is connected to the output of the j-th two-input element OR 7.2 ₁ -7.2 _N. The first input of the j-th two-input OR element is connected to the j-th inverse output of the decoder, and the second input of the j-th two-input OR element is the j-th bit of the N-bit input "Search completion rule" 27 of the display unit. The r-th input of the decoder is the r-th bit of the K-bit address input "Event code" 21 of the display unit.

Decoder 7.1 is designed to convert the binary code arriving at its input into a low-level signal at the corresponding output. Low-level decoder implementation schemes are known. See, for example, in the book: P. P. Maltsev, N. S. Dolidze et al., “Digital Integrated Circuits: A Reference Book”. - M .: "Radio and Communications", 1994, p. 41-47.

The claimed device implements a syntactic approach to pattern recognition (Gonzalez R., Tu J. Principles of pattern recognition. - M .: Mir, 1978. - 411 pp.), Based on the identification of individual elements of the incoming data stream - blocks of binary information (BDI) , by parallel analysis of the values of identification signs and control of their order for compliance with the given rules. As signs of identification, bit values are used in the corresponding BDI positions. The rules for following the BDI are set by the formal grammar - the search script.

To explain the operation of the device, it is necessary to consider the rules for specifying a search script. The SC search script can be represented by the following scheme:

- множество типов БДИ, входящих в состав сценария;Where

- many types of BDI included in the script;

- множество масок переходов;

- many transition masks;

MB - mask of the beginning of the search script;

MF - mask for ending the search script;

T - waiting time for the next BDI.

The identification of the type of BDI in the device is carried out by comparing the values of the identification bits of the BDI with their reference values. By identification bits are meant bits of the BDI, the values of which allow you to uniquely identify the type of BDI. For each type of BDI, a plurality of identification bits may be individual. In this regard, two bit masks are associated with each type of BDI:

where M1 _n is the first bit mask of the BDI n-th type;

M2 _n is the second bit mask of the NDI type NDI.

Bit masks contain L bits, where L is the maximum possible number of bits in the BDI used in the search script. The first bitmask is used to indicate the positions of the IDI identification bits. The values of the logical unit in the bits of the first bitmask correspond to the positions of the identification bits. In all other bits of the bitmask, logical zero values are set. The second bitmask is designed to set the reference values to which the values of the identification bits must correspond. In this case, the bits of the second bitmask, which are not identification, can have arbitrary values, since they do not affect the process of identifying the BDI.

A lot of transition masks are used to set the order of the BDI within the script. The set contains N transition masks, each of which contains N binary digits. Thus, each type of BDI has its own transition mask. In this case, the nth transition mask MP _n contains information about the types of NDI, which, according to the search scenario, are expected after observing an NDI NDI. The specified information is set by setting the value of logical zero in the bits of the mask transitions, the sequence numbers of which correspond to the types of expected BDI. In all other digits of the transition mask, the values of the logical unit are set.

The mask for the beginning of the search script is intended to indicate the types of the BDI that are expected first in the search script - the initial BDI. The MB mask contains N binary bits. In the bits of the mask at the beginning of the search script, the numbers of which correspond to the initial types of BDIs, logical zero values are set. In all other digits of the mask, the beginning of the search script sets the values of the logical unit.

The mask of the end of the search script is intended to indicate the types of BDI, the observation of which indicates the completion of the search script - the final BDI. The MF mask contains N binary bits. In the bits of the mask of the end of the search script, the numbers of which correspond to the final types of the BDI, the logical zero values are set. In all other bits of the mask of the end of the search script, the values of the logical unit are set.

The waiting time for the next BDI T sets the maximum allowable time interval during which the next BDI specified by the type search script is expected. In the event that during the specified time interval the expected type of the BDI is not detected, the search script is interrupted and the transition to waiting for the initial BDI is performed. The waiting time for the next BDI is set in the form of an M-bit code. In this case, the smallest waiting time corresponds to the largest code, which is an addition to the maximum number represented in the M-bit code.

, устройства соответствует множеству типов БДИ, входящих в состав сценария. При обнаружении очередного заданного сценарием типа БДИ устройство переходит в состояние, номер которого соответствует типу обнаруженного БДИ. Находясь в одном из состояний устройство ожидает появления БДИ, типы которых определяются маской переходов, номер которой соответствует номеру текущего состояния устройства.Below, the operation of the device is considered as the process of transition of the device from state to state. Many states

, the device corresponds to the many types of BDI that are part of the script. When it detects the next type of BDI specified by the script, the device goes into a state whose number corresponds to the type of detected BDI. Being in one of the states, the device expects the appearance of a BDI, the types of which are determined by the transition mask, the number of which corresponds to the number of the current state of the device.

On Fig is an example of a search script that includes N = 8 types of BDI. Corresponding to the given search scenario, filling in the transition masks, the script start mask and the script end mask is shown in Fig. 9.

Initialization of the device includes the following operations:

initial reset of the device;

installation of the first and second bit masks;

setting the mask for the beginning of the script and transition masks;

setting the mask for ending the search script;

setting the waiting time for the next BDI.

The initial reset of the device is as follows. At the enable input 29 of the device, the value of the logical unit is set, which goes to the corresponding input of the search strategy register 5. The logical unit at the enable input 29 of the search strategy register 5, arriving at the third inputs of all three-input elements OR-NOT 5.3 ₁ -5.3 _N , provides a logical zero at their outputs, regardless of the logical values set on the first and second inputs. In this regard, the signal output 17 of the register of the search strategy 5 will be set to a logical zero. Logical zero from the signal output 17 of the search strategy register 5 is fed to the corresponding input of the shaper of time intervals 4 and then to the first information input J of the JK trigger 4.2. At the input "Initial reset" 18 devices set the value of the logical unit, which is supplied to the corresponding inputs of the shaper time intervals 4 and the block forming the address of the transition vector 6. The value of the logical unit from the input "Initial reset" 18 shaper time intervals 4 through the first two-input element OR 4.1 arrives at the second information input To the JK-trigger 4.2, and through the second two-input element OR 4.6 - to the reset input R of the counter 4.7. The logical unit at the input of the JK-trigger in the presence of a logical zero at its input J leads to a logical zero at the output of the JK-trigger, which, entering the second input of the two-input element And 4.3, sets the value of the logical zero at its output, regardless of the logical values at its first entrance. The logical unit at the reset input R of the counter 4.7 provides a logical zero at its overflow output P. The logical zero value from the overflow output P of the counter 4.7 goes to the second input of the second two-input element And 4.5, which leads to an unconditional installation at its output, and, accordingly, to output "Reset" 20 shaper time intervals 4 values of logical zero. The logical unit from the input "Initial reset" of the block for generating the address of the transition mask 6 through the two-input element OR 6.3 is fed to the reset input R of the register 6.4, which leads to the setting of a logic zero at its outputs Q ₁ -Q _K , and, accordingly, at all bits K- bit output "Event code" 21. Upon completion of the initial reset operation at the input "Initial reset" 18 the device sets the value of the logical zero, which leads to the setting of the logical zero at the second information input To the JK trigger 4.2 and at the reset input R of the counter 4 .7.

The installation of the first and second bit masks, providing the identification of each of the N types of BDI, is carried out in the corresponding blocks of mask storage 1 ₁ -1 _N. For this, the corresponding first bit masks are set at the first L-bit inputs of Mask 1 12 ₁ -12 _{N of} each of the N mask storage units 1 ₁ -1 _N , and 13 ₁ -13 _N at the first L-bit inputs of Mask 2 of each of N mask storage units 1 ₁ −1 _N , respective second bit masks are set. At the write enable input 10, the device sets the value of the logical unit, which is fed to the initialization inputs of the first and second registers 1.1 and 1.2 of each of the N mask storage units and provides the first and second bit masks in the corresponding registers. At the end of the write operation at the input of the write permission 10, the device sets the value of logical zero.

, должна быть записана по адресу, соответствующему ее порядковому номеру, то есть адресу, значение которого равно n. Для этого на управляющем входе 24 устройства устанавливают значение логической единицы, которая, поступая на управляющий вход SE селектора-мультиплексора 5.1, обеспечивает коммутацию второй группы информационных входов B₁-В_K селектора-мультиплексора 5.1 на его выходы Q₁-q_K, где К=(log₂N)+1 - количество двоичных разрядов, достаточное для адресации N масок переходов и маски начала сценария поиска. На K-разрядном адресном входе 22 устройства устанавливают K-разрядный адрес, по которому в оперативное запоминающее устройство 5.2 должна быть записана маска начала сценария поиска. С выходов Q₁-Q_K селектора-мультиплексора 5.1 K-разрядный адрес поступает на адресные входы A₁-А_к оперативного запоминающего устройства 5.2. На N-разрядном информационном входе 23 устройства устанавливают маску начала сценария поиска, которая поступает на информационные входы D₁-D_N оперативного запоминающего устройства 5.2. Запись осуществляется путем установки логического нуля на входах "Выбор кристалла" 25 и "Чтение/запись" 26 устройства, с которых логический ноль поступает на соответствующие входы

и

оперативного запоминающего устройства 5.2. По окончании записи маски на входе "Выбор кристалла" 25 устанавливают значение логической единицы. Затем на K-разрядном адресном входе 22 устройства устанавливают K-разрядный адрес, по которому в оперативное запоминающее устройство должна быть записана первая маска переходов МР₁ (значение адреса равно 1), а на N-разрядном информационном входе 23 устройства устанавливают маску переходов МР₁, после чего путем установки значения логического нуля на входе "Выбор кристалла" 25 инициируют операцию записи в оперативное запоминающее устройство 5.2. Аналогичным образом в оперативное запоминающее устройство записывают все N масок переходов. По окончании записи масок переходов в оперативное запоминающее устройство на входе "Чтение/запись" 26 устанавливают значение логической единицы, а на управляющем входе 24 устройства устанавливают значение логического нуля, что обеспечивает коммутацию первой группы информационных входов A₁-А_K селектора-мультиплексора 5.1 на его выходы Q₁-Q_K.The mask of the beginning of the search script and transition masks are set in the random access memory 5.2 of the search strategy register 5. In this case, the mask of the beginning of the search script MB must be written to the random access memory at the zero address, and the nth transition mask

, must be recorded at the address corresponding to its serial number, that is, an address whose value is n. To do this, set the value of a logical unit at the control input 24 of the device, which, when fed to the control input SE of the selector-multiplexer 5.1, provides switching of the second group of information inputs B ₁ -B _{K of the} selector-multiplexer 5.1 to its outputs Q ₁ -q _K , where K = (log ₂ N) +1 - the number of bits that is sufficient for addressing N transition masks and the mask of the beginning of the search script. At the K-bit address input of the device 22, a K-bit address is set at which the mask of the beginning of the search script should be written to the random access memory 5.2. From the outputs Q ₁ -Q _{K of the} selector-multiplexer 5.1, the K-bit address is supplied to the address inputs A ₁ -A of _the random access memory 5.2. On the N-bit information input 23 of the device set the mask of the beginning of the search script, which is fed to the information inputs D ₁ -D _N random access memory 5.2. Writing is carried out by setting a logical zero at the inputs "Choice of crystal" 25 and "Read / write" 26 devices, from which a logical zero is supplied to the corresponding inputs

and

random access memory 5.2. At the end of the recording mask at the input of "Crystal Select" 25 set the value of the logical unit. Then, on the K-bit address input of the device 22, a K-bit address is set at which the first transition mask MP ₁ (address value is 1) should be written to the random access memory, and on the N-bit information input 23 of the device, the transition mask MP ₁ then, by setting the value of logical zero at the input "Choice of crystal" 25 initiate the operation of writing to random access memory 5.2. Similarly, all N transition masks are written to the random access memory. At the end of writing the transition masks to the random access memory at the “Read / write” input 26, a logical unit value is set, and a logical zero value is set at the control input 24 of the device, which ensures switching of the first group of information inputs A ₁ -A _{K of the} selector-multiplexer 5.1 to its outputs are Q ₁ -Q _K.

Setting the end mask of the search script MF consists in setting the device logical values corresponding to the bit values of the end mask of the search script on the bits of the K-bit input "Search termination rule" 27.

Setting the time to wait for the next BDI consists in setting logical values corresponding to the values of the bits of the time-out code on the bits on the M-bit input "Code time-out" 19.

After performing these operations, the device is ready for operation.

будет установлено значение логической единицы. Значения логической единицы с инверсных выходов

дешифратора 7.1 поступает на первые входы соответствующих двухвходовых элементов ИЛИ 7.2₁-7.2_N. В результате на выходах всех двухвходовых элементов ИЛИ 7.2₁-7.2_N устанавливается значение логической единицы вне зависимости от логических значений на их вторых входах. Это приводит к установке значения логической единицы на выходе N-входового элемента И 7.3, а соответственно и на выходе "Результат поиска" 28 устройства. Логические значения на выходе "Результат поиска" 28 устройства имеют следующее значение: логический ноль на указанном выходе означает, что во входящем потоке БДИ обнаружен заданный сценарий поиска, а логическая единица - отсутствие заданного сценария поиска. На входе "Чтение/запись" 26 регистра стратегии поиска 5 установлено значение логической единицы, что обеспечивает перевод оперативного запоминающего устройства 5.2 в режим чтения информации. При этом на входе "Выбор кристалла" 25 регистра стратегии поиска 5 также установлено значение логической единицы. На разрешающем входе 29 устройства установлено значение логической единицы, что обеспечивает установку на сигнальном выходе 17 регистра стратегии поиска 5 значения логического нуля. При этом на выходе JK-триггера 4.2, на его первом и втором информационных входах установлено значение логического нуля.In the initial period, when the BDIs to be analyzed do not arrive at the input of the device, clock pulses are received from the external generator to the input of the frequency divider 3 through the first clock input 8 of the device. From the output of the frequency divider 3 clock pulses are fed to the second clock input 9 of the shaper of time intervals 4. As a result of the operation of the initial reset of the device at all information outputs Q ₁ -Q _{K of} register 6.4, and, accordingly, at all bits of the K-bit output "Event code "21 block formation mask transitions 6 set to logical zero. A logical zero value is set at the control input 24 of the search strategy register 5, which ensures switching of logical zero values from the bits of the K-bit input "Event code" 21 of the search strategy register 5 to the corresponding address inputs A ₁ -A _{K of} random access memory 5.2. Thus, a zero address is set at the address input of random access memory pointing to the mask of the beginning of the search script. The values of logical zero from the bits of the K-bit output "Event code" 21 of the block forming the address of the transition mask 6 are supplied to the corresponding bits of the input "Event code" 21 of the indicating unit 7 and then to the inputs Y ₁ -Y _{K of the} decoder 7.1. If there is a logical zero value at all inputs Y ₁ -Y _{K of the} decoder 7.1, at all its inverse outputs

the logical unit value will be set. Logic Unit Values from Inverted Outputs

the decoder 7.1 arrives at the first inputs of the corresponding two-input elements OR 7.2 ₁ -7.2 _N. As a result, at the outputs of all two-input elements OR 7.2 ₁ -7.2 _N , the value of the logical unit is set regardless of the logical values at their second inputs. This leads to the installation of the value of the logical unit at the output of the N-input element AND 7.3, and, accordingly, at the output of the "Search Result" 28 of the device. Logical values at the “Search Result” output 28 of the device have the following meaning: a logical zero at the indicated output means that a specified search script has been detected in the incoming BDI stream, and a logical unit is the absence of a specified search script. At the input "Read / write" 26 register search strategy 5, the value of the logical unit is set, which ensures the transfer of random access memory 5.2 in the mode of reading information. At the same time, at the input "Choice of Crystal" 25 register search strategy 5 also set the value of the logical unit. At the enable input 29 of the device, a logical unit value is set, which ensures that the signal output 17 of the search strategy register 5 is set to a logical zero value. At the same time, the output of the JK-trigger 4.2, at its first and second information inputs, is set to a logical zero.

Upon receipt of the BDI to be analyzed, the logical values corresponding to the binary bits of the BDI are set at the L-bit information input 11 of the device. The moment of time corresponding to the installation of the BDI on the L-bit information input 11 of the device is denoted as T ₁ . From the L-bit information input 11 of the device, the BDI is fed to the L-bit information inputs of the selection blocks 2 ₁ -2 _N. Each selection block identifies the BDI of the corresponding type. The type of BDI is determined by the first and second bit masks supplied respectively to the second L-bit input "Mask 1" and the second L-bit input "Mask 2" of the selection block. In comparators 2.3 of each selection block 2 ₁ -2 _N , the values of the identification bits of the received BDI are compared with the values of the corresponding bits of the second bit mask. Identification bits are allocated in the first and second groups of two-input elements AND 2.1 ₁ -2.1 _L , 2.2 ₁ 1-2.2 _{L of} each selection block based on the corresponding first bit mask. In case of equality of the compared values at the output of the equality "A = B" of the comparator 2.3, the value of the logical unit is set, otherwise, the value of the logical zero. The logical value corresponding to the comparison result, from the output "A = B" of the comparator is inverted by inverter 2.4 and goes to the output "Comparison result" of the selection block. Thus, upon receipt of a BDI, the type of which corresponds to one of the BDI types provided in the search script, at the output “Comparison Result” of the selection block, in which the matching values of the identification bits of the incoming BDI with the corresponding values of the second bitmask are found, the value of logical zero , and at the outputs of all other selection blocks - the value of a logical unit. Upon receipt of the BDI, not provided for by the search script, the logical unit value will be set at the outputs “Comparison result” of all selection blocks. Boolean values corresponding to the comparison results from the outputs of the selection blocks are sent to the corresponding inputs "Comparison result" (16 ₁ -16 _N ) of the search strategy register 5 and the block for generating the address of transition mask 6.

In the register of the search strategy 5, the correspondence identified by the selection blocks of the BDI type to the type expected according to the search script is checked. The check is carried out regardless of the results of the identification of the BDI in the selection blocks. The type (s) of the expected BDI are determined by the mask of the beginning of the search script or by the transition masks stored in the random access memory 5.2. The mask, the conformity of which is checked, is determined by the K-bit address installed on the address inputs A ₁ -A _{K of} random access memory 5.2. The address is the code installed on the K-bit input "Event Code" 21 of the search strategy register 5. From the K-bit input "Event Code" 21, this code is sent to the first group of information inputs A ₁ -A _{K of the} selector-multiplexer 5.1, where, if there is a logical zero value at the control input SE of the selector-multiplexer 5.1, it is switched to the address inputs of random access memory 5.2. The corresponding mask is read by setting the logic zero value at the input "Crystal Choice" 25 of the search strategy register 5. Setting the logical zero value at the input "Crystal Choice" 25 of the search strategy register must be delayed with respect to time T ₁ determined by the signal delay time in the selection block. Let us designate the time of setting a logical zero at the input "Choice of crystal" 25 register strategy search 5 as T ₂ . Checking the correspondence of the identified BDI type to the type expected according to the search script is carried out by three-input elements OR-NOT 5.3 ₁ -5.3 _N. In this case, the first inputs of the three-input elements OR NOT 5.3 ₁ -5.3 _N receive logical values from the outputs of the corresponding selection blocks 2 ₁ -2 _N , and the second inputs receive logical values corresponding to the mask read from the random access memory 5.2. The verification results come from the outputs of the three-input elements OR-NOT 5.3 ₁ -5.3 _N to the corresponding inputs of the N-input element OR 5.4 after setting the value of the logical zero at the enable input 29 of the device. Setting the value of logical zero at the enable input 29 of the device should be carried out with a time delay relative to the time T ₂ , determined by the time of reading information from random access memory 5.2. Let us designate the time of setting a logical zero at the enable input 29 of the device as T ₃ . If the identified type of BDI coincides with one of the types expected according to the search scenario, the output of the corresponding three-input OR-NOT element, and therefore, the signal output 17 of the search strategy register 5, will be set to the value of the logical unit, which is fed to the signal input 17 of the formation unit addresses of the transition mask 6 and the shaper of time intervals 4.

шифратора 6.1 (нулевой вход шифратора 6.1 не используется, при этом на нем всегда должно быть установлено значение логической единицы). Если поступивший БДИ идентифицирован одним из блоков селекции 2₁-2_N, на инверсном входе шифратора 6.1, номер которого соответствует номеру блока селекции, идентифицировавшего БДИ, будет установлено значение логического нуля, а на всех остальных инверсных входах - значение логической единицы. При этом на инверсных выходах

дешифратора 6.1 установится код, соответствующий инверсному представлению номера входа дешифратора, на котором установлено значение логического нуля. Инверторами 6.2₁-6.2_K данный код преобразуется в код типа БДИ, то есть код, соответствующий номеру блока селекции, идентифицировавшего поступивший БДИ. Данный код используется в качестве адреса, по которому в оперативном запоминающем устройстве 5.2 хранится соответствующая маска переходов. С выходов инверторов 6.2₁-6.2_K K-разрядный код типа БДИ поступает на соответствующие информационные входы D₁-D_K регистра 6.4. Запись кода типа БДИ в регистр 6.4 осуществляется только при поступлении на сигнальный вход 17 блока формирования адреса маски переходов 6 значения логической единицы, то есть только в том случае, когда в блоке стратегии поиска 5 будет обнаружено соответствие типа поступившего БДИ типу, ожидаемому согласно сценария поиска. В противном случае в регистре 6.4 сохраняется предыдущее значение кода типа БДИ. Таким образом, на K-разрядном выходе "Код события" 21 блока формирования адреса маски переходов 6 всегда установлен код, соответствующий адресу, по которому в оперативном запоминающем устройстве 5.2 хранится маска переходов, определяющая тип (типы) ожидаемых согласно сценария поиска БДИ. С K-разрядного выхода "Код события" 21 блока формирования адреса маски переходов 6 код типа БДИ поступает на соответствующие входы регистра стратегии поиска 5 и блока индикации 7.If the type of incoming BDI matches the type expected according to the search script, in the block of generating the address of the transition mask 6, based on the identification results of the received BDI, the address is generated by which the transition mask is stored in the random access memory 5.2, which determines the next type (types) of the BDI . Logical values corresponding to the results of the identification of the BDI from the outputs of the selection blocks 2 ₁ -2 _N are supplied to the corresponding inputs “Comparison result” 16 ₁ -16 _{N of the} block for generating the address of transition mask 6 and then to the corresponding inverse inputs

the encoder 6.1 (the zero input of the encoder 6.1 is not used, and the value of the logical unit should always be set on it). If the received BDI is identified by one of the selection blocks 2 ₁ -2 _N , at the inverse input of the encoder 6.1, the number of which corresponds to the number of the selection block that identified the BDI, the value will be set to logical zero, and on all other inverse inputs - the value of the logical unit. At the same time on inverse outputs

of the decoder 6.1, a code is set corresponding to the inverse representation of the decoder's input number, on which the value of logical zero is set. Inverters 6.2 ₁ -6.2 _K, this code is converted into a code of type BDI, that is, a code corresponding to the number of the selection block that identified the incoming BDI. This code is used as the address where the corresponding transition mask is stored in the random access memory 5.2. From the outputs of the inverters 6.2 ₁ -6.2 _{K the} K-bit code of the BDI type is supplied to the corresponding information inputs D ₁ -D _{K of the} register 6.4. Writing a code of type BDI in register 6.4 is carried out only when a logical unit value is received at the signal input 17 of the unit for generating the transition mask address 6, that is, only if the type of the received BDI matches the type expected in the search script in the search strategy block 5 . Otherwise, in register 6.4, the previous value of the code of the BDI type is stored. Thus, on the K-bit output “Event Code” 21 of the transition mask address generation unit 6, a code is always set corresponding to the address at which the transition mask is stored in the random access memory 5.2, which determines the type (s) expected according to the BDI search script. From the K-bit output "Event Code" 21 of the block forming the address of the transition mask 6, a code of the BDI type is supplied to the corresponding inputs of the search strategy register 5 and display unit 7.

If the type of the received BDI matches the expected type, the value of the logical unit from the signal output 17 of the search strategy register 5 is supplied to the corresponding input of the time interval shaper 4. From the signal output 17 of the time interval shaper 4, the value of the logical unit goes to the write permission V of the counter 4.7 and the first information J JK trigger input 4.2. At the same time, the code for the waiting time for the next BDI installed on the M-bit input “Code for the waiting time” 19 of the device is recorded in the counter 4.7 and the output of the JK trigger 4.2 generates a value of a logical unit (since its second information input K sets the logical value zero). The value of the logical unit from the output of the JK-trigger 4.2, arriving at the second input of the first two-input element And 4.3, allows the receipt of clock pulses from the second clock input 9 of the shaper time intervals to the counting input from the counter 4.7. Thus, in the shaper of time intervals, a countdown of the waiting time of the next BDI is initiated.

The end of the analysis of the received BDI and the transition to waiting for the next BDI is carried out by setting the value of the logical unit at the enable input 29 of the device, which leads to the unconditional setting of the logical zero at the signal output 17 of the search strategy register 5. For the correct operation of the device, setting the value of the logical unit at the enable input 29 should be carried out with a time delay ΔT relative to the instant of time T _3, defined by the delay time of parallel switching elements trehvhodovyh DOES _NOT-1 5.3 -5.3 _{N, N-OR} input elements 5.4 and the maximum delay time of recording in the register 6.4, the time-delay JK-flip-flop 4.2, and the recording delay time counter 4.7:

where ΔТ _5.3 - the delay time of the parallel operation of the three-input elements OR NOT 5.3 ₁ -5.3 _N ;

ΔT _5.4 is the delay time of the N-input element OR 5.4;

ΔT _6.4 is the delay time for writing to register 6.4;

ΔT _4.2 is the delay time of the JK trigger 4.2;

ΔT _4.7 is the delay time for writing to the counter 4.7.

Simultaneously with setting the value of the logical unit at the enable input 29 of the device, the setting of the value of the logical unit at the input "Crystal Select" 25 is carried out.

If before the expiration of the waiting time another BDI arrives, the type of which corresponds to the type expected according to the search scenario, then the value of the logical unit at the signal output 17 of the search strategy register will lead to the re-initialization of the counter 4.7 of the time interval generator 4 (re-recording the time-out code of the waiting time for the next BD ) In this case, the logical value at the output of JK-trigger 4.2 will not change (since its second information input K has a logical zero value), and clock pulses will continue to be received at the counting input C of counter 4.7. Thus, the countdown of the waiting time for the next BDI will start from the beginning.

If the next BDI corresponding to the search script does not arrive before the timeout expires, then counter overflow 4.7. At the same time, at the output P of the counter overflow 4.7, the value of the logical unit is set, which goes to the second input of the second two-input element AND 4.5 and through the first two-input element OR 4.1 to the second information input K of the JK trigger 4.2. The values of the logical unit at the output of the overflow P of the counter 4.7 and at the signal input 17 of the shaper time intervals can be set at arbitrary points in time. In this regard, the following combinations of logical values may appear on the information inputs of the JK trigger 4.2:

at the first information input J of the JK trigger 4.2, a value of logical zero is set, and at its second information input K, a value of a logical unit is set;

On the first and second information inputs of the JK-trigger 4.2, the values of the logical unit are set.

In the first case, at the output of the JK trigger 4.2, a logic zero value will be set, which will go to the second input of the first two-input element And 4.3 and to the input of the inverter 4.4. The value of logical zero at the second input of the first two-input element And 4.3 will lead to the termination of the receipt of clock pulses from the second clock input 9 of the shaper time intervals 4 to the counting input from the counter 4.7. The value of logical zero at the input of the inverter 4.4 will lead to the setting of the value of the logical unit at the first input of the second two-input element AND 4.5, which, if there is the value of the logical unit at its second input, will lead to the setting of the value of the logical unit at the second input of the second two-input element OR 4.6 and the output " Reset "20 of the shaper of time intervals 4. The value of the logical unit at the second input of the second two-input element OR 4.6 will reset the counter 4.7, and the value of the logical unit at the output" Reset "20 a reset register 6.4 transitions mask forming unit 6. The address counter is reset will set at its overflow output P value logical zero, which goes to the second information input of the JK-K flip-flop 4.2, and the second input of the second two-input AND gate 4.5. In this case, the output "Reset" 20 of the shaper of time intervals 4 sets the value of logical zero. Resetting the register 6.4 of the address mask generation block of transitions 6 will result in the installation of address inputs A ₁ -A _{K of} random access memory 5.2 of the search strategy register 5 of the zero address. Thus, the search for the next BDI, determined by the current transition mask, is interrupted and the device proceeds to wait for the BDI, the types of which are determined by the mask of the beginning of the search script (initial BDI).

In the second case, the logical value at the output of the JK trigger 4.2 does not change. In this case, clock pulses will continue to be supplied to the counting input C of the counter 4.7, and the output of the second two-input element And 4.5 will remain the value of the logical zero (despite the value of the logical unit at its second input). The value of the logical unit at the signal input 17 of the shaper time intervals 4 will lead to the recording of the waiting code of the next BDI installed on the M-bit input "Code timeout" 19 in the counter 4.7. At the same time, at the output of the overflow P of counter 4.7, a logical zero value will be set, which will go to the second information input K of the JK trigger 4.2 and to the second input of the second two-input element And 4.5. Thus, the reset of register 6.4 of the unit for generating the address of the transition mask 6 will not occur and the address corresponding to the address of the next transition mask will be set at the address inputs A ₁ -A _{K of the} random access memory 5.2 of the search strategy register 5. In this regard, the operation of the device to search for the next (according to the search script) BDI will continue.

дешифратора 7.1 поступают на первые входы соответствующих двухвходовых элементов ИЛИ 7.2₁-7.2_N, где происходит их сравнение с значениями маски окончания сценария поиска, установленными на N-разрядном входе "Правило завершения поиска" 27. При совпадении логических значений на входах двухвходового элемента ИЛИ, номер которого соответствует коду типа БДИ, на его выходе установится значение логического нуля, которое через N-входовый элемент И 7.3 поступит на выход "Результат поиска" 28 устройства, что соответствует обнаружению в входящем потоке БДИ последовательности БДИ, соответствующей сценарию поиска.Upon receipt of the BDI, the type of which corresponds to one of the BDI types specified in the mask for the end of the search script (final BDI), the output “Search result” 28 of the device generates a value of logical zero. The formation of the value of logical zero at the output "Search Result" 28 of the device is as follows. From the bits of the K-bit input "Event Code" 21 of the display unit 7, a code of the type BDI is supplied to the corresponding inputs Y ₁ -Y _{K of the} decoder 7.1. At the same time, the inverse output of the decoder 7.1, whose number corresponds to the code of the BDI type, will be set to a logical zero, and at all other outputs of the decoder, the value of a logical unit. Logical values from outputs

decoder 7.1 is fed to the first inputs of the corresponding two-input elements OR 7.2 ₁ -7.2 _N , where they are compared with the values of the mask for the end of the search script installed on the N-bit input "Search completion rule" 27. If the logical values at the inputs of the two-input OR element match, the number of which corresponds to a code of type BDI, a logic zero value is set at its output, which, through the N-input element AND 7.3, goes to the output “Search Result” 28 of the device, which corresponds to detection in the input stream of the BDI BDI sequence matching the search script.

Thus, the proposed device information retrieval provides the following functions:

parallel identification of incoming BDI;

BDI order control;

control of intervals following BDI;

signaling that a BDI sequence specified by the search script has been detected.

Claims (6)

1. An information search device containing N> 2 selection blocks, a search strategy register, a time interval shaper, an indication unit, a frequency divider, the clock input of which is the first clock input of the device, the “Result of comparison” outputs of the selection blocks are connected to the corresponding inputs “Comparison result "search strategy register, characterized in that additionally mask storage blocks and a transition mask address generation block are added, K-bit, where K = (log ₂ N) +1, the event code output of which is connected to K-bit the input inputs "Event code" of the search strategy register and the display unit, the recording permission inputs of all mask storage units are interconnected and are the device recording permission input, the corresponding bits of L-bit information inputs, where L≥2, selection blocks are combined and are corresponding bits L-bit information input of the device, the first L-bit inputs "Mask 1" and "Mask 2" of the j-th mask storage unit, where j = 1, 2, ..., N, are the j-th first L-bit inputs Mask 1 and Mask 2, respectively, of the device, WTO the L-bit outputs “Mask 1” and “Mask 2” of the j-th mask storage unit are connected to the corresponding second L-bit inputs “Mask 1” and “Mask 2” of the j-th selection block, the outputs “Compare result” of the selection blocks connected to the corresponding inputs “Comparison result” of the transition mask address generation unit, the output of the frequency divider is connected to the clock input of the time interval generator, the “Initial reset” input of which is connected to the “Initial reset” input of the transition mask address generation unit and is the “Initial reset” input device properties, M-bit input "Time-out code" of the time slot generator, where M≥2 is the bit depth of the time-delay code, is the M-bit input "Time-out code" of the device, and the output of the time interval generator is connected to the "Reset" input of the forming unit transition mask addresses, the signal output of the search strategy register is connected to the signal inputs of the time slot generator and the transition mask address generation block, K-bit address input, control input, N-bit information input and section The input of the search strategy register is respectively the K-bit address input, the control input, the N-bit information input and the enable input of the device, the Read / Write input of the search strategy register is the Read / Write input of the device, N-bit input "Rule termination of the search "and exit" Search result "of the display unit are respectively the N-bit input" Search termination rule "and the output" Search result "of the device, and the search strategy register consists of a selector-multiplexer, opera memory, N three-way OR-NOT elements, N-input OR element, the output of which is the signal output of the search strategy register, the j-th input of the N-input OR element is connected to the inverse output of the j-th three-input element OR-NOT, the first input of the j-th three-input OR-NOT element is the j-th input "Comparison result" of the search strategy register, the second input of the j-th three-input OR-NOT element is connected to the j-th information output of random access memory, and the third inputs of all three-input OR - NOT interconnected and are the resolving input of the search strategy register, rth, where r = 1, 2, ..., K, the address input of the random access memory is connected to the rth output of the selector-multiplexer, the jth information input random access memory is the j-th bit of the N-bit information input of the search strategy register, and the inverse inputs "Crystal Choice" and "Read / Write" random access memory are the input "Crystal Choice" to set it to a logical zero value at reading or writing the corresponding mask and the "Read / write" input of the search strategy register, the rth input of the first group of information inputs of the selector-multiplexer is the r-bit of the K-bit input "Event code" of the search strategy register, the rth input of the second group of information the input of the selector-multiplexer is the rth bit of the K-bit address input of the search strategy register, and the control input of the selector of the multiplexer is the control input of the search strategy register. 2. The device according to claim 1, characterized in that the mask storage unit consists of first and second registers, the information outputs of the first register are the corresponding bits of the second L-bit output "Mask 1" of the mask storage unit, and the information outputs of the second register are the corresponding bits the second L-bit output "Mask 2" of the mask storage unit, the recording permission inputs of the first and second registers are interconnected and are the recording permission input of the mask storage unit, information inputs of the first register and are the corresponding bits of the first L-bit input "Mask 1" of the mask storage unit, and the information inputs of the second register are the corresponding bits of the first L-bit input "Mask 2" of the mask storage unit. 3. The device according to claim 1, characterized in that the selection block consists of the first and second groups of two-input elements And L elements in each group, a comparator, an inverter, the inverse output of which is the "Result of comparison" output of the selection block, the inverter input is connected to the equality output of the comparator, i-th, where i = 1, 2, ..., L, the input of the first group of information inputs of the comparator is connected to the output of the i-th two-input element And the first group of two-input elements And, and the i-th, the input of the second group information inputs of the comparator is connected to the output i- of the second two-input element And the second group of two-input elements And, the first input of the i-th two-input element And the first group of two-input elements And is the i-th bit of the L-bit information input of the selection block, the second input of the i-th two-input element And the first group of two-input elements And is connected with the first input of the i-th two-input element And the second group of two-input elements And is the i-th bit of the second L-bit input "Mask 1" of the selection block, and the second input of the i-th two-input element And the second group of two-input electronic And cops is i-m bits of the second L-bit input "Mask 2 'selection unit. 4. The device according to claim 1, characterized in that the time interval shaper consists of a first two-input OR element, a JK trigger, a first two-input element AND, an inverter, a second two-input element AND, a second two-input element OR, a counter, the overflow output of which is connected to the second inputs of the second two-input element AND and the first two-input element OR, the first input of the first two-input element OR is connected to the first input of the second two-input element OR and is the input "Initial reset" form of the time interval, the output of the first two-input OR element is connected to the second information input of the JK trigger, the first information input of which is connected to the counter enable input and is the signal input of the time interval generator, e-th, where e = 1, 2, ... , M, the information input of the counter is the e-th digit of the M-bit input "Timeout code" of the time shaper, the reset input of the counter is connected to the output of the second two-input element OR, and the counter input of the counter is connected to the output of the first of the two-input element And, the first input of which is the second clock input of the time slot former, the output of the JK trigger is connected to the second input of the first two-input element And and the inverter input, the output of which is connected to the first input of the second two-input element And, the output of the second two-input element And is connected to the second input of the second two-input element OR and is the output "Reset" of the shaper time intervals. 5. The device according to claim 1, characterized in that the transition mask address generating unit consists of an encoder, K inverters, a two-input OR element, a register, the rth information output of which is the rth bit of the K-bit output "Event code" of the block the formation of the address of the transition mask, the r-th information input of the register is connected to the inverse output of the r-th inverter, the input enable the register is the signal input of the block forming the address of the transition mask, the input of the reset register is connected to the output of the two-input element OR, the first and the second input of which is respectively the “Reset” input and the “Initial reset” input of the transition mask address generating unit, the input of the r-th inverter is connected to the r-th inverse output of the encoder, the j-th inverse input of which is the j-th input "Comparison result "block formation address mask transitions. 6. The device according to claim 1, characterized in that the display unit consists of a decoder, N two-input elements OR, N-input element AND, the output of which is the output "Search Result" of the display unit, and the j-th input of the N-input element AND connected to the output of the j-th two-input OR element, the first input of the j-th two-input OR element is connected to the j-th inverse output of the decoder, and the second input of the j-th two-input OR element is the j-th bit of the N-bit input "Search termination rule" of the display unit, the rth input of the decoder is the rth discharge of K- bit address input "Event code" of the display unit.

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