KR20050002424A - Method of manufacturing flash memory device - Google Patents

Abstract

PURPOSE: A method of manufacturing a flash memory device is provided to prevent under-cut of a control gate in spite of a sufficient over-etching process on the control gate by using an under-cut preventing spacer. CONSTITUTION: A tunnel oxide layer and a first conductive pattern are formed on a semiconductor substrate(11). A dielectric film, a second conductive layer(17) and a hard mask pattern(19) are sequentially formed on the resultant structure. The second conductive layer is partially etched by using a first gate etching process. An under-cut preventing spacer(100S) is formed at both sidewalls of the etched second conductive layer. A control gate is completed by etching again the second conductive layer using the spacer as an etching mask.

Description

Method of manufacturing flash memory device {Method of manufacturing flash memory device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a flash memory device capable of preventing undercut and gate bridge of a control gate generated when a control gate is formed. It is about.

The flash memory device includes a stack gate and a floating gate and a control gate. Due to the high step height of the polysilicon layer for the floating gate due to the stack gate structure, sufficient transient etching must be performed when forming the conductive layer for the control gate. However, when sufficient excessive etching is performed to form the control gate, an undercut is generated in the portion of the control gate in contact with the dielectric film. In order to prevent the undercut phenomenon, when the excessive etching target is insufficient, a dielectric film fence remains, which causes the floating gate polysilicon layer to remain on the substrate, causing a bridge phenomenon between neighboring gates. . It is very difficult to set an etching condition to satisfy both the undercut phenomenon and the gate bridge phenomenon, and this phenomenon becomes more intense as the device becomes more integrated, making it impossible to realize the high integration of the device.

Accordingly, the present invention prevents the undercut phenomenon from occurring in the control gate even when sufficient overetching is performed during the control gate etching process, thereby improving the electrical characteristics and the reliability of the device as well as providing a high integration of the device. The purpose is to provide a manufacturing method.

1 is a layout diagram of a flash memory device.

2 to 8 are cross-sectional views of devices for describing a method of manufacturing a flash memory device according to an embodiment of the present invention, where a is a cross-sectional view of a device cut along the line XX of FIG. It is sectional drawing of the element cut | disconnected along the Y1-Y1 line of FIG. 1, and c in each figure is sectional drawing of the element cut along the Y2-Y2 line | wire of FIG.

<Explanation of symbols for the main parts of the drawings>

11: semiconductor substrate 12: tunnel oxide film

13: first polysilicon layer 14: device isolation film

15: second polysilicon layer 16: dielectric film

17: third polysilicon layer 18: metal-silicide layer

19: hard mask layer 100: undercut prevention film

100S: Undercut prevention film spacer

Method for manufacturing a flash memory device according to an embodiment of the present invention for achieving this object, the active region is defined by the device isolation layer, the first conductivity is partially overlapped with the tunnel oxide film and the device isolation layer on the semiconductor substrate of the active region Forming a layer pattern; Forming a dielectric film and a second conductive layer on the entire structure including the first conductive layer pattern; Forming a hard mask layer pattern on the second conductive layer; Etching a thickness of the second conductive layer by a first gate etching process; Forming an undercut prevention layer spacer on an etching surface of the second conductive layer; Forming a control gate by etching the remaining thickness of the second conductive layer by a second gate etching process; And forming a floating gate by etching the dielectric layer and the first conductive layer pattern by a third gate etching process.

In the above, the first gate etching process includes a main etching process in which the etching target is set to remove the second conductive layer formed in the active region, and a transient etching in which the etching target is set to about 10 to 50% of the thickness of the second conductive layer. The process takes place.

The undercut prevention layer spacer is deposited by a low pressure chemical vapor deposition method using a nitride to a thickness of 20 ~ 70 ,, and then formed by a spacer etching process, the spacer etching process is 100 to 250% of the thickness of the undercut prevention layer Proceed by

The second gate etching process is performed by setting a sufficient etching target in consideration of the thickness of the second conductive layer left after the first gate etching process.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only this embodiment to make the disclosure of the present invention complete, and to those skilled in the art the scope of the invention It is provided for complete information. Like numbers refer to like elements in the figures.

1 is a layout diagram of a flash memory device. 2 to 8 are cross-sectional views of devices for describing a method of manufacturing a flash memory device according to an embodiment of the present invention, where a is a cross-sectional view of a device cut along the line XX of FIG. It is sectional drawing of the element cut | disconnected along the Y1-Y1 line of FIG. 1, and c in each figure is sectional drawing of the element cut along the Y2-Y2 line | wire of FIG.

1, 2A, 2B, and 2C, an element isolation layer 14 is formed in a field region of the semiconductor substrate 11 by a self-aligned element isolation (SA-STI) process, and between the element isolation layers 14. The tunnel oxide film 12 and the first polysilicon layer 13 for the floating gate are formed in the active region of the. The second polysilicon layer 15 for the floating gate is patterned by an etching process using a floating gate mask to partially cover the device isolation layer 14 while covering the first polysilicon layer 13 in the active region. The dielectric film 16 is formed over the entire structure including the patterned second polysilicon layer 15. The third polysilicon layer 17 and the metal-silicide layer 18 for the control gate are formed on the dielectric film 16. The hard mask layer 19 is formed on the metal-silicide layer 18. After forming a photoresist pattern (not shown) using a control gate mask, the hard mask layer 19 is patterned by an etching process using the photoresist pattern as an etching mask. Thereafter, the photoresist pattern is stripped and a wafer cleaning process is performed.

Referring to FIGS. 1, 3A, 3B, and 3C, the metal-silicide layer 18 may be subjected to a main etch process and an over etch using the patterned hard mask layer 19 as an etch mask. Patterning is performed in the process, and then the third polysilicon layer 17 is first patterned in the main etching process. The main etching process of the third polysilicon layer 17 is performed by setting an etch target to remove the third polysilicon layer 17 formed in the active region, thereby exposing the dielectric film 16 to the active region, The third polysilicon layer 17 remains in the field region by the height of the patterned second polysilicon layer 15.

1, 4A, 4B, and 4C, since the third polysilicon layer 17 is subjected to the transient etching process after the main etching process using the patterned hard mask layer 19 as an etching mask. The first gate etching process is completed. The over-etching process of the third polysilicon layer 17 causes the third polysilicon layer 17 to etch the etch target to such an extent that the first patterned third polysilicon layer 17 in the active region is not etch damaged. The thickness of 10 to 50% of the thickness of the second polysilicon layer 17 is lower than the height of the patterned second polysilicon layer 15.

1, 5A, 5B, and 5C, an undercut prevention layer 100 is formed along the upper surface of the entire structure of the second polysilicon layer 17.

In the above, the undercut prevention film 100 serves to protect the third polysilicon layer 17 patterned in the active region from etching damage during the subsequent etching process, and low pressure chemical vapor deposition (LPCVD) using nitride. It is formed by depositing a thickness of about 100 kPa or less, preferably 20 to 70 kPa.

1, 6A, 6B, and 6C, the undercut prevention layer 100 is etched by a spacer etching process, thereby etching the third polysilicon layer and the metal-silicide layers 17 and 18 thereon. An undercut prevention film spacer 100S is formed on the surface. In the spacer etching process, the etching target proceeds about 100 to 250% with respect to the thickness of the undercut prevention film 100. When the undercut prevention layer 100 is formed of nitride and the dielectric layer 16 is formed of an upper oxide / middle nitride / lower oxide (ONO) structure, the portion where the dielectric layer 16 is exposed during the spacer etching process is an upper oxide layer. And the middle nitride film is removed leaving only the lower oxide film.

1, 7A, 7B, and 7C, a third poly remaining in the field region by a second gate etching process using the hard mask layer 19 as an etch mask while the undercut prevention layer spacer 100S is formed. The silicon layer 17 is completely removed to form a control gate. The second control gate etching process is performed by setting a sufficient etching target in consideration of the remaining thickness of the third polysilicon layer 17, wherein the third polysilicon layer 17 in contact with the dielectric film 16 in the active region The undercut protection layer spacer 100S is protected so that the undercut phenomenon does not occur in this portion, and the third polysilicon layer 17 does not remain on the substrate due to a sufficient excessive etching process, so that the gate bridge phenomenon does not occur. .

1, 8A, 8B, and 8C, the dielectric film 16, the second polysilicon layer 15, and the first poly in a third gate etching process using the hard mask layer 19 as an etching mask. The silicon layer 13 is patterned to form a floating gate of the first and second polysilicon layers 15.

Meanwhile, although the configuration of the NAND flash memory device to which the self-aligning device isolation process is applied has been described as an embodiment, the present invention is not limited thereto and is applicable to all semiconductor devices having a stack gate structure composed of a floating gate and a control gate. . That is, the first and second polysilicon layers 13 and 15 may be stacked as a conductive layer for the floating gate, but may be applied as a single layer or other conductive material. In addition, the conductive layer for the control gate may be applied to a single layer or another conductive material, not a structure in which the third polysilicon layer 17 and the metal-silicide layer 18 are stacked.

As described above, the present invention prevents the undercut phenomenon from occurring in the control gate even when sufficient etching is performed during the control gate etching process, thereby preventing the gate bridge phenomenon and securing the gate etching process margin. In addition to improving the electrical characteristics and reliability of the device, it is possible to realize high integration of the device.

Claims (8)

Forming a first conductive layer pattern in which an active region is defined by a device isolation layer and partially overlapping the tunnel oxide film and the device isolation layer on a semiconductor substrate of the active region; Forming a dielectric film and a second conductive layer on the entire structure including the first conductive layer pattern; Forming a hard mask layer pattern on the second conductive layer; Etching a thickness of the second conductive layer by a first gate etching process; Forming an undercut prevention layer spacer on an etching surface of the second conductive layer; Forming a control gate by etching the remaining thickness of the second conductive layer by a second gate etching process; And And forming a floating gate by etching the dielectric layer and the first conductive layer pattern by a third gate etching process. The method of claim 1, And the first conductive layer pattern is formed by stacking a first polysilicon layer and a second polysilicon layer. The method of claim 2, And the first polysilicon layer is formed on a semiconductor substrate in an active region together with a tunnel oxide film by a self-aligning device isolation process. The method of claim 1, The second conductive layer is a method of manufacturing a flash memory device formed by stacking a polysilicon layer and a metal-silicide layer. The method of claim 1, The first gate etching process includes a main etching process in which an etching target is set to remove the second conductive layer formed in the active region, and a transient target in which an etching target is set to about 10 to 50% of the thickness of the second conductive layer. A method of manufacturing a flash memory device comprising an etching process. The method of claim 1, The undercut prevention layer spacer is deposited by a low pressure chemical vapor deposition method using a nitride to a thickness of 20 ~ 70 Å, and then formed by a spacer etching process. The method of claim 6, The spacer etching process is a method of manufacturing a flash memory device to proceed with the etching target to 100 ~ 250% with respect to the thickness of the undercut prevention film. The method of claim 1, And the second gate etching process is set to a sufficient etching target in consideration of the thickness of the second conductive layer remaining after the first gate etching process.