KR101556160B1 - Thin film transistor array panel - Google Patents

Abstract

A thin film transistor array substrate capable of improving the response speed of a liquid crystal is provided. The thin film transistor array substrate includes a gate wiring and a data wiring which are insulated from each other and intersected with each other on an insulating substrate to define a pixel region, a thin film transistor formed at an intersection of the gate wiring and the data wiring, A capacitive electrode formed so that at least a part of the capacitive electrode overlaps with the data line and is oriented parallel to the data line and another portion overlaps with the at least two pixel electrodes and is free of openings or slits opposed to the data lines; And at least one of the at least two pixel electrodes is connected to a first side of the data line and a second side of the data line, And the other of the two pixel electrodes is disposed adjacent to a second side of the data line which is the opposite side of the first side of the data line, and the sustain line line is connected to the drain electrode extension It can be completely overlapped.

Description

[0001] The present invention relates to a thin film transistor array panel

The present invention relates to a thin film transistor array substrate, and more particularly, to a thin film transistor array substrate capable of improving the response speed of a liquid crystal.

2. Description of the Related Art In general, a liquid crystal display (LCD) is a liquid crystal display device that applies an intensity-controlled electric field to a liquid crystal having anisotropic permittivity injected between two substrates to adjust the amount of light transmitted through the substrate, .

Recently, various studies have been conducted to improve the response speed of liquid crystal. Methods for improving the response speed of the liquid crystal include a method of improving the driving conditions, a method of changing the liquid crystal material, and a method of changing the design structure. Here, as a method for improving the driving condition, first, there is a problem that the response speed of the liquid crystal is improved but the power consumption is increased if the rising time is increased by raising the driving voltage AVDD. Secondly, when the offset voltage is lowered, the falling time is increased and the response speed of the liquid crystal is partially improved. However, it is difficult to lower the offset voltage below a predetermined voltage to match the gamma value of the target gamma curve. Third, although the response speed of the liquid crystal can be partially improved through optimization of the common voltage, other problems such as afterimage and flicker occur.

Further, there are limitations in the method for changing the material of the liquid crystal.

Among the above methods, a method of changing the design structure is suitable for improving the response speed of the liquid crystal, but the response speed is still delayed.

On the other hand, the voltage sensed by the liquid crystal during one frame can be expressed by Equation (1).

&Quot; (1) " V = Q / (Cst + Clc)

Here, the amount of charge Q charged during one frame during the driving of the thin film transistor is kept constant by the charge conservation law, but the data voltage V changes as the liquid crystal capacitor Clc changes. In other words, as the liquid crystal capacitor Clc changes, the data voltage V applied to the pixel electrode may be reduced and a cusp may be generated. As a result, a delay occurs in response speed. For example, when the data voltage is applied to the pixel electrode in black (4V), when the data voltage is not applied to the pixel electrode in white (0.5V), and when the pixel electrode is changed from black to white, the holding capacitor Cst ) Is 0, the permittivity is 13.5 when the pixel electrode is in the black state, and the permittivity is 3.6 when it is in the white state. If the pixel electrode is black by the equation Q = (Cst + Clc) * V, The amount of charge (Q) becomes 6.75. Since the amount of charge Q in the liquid crystal is maintained by the law of conserving the charge amount, the voltage when the pixel electrode is in the white state is 1.875 by the equation 6.75 = (0 + 3.6) * V. Therefore, when the data voltage is not applied to the pixel electrode, the data voltage is 1.875 V, that is, gray state instead of 0.5V, and a cusp is generated. This occurs at the current frame and next frame boundary due to capacity shortage of the holding capacitor Cst.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a thin film transistor array substrate capable of improving the response speed of a liquid crystal.

The technical objects of the present invention are not limited to the above-mentioned technical problems, and other technical subjects not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a thin film transistor array substrate including a gate wiring and a data wiring which are insulated from each other and intersected with each other to define a pixel region, A drain electrode extension extending from the drain electrode, and a capacitive electrode which is at least partially overlapped and aligned in parallel with the data line, wherein another portion overlaps with the at least two pixel electrodes, A capacitive electrode formed so as to have no opening or slit facing the wiring; And at least one of the at least two pixel electrodes is connected to a first side of the data line and a second side of the data line, And the other of the two pixel electrodes is disposed adjacent to a second side of the data line which is the opposite side of the first side of the data line, and the sustain line line is connected to the drain electrode extension It can be completely overlapped.
The details of other embodiments are included in the detailed description and drawings.

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As described above, the thin film transistor substrate according to the present invention can improve the response speed of the liquid crystal by increasing the capacitance of the holding capacitor by forming the floating electrode overlapping the data line.

1 is a block diagram of a liquid crystal display including a thin film transistor array substrate according to a first embodiment of the present invention.
2 is a block diagram of a liquid crystal display including a thin film transistor array substrate according to a second embodiment of the present invention.
FIG. 3 is a layout diagram showing a thin film transistor array substrate according to a first embodiment of the present invention, which is applied to the block diagram of FIG.
4 is a cross-sectional view taken along line IIa'-IIa 'and IIb'-IIb' in FIG. 3;
5 is a schematic cross-sectional view of part A of Fig.
6 and 7 are views showing the arrangement of the data lines and the pixel electrodes of the thin film transistor array substrate according to the first embodiment of the present invention.
8 is a plan view showing various modifications of the floating electrode of the thin film transistor array substrate according to the first embodiment of the present invention.
FIG. 9 is a layout diagram showing a thin film transistor array substrate according to a second embodiment of the present invention, which is applied to the block diagram of FIG. 2. FIG.
10 is a cross-sectional view taken along lines IIa'-IIa 'and IIb'-IIb' in FIG.
11 is a layout diagram showing a thin film transistor array substrate according to a third embodiment of the present invention.
12 is a cross-sectional view taken along line IIa'-IIa 'and IIb'-IIb' of FIG.
13 and 14 are views showing the arrangement of the data lines and the pixel electrodes of the thin film transistor array substrate according to the third embodiment of the present invention.
15 is a plan view showing various modifications of the floating electrode of the thin film transistor array substrate according to the third embodiment of the present invention.
16 is a layout diagram showing a thin film transistor array substrate according to a fourth embodiment of the present invention.
17 is a cross-sectional view taken along lines IIa'-IIa 'and IIb'-IIb' in FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a liquid crystal display device including a thin film transistor array substrate according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of a liquid crystal display device including a thin film transistor array substrate according to a second embodiment of the present invention. Block diagram.

1 and 2, the liquid crystal display of the present invention includes a liquid crystal panel 100, a driving voltage generating unit 200, a gate driving unit 300, a gamma voltage generating unit 400, a data driving unit 500, And a timing controller 600.

The liquid crystal panel 100 is connected to a plurality of display signal lines G1 to Gn and D1 to Dm in terms of an equivalent circuit and includes a plurality of unit pixels arranged in a matrix form.

The display signal lines G1-Gn and D1-Dm include a plurality of gate lines G1-Gn for transmitting gate signals and data lines D1-Dm for transferring data signals. The gate lines G1 - Gn extend in the row direction, are substantially parallel to each other, the data lines D1 - Dm extend in the column direction, and are substantially parallel to each other.

Each unit pixel includes a switching element Q connected to the display signal lines G1-Gn and D1-Dm and a liquid crystal capacitor Clc and a storage capacitor Cst connected thereto. The storage capacitor Cst may be omitted as needed.

The switching element Q is provided on the TFT substrate. The control terminal and the input terminal of the switching element Q are connected to the gate lines G1 to Gn and the data lines D1 to Dm, respectively, (Clc) and the storage capacitor (Cst).

The liquid crystal capacitor Clc has two terminals, that is, a pixel electrode of the TFT substrate and a common electrode of the color filter substrate, and the liquid crystal layer between the two electrodes functions as a dielectric. The pixel electrode is connected to the switching element Q and the common electrode is formed on the front surface of the color filter substrate and receives the common voltage Vcom. Here, the common electrode may be provided on the TFT substrate, and both electrodes are made linear or rod-shaped.

 1 and 2, a liquid crystal display device including a thin film transistor array substrate according to a first embodiment of the present invention and a thin film transistor array substrate according to a second embodiment of the present invention includes: And has basically the same structure.

1, in the case of a liquid crystal display device including a thin film transistor array substrate according to the first embodiment of the present invention, the storage capacitor Cst has a structure in which the pixel electrode overlaps with the previous gate line immediately above the insulator A shear gate method is used. Here, since the pixels of the first row have no gate line at the previous stage, the storage capacitor gate line G0 of the first pixel row is added and the common voltage Vcom is applied to form the storage capacitor.

2, in the case of a liquid crystal display device including a thin film transistor array substrate according to the second embodiment of the present invention, the storage capacitor Cst has a structure in which a separate signal line provided on the thin film transistor substrate and a pixel electrode overlap each other And an independent wiring method in which a predetermined voltage such as the common voltage Vcom is applied to the separate signal line is used. That is, the liquid crystal display device including the thin film transistor array substrate according to the first embodiment of the present invention and the thin film transistor array substrate according to the second embodiment of the present invention includes the storage capacitor Cst Only the method is different and can be driven substantially the same.

On the other hand, in order to realize color display, each unit pixel must be able to display a color, which can be achieved by providing a red, green, or blue color filter in a region corresponding to the pixel electrode. Here, the color filter may be formed in the corresponding region of the color filter substrate, or may be formed on or below the pixel electrode of the TFT substrate.

A polarizer (not shown) for polarizing light is attached to the outer surface of at least one of the TFT substrate and the color filter substrate of the liquid crystal panel 100.

The driving voltage generator 200 generates a plurality of driving voltages. For example, the driving voltage generator 200 generates the gate-on voltage Von, the gate-off voltage Voff, and the common voltage Vcom.

The gate driver 300 is connected to the gate lines G1 to Gn of the liquid crystal panel 100 and supplies a gate signal composed of a combination of the gate on voltage Von and the gate off voltage Voff from the outside to the gate lines G1- Gn.

The gamma voltage generator 400 may generate two sets of gamma voltages related to the transmittance of the unit pixel. That is, one of the two sets is the positive data voltage and the other set is the negative data voltage. The positive polarity data voltage and the negative polarity data voltage are voltages having opposite polarity to the common voltage (Vcom), and are alternately provided to the liquid crystal panel in the inversion driving.

The data driver 500 is connected to the data lines D1 to Dm of the liquid crystal panel 100 and generates a plurality of data voltages based on the plurality of gamma voltages supplied from the gamma voltage generator 400, A data voltage is selected and applied to a unit pixel as a data signal and is usually composed of a plurality of integrated circuits.

The timing controller 600 generates a control signal for controlling operations of the gate driver 300 and the data driver 500 and supplies the corresponding control signals to the gate driver 300 and the data driver 500. [

FIG. 3 is a layout view showing a thin film transistor array substrate according to a first embodiment of the present invention, which is applied to the block diagram of FIG. 1, and FIG. 4 is a cross-sectional view taken along the line IIa'-IIa "and IIb'- And FIG. 5 is a schematic cross-sectional view of part A of FIG. 3, and FIGS. 6 and 7 are views showing the arrangement of data lines and pixel electrodes of a thin film transistor array substrate according to the first embodiment of the present invention, 8 is a plan view showing various modifications of the floating electrode of the thin film transistor array substrate according to the first embodiment of the present invention.

Referring to FIGS. 3 and 4, a plurality of gate wirings for transferring a gate signal are formed on an insulating substrate 10. The gate wirings 22, 24, 26, 27 and 28 are connected to the gate lines 22 extending in the horizontal direction and the gate ends 22 for receiving the gate signals from the outside and transmitting them to the gate lines. A gate electrode 26 of the thin film transistor formed in the form of a projection connected to the gate line 22, a sustain electrode 28 and a gate line 22 formed in parallel with the gate line 22, And a floating electrode 27 formed between the gate lines 28 in a direction perpendicular to the gate lines 22. [

The sustain electrode 28 overlaps the pixel electrode 82 to be described later to form a storage capacitor Cst1 for improving the charge storage ability of the pixel. The shape and arrangement of the sustain electrodes 28 may be modified into various shapes.

The floating electrode 27 is formed on the same layer as the gate wirings 22, 24, 26 and 28 as shown in FIG. 4, has a floating state in which no electric field is applied, As shown in FIG. 3, the floating electrode 27 is formed so as to overlap at least a part of the data line 62 and the pixel electrode 82, and the first to third overlap capacitors Cid, Cif, Cdf ). 5, the first overlap capacitor Cid is formed between the pixel electrode 82 and the data line 62, and between the second overlap capacitor Cif pixel electrode 82 and the floating electrode 27 And a third overlap capacitor Cdf is formed between the data line 62 and the floating electrode 27, respectively. Accordingly, in the present invention, since the floating electrode 27 is formed between the gate lines 22 so as to overlap with the data line 62, the first and third overlap capacitors Cid and Cif and Cdf are connected to the storage capacitor Cst1 And the capacity of the holding capacitor Cst is increased. This can be expressed as the following equation.

&Quot; (2) " Cst = Cst1 + [Cid + (Cif || Cdf)]

Since the capacitance of the capacitor varies depending on the area of the electrode and the distance between the electrodes, the area of the floating electrode 27 is increased to increase the capacitance of the third overlap capacitor 27 formed between the data line 62 and the floating electrode 27. [ (Cdf) can be increased.

When the capacitance of the third overlap capacitor Cdf is increased to increase the capacitance of the entire storage capacitor Cst, when one pixel is driven in the thin film transistor, the data voltage is applied to the pixel electrode during one frame (black state) , The storage capacitor Cst is charged, and the rate of discharging the charge to the storage capacitor Cst is increased when the data voltage is not applied to the pixel electrode in the next frame (white state). As a result, the response speed of the liquid crystal can be prevented from being delayed due to the cusp phenomenon occurring between the current frame and the next frame, thereby improving the response speed of the liquid crystal.

The floating electrode 27 may be formed in a polygonal pattern as shown in FIG. 3, or may be formed in a polygonal pattern in which a portion overlapping the data line is at least partially open as in FIGS. 8A to 8H . The floating electrode 27 includes first and second electrodes 27a and 27b formed with a data line 62 sandwiched therebetween and the first and second electrodes 27a and 27b are connected to the data line 62. [ And at least a part of which is overlapped with the connection electrode 27c.

As shown in FIG. 6, a pixel electrode 82 may be formed on the floating electrode 27 to overlap the floating electrode 27 on at least a portion of the data line 62. 7, a pixel electrode 82 may be formed on the floating electrode 27 so that at least a portion of the pixel electrode 82 overlaps the floating electrode 27 on both sides with respect to the data line 62. Referring to FIG.

The gate wirings 22, 24, 26 and 28 and the floating electrode 27 are made of a metal of aluminum series such as aluminum (Al) and an aluminum alloy, a series metal such as silver (Ag) Alloys and molybdenum metals such as molybdenum (Mo) and molybdenum alloys, chromium (Cr), titanium (Ti), tantalum (Ta) and the like. Further, the gate wiring lines 22, 24, 26, and 28 and the floating electrode 27 may have a multi-film structure including two conductive films (not shown) having different physical properties. One of the conductive films is made of a metal having a low resistivity such as an aluminum-based metal, a silver-based metal, a copper-based metal or the like so as to reduce signal delay or voltage drop of the gate wirings 22, 24, . Alternatively, the other conductive film may be made of a material having excellent contact properties with other materials, particularly ITO (indium tin oxide) and IZO (indium zinc oxide), such as molybdenum metal, chromium, titanium, tantalum and the like. A good example of such a combination is a chromium bottom film, an aluminum top film, an aluminum bottom film and a molybdenum top film. However, the present invention is not limited thereto, and the gate wirings 22, 24, 26, and 28 and the floating electrode 27 may be formed of various metals and conductors.

A gate insulating film 30 made of silicon nitride (SiNx) or the like is formed on the substrate 10, the gate wirings 22, 24, 26, and 28 and the floating electrode 27.

A semiconductor layer 44 made of a semiconductor such as hydrogenated amorphous silicon or polycrystalline silicon is formed in an island shape on the gate insulating film 30 of the gate electrode 26. A silicide or n-type impurity Resistive contact layers 55 and 56 made of a material such as n + hydrogenated amorphous silicon doped with the high concentration are formed.

Data lines 62, 65, 66, 67, and 68 are formed on the ohmic contact layers 55 and 56 and the gate insulating film 30, respectively. The data lines 62, 65, 66, 67, and 68 are vertically formed and intersect the gate line 22 to define a pixel. The data line 62 is a branch of the data line 62, and the ohmic contact layer 55 A data terminal 68 connected to one end of the data line 62 to receive an image signal from the outside and a source electrode 65 separated from the gate electrode 26 ) Or a drain electrode 66 extending from the drain electrode 66 and the drain electrode 66 formed on the resistive contact layer 56 on the opposite side of the source electrode 65 to the channel portion of the thin film transistor and overlapping the pixel electrode 27 And an electrode extension portion 67.

The data line 62, the source electrode 65, and the drain electrode 66 are preferably formed of a refractory metal such as chromium, molybdenum-based metal, tantalum, and titanium, And may have a multi-layer structure consisting of a lower film (not shown) such as a refractory metal and a low resistance material upper film (not shown) located thereon. Examples of the multilayer structure include a triple layer of a molybdenum film-aluminum film-molybdenum film in addition to the chromium lower film and the aluminum upper film or the aluminum lower film and the molybdenum upper film.

The source electrode 65 overlaps at least a portion of the semiconductor layer 44 and the drain electrode 66 faces the source electrode 65 about the gate electrode 26 and overlaps with the semiconductor layer 44 at least partially do. The resistive contact layers 55 and 56 are present between the semiconductor layer 44 under the resistive contact layers 55 and 56 and the source electrode 65 and the drain electrode 66 above the semiconductor layer 44 and serve to lower the contact resistance.

The drain electrode extension 67 is formed to overlap with the pixel electrode 22 and a storage capacitor is formed with the pixel electrode 27 and the gate insulating film 30 interposed therebetween.

A protective film 70 is formed on the data lines 62, 65, 66, 67, and 68 and the semiconductor layer 44 not covered with these. The protective layer 70 may be formed of, for example, an a-Si: C: O, a-Si: Al, or a-Si: C formed by plasma chemical vapor deposition (PECVD) O: F, or silicon nitride (SiNx), which is an inorganic material. In order to prevent the organic material of the protective layer 70 from contacting the exposed portion of the semiconductor layer 44 between the source electrode 65 and the drain electrode 66 when the protective layer 70 is formed of an organic material, It may be formed by adding an insulating film (not shown) made of silicon nitride (SiNx) or silicon oxide (SiO ₂₎ on the lower organic layer.

Contact holes 77 and 78 exposing the drain electrode extension 67 and the data line end 68 are formed in the passivation layer 70. Gate lines 32 and 24 are formed in the passivation layer 70 and the gate insulating layer 30, The contact hole 74 is exposed. A pixel electrode 82 electrically connected to the drain electrode 66 through the contact hole 77 and located in the pixel is formed on the passivation layer 70. The pixel electrode 82 to which the data voltage is applied generates an electric field together with the common electrode of the upper panel to determine the arrangement of the liquid crystal molecules in the liquid crystal layer between the pixel electrode 82 and the common electrode.

An auxiliary gate end 84 and an auxiliary data end 88 connected to the gate end 24 and the data end 68 are formed on the protective film 70 through the contact holes 74 and 78, respectively. The pixel electrode 82, the assist gate, and the data ends 86 and 88 are made of ITO.

FIG. 9 is a layout view showing a thin film transistor array substrate according to a second embodiment of the present invention applied to the block diagram of FIG. 2, and FIG. 10 is a sectional view taken along a line IIa'-IIa "and IIb'- Fig.

The thin film transistor array substrate according to the second embodiment of the present invention includes the thin film transistor array substrate according to the first embodiment of the present invention except that it includes a separate storage electrode line 29 for forming the storage capacitor Cst1. (FIG. 1), the remaining portions except for the holding capacitor Cst1 will be omitted for convenience of explanation.

9 and 10, the storage capacitor Cst1 is formed by overlapping a separate storage electrode line 29 and a pixel electrode 82 provided on the thin film transistor array substrate 10, and the separate storage electrode lines 29 ), A separate wiring method in which a predetermined voltage such as the common voltage Vcom is applied is used.

The floating electrode 27 is formed on the same layer as the gate wiring 22, 24, 26 and 29 as shown in Fig. 10, has a floating state in which no electric field is applied, As shown in FIG. 9, the floating electrode 27 is formed so as to overlap at least a part of the data line 62 and the pixel electrode 82, and the first to third overlap capacitors Cid, Cif, Cdf ). 5, the first overlap capacitor Cid is formed between the pixel electrode 82 and the data line 62, and between the second overlap capacitor Cif pixel electrode 82 and the floating electrode 27 And a third overlap capacitor Cdf is formed between the data line 62 and the floating electrode 27, respectively. Since the capacitance of the capacitor varies depending on the area of the electrode and the distance between the electrodes, the area of the floating electrode 27 is increased to increase the capacitance of the third overlap capacitor 27 formed between the data line 62 and the floating electrode 27. [ (Cdf) can be increased.

When the capacitance of the third overlap capacitor Cdf is increased to increase the capacitance of the entire storage capacitor Cst, when one pixel is driven in the thin film transistor, the data voltage is applied to the pixel electrode during one frame (black state) , The storage capacitor Cst is charged, and the rate of discharging the charge to the storage capacitor Cst is increased when the data voltage is not applied to the pixel electrode in the next frame (white state). As a result, the response speed of the liquid crystal can be prevented from being delayed due to the cusp phenomenon occurring between the current frame and the next frame, thereby improving the response speed of the liquid crystal. Therefore, the same effect as in the first embodiment of the present invention can be obtained.

The floating electrode 27 may be formed in a polygonal pattern as shown in FIG. 9, or may be formed in a polygonal pattern in which at least a portion overlapping the data line is opened as in FIGS. 8A to 8H . The floating electrode 27 includes first and second electrodes 27a and 27b formed with a data line 62 sandwiched therebetween and the first and second electrodes 27a and 27b are connected to the data line 62. [ And at least a part of which is overlapped with the connection electrode 27c.

As shown in FIG. 6, a pixel electrode 82 may be formed on the floating electrode 27 to overlap the floating electrode 27 on at least a portion of the data line 62. 7, a pixel electrode 82 may be formed on the floating electrode 27 so that at least a portion of the pixel electrode 82 overlaps the floating electrode 27 on both sides with respect to the data line 62. Referring to FIG.

11 is a layout view showing a thin film transistor array substrate according to a third embodiment of the present invention, FIG. 12 is a cross-sectional view taken along line IIa'-IIa 'and IIb'-IIb' FIG. 15 is a view showing the arrangement of the data line and the pixel electrode of the thin film transistor array substrate according to the third embodiment of the present invention, and FIG. 15 is a view showing various variations of the floating electrode of the thin film transistor array substrate according to the third embodiment of the present invention Fig.

The thin film transistor array substrate according to the third embodiment of the present invention includes a pixel electrode 82 formed by overlapping the pixel electrode 82 with the immediately preceding gate line 28 via an insulator to form the storage capacitor Cst1, (Fig. 3) according to the first embodiment of the present invention, except that the shape of the floating electrode 27 is changed in accordance with the pattern shape of the data line 62 and the arrangement of the floating electrode 27 in the data line 62, Will be omitted for convenience of explanation.

11 and 12, the holding capacitor Cst1 uses a front gate method in which the pixel electrode 82 is superimposed on the front gate line 28 immediately above via an insulator. Here, since the pixels of the first row have no gate line at the previous stage, the storage capacitor gate line G0 of the first pixel row is added and the common voltage Vcom is applied to form the storage capacitor.

The pixel electrode 82 includes a first pixel electrode (not shown) and a second pixel electrode (not shown) separated by a cutout portion 83 formed along the data line 62. Here, the first pixel electrode and the second pixel electrode are electrically connected. A protrusion may be formed at the position of the cutout 83, and the cutout 83 or the protrusion may be referred to as a domain splitting means. The cutout portion 83 vertically divides the pixel region into approximately 1: 2 and forms approximately 45 degrees or -45 degrees with the gate line 22. [ At this time, the first pixel electrode may be formed on the right or left of the cutout 83, and preferably has a plurality of trapezoidal shapes. Here, it is preferable that the width of the cutout portion 83 is between 9 탆 and 12 탆. If the protrusion is formed instead of the cutout portion 83 by the domain dividing means, the width is preferably set to be between 5 탆 and 10 탆.

The data line 62 is formed so that the repeatedly bent portion and the vertically extending portion appear at intervals of the pixel length. At this time, the bent portion of the data line 62 is made up of two straight portions, one of which is at 45 degrees with respect to the gate line 22, and the other portion is connected to the gate line 22 -45 degrees. A source electrode 65 is connected to a vertically extending portion of the data line 62.

Here, the ratio of the length of the bent portion of the data line 62 to the length of the vertically extending portion is in a range of 1: 1 to 9: 1 (i.e., the ratio of the bent portion of the data line 62 is 50% to 90% ).

Therefore, the pixels formed by intersecting the gate line 22 and the data line 62 are formed in a bent band shape. In this manner, the data line 62 may be formed by a combination of a straight line and a bent band like a pixel, but the present invention is not limited thereto, and the data line 62 may be formed as a straight line or a bent band.

The floating electrode 27 is formed on the same layer as the gate wirings 22, 24, 26 and 28 as in FIG. 12, has a floating state in which no electric field is applied, Respectively. 11, the floating electrode 27 is formed so as to overlap at least a part of the data line 62 and the pixel electrode 82, and the first to third overlap capacitors Cid, Cif, Cdf ). 5, the first overlap capacitor Cid is formed between the pixel electrode 82 and the data line 62, and between the second overlap capacitor Cif pixel electrode 82 and the floating electrode 27 And a third overlap capacitor Cdf is formed between the data line 62 and the floating electrode 27, respectively. Since the capacitance of the capacitor varies depending on the area of the electrode and the distance between the electrodes, the area of the floating electrode 27 is increased to increase the capacitance of the third overlap capacitor 27 formed between the data line 62 and the floating electrode 27. [ (Cdf) can be increased.

When the capacitance of the third overlap capacitor Cdf is increased to increase the capacitance of the entire storage capacitor Cst, when one pixel is driven in the thin film transistor, the data voltage is applied to the pixel electrode during one frame (black state) , The storage capacitor Cst is charged, and the rate of discharging the charge to the storage capacitor Cst is increased when the data voltage is not applied to the pixel electrode in the next frame (white state). As a result, the response speed of the liquid crystal can be prevented from being delayed due to the cusp phenomenon occurring between the current frame and the next frame, thereby improving the response speed of the liquid crystal. Therefore, the same effect as in the first embodiment of the present invention can be obtained.

11, the floating electrode 27 may be formed in a polygonal pattern having a straight line and a bent band shape in the same manner as the data line 62. Also, as shown in FIGS. 15A to 15H, A portion overlapping with a data line having a shape can be formed in a polygonal pattern that is at least partially open. The floating electrode 27 includes first and second electrodes 27a and 27b formed with a data line 62 sandwiched therebetween and the first and second electrodes 27a and 27b are connected to the data line 62. [ And at least a part of which is overlapped with the connection electrode 27c.

13, a pixel electrode 82 may be formed on the floating electrode 27 to partially overlap the floating electrode 27 on one side of the data line 62. Referring to FIG. 14, a pixel electrode 82 may be formed on the floating electrode 27 so that at least a portion of the pixel electrode 82 overlaps with the floating electrode 27 on both sides of the data line 62. Referring to FIG.

FIG. 16 is a layout view showing a thin film transistor array substrate according to a fourth embodiment of the present invention, and FIG. 17 is a sectional view taken along line IIa'-IIa 'and IIb'-IIb' of FIG.

The thin film transistor array substrate according to the fourth embodiment of the present invention includes the thin film transistor array substrate according to the third embodiment of the present invention, except that it includes a separate storage electrode line 29 for forming the storage capacitor Cst1. (FIG. 11), so that the remaining parts except for the holding capacitor Cst1 will be omitted for convenience of explanation.

16 and 17, the storage capacitor Cst1 is formed by overlapping a separate storage electrode line 29 and a pixel electrode 82 provided on the thin film transistor array substrate 10, and the separate storage electrode lines 29 ), A separate wiring method in which a predetermined voltage such as the common voltage Vcom is applied is used.

The floating electrode 27 is formed on the same layer as the gate wirings 22, 24, 26 and 28 as shown in Fig. 17, has a floating state in which no electric field is applied, Respectively. 16, the floating electrode 27 is formed so as to overlap at least a part of the data line 62 and the pixel electrode 82, and the first to third overlap capacitors Cid, Cif, Cdf ). 5, the first overlap capacitor Cid is formed between the pixel electrode 82 and the data line 62, and between the second overlap capacitor Cif pixel electrode 82 and the floating electrode 27 And a third overlap capacitor Cdf is formed between the data line 62 and the floating electrode 27, respectively. Since the capacitance of the capacitor varies depending on the area of the electrode and the distance between the electrodes, the area of the floating electrode 27 is increased to increase the capacitance of the third overlap capacitor 27 formed between the data line 62 and the floating electrode 27. [ (Cdf) can be increased.

When the capacitance of the third overlap capacitor Cdf is increased to increase the capacitance of the entire storage capacitor Cst, when one pixel is driven in the thin film transistor, the data voltage is applied to the pixel electrode during one frame (black state) , The storage capacitor Cst is charged, and the rate of discharging the charge to the storage capacitor Cst is increased when the data voltage is not applied to the pixel electrode in the next frame (white state). As a result, the response speed of the liquid crystal can be prevented from being delayed due to the cusp phenomenon occurring between the current frame and the next frame, thereby improving the response speed of the liquid crystal. Therefore, the same effect as in the first embodiment of the present invention can be obtained.

The floating electrode 27 may be formed in a polygonal pattern as shown in FIG. 16, or may be formed in a polygonal pattern in which a portion overlapping the data line is at least partially open as in FIGS. 15A to 15H . The floating electrode 27 includes first and second electrodes 27a and 27b formed with a data line 62 sandwiched therebetween and the first and second electrodes 27a and 27b are connected to the data line 62. [ And at least a part of which is overlapped with the connection electrode 27c.

13, a pixel electrode 82 may be formed on the floating electrode 27 to partially overlap the floating electrode 27 on one side of the data line 62. Referring to FIG. 14, a pixel electrode 82 may be formed on the floating electrode 27 so that at least a portion of the pixel electrode 82 overlaps with the floating electrode 27 on both sides of the data line 62. Referring to FIG.

In addition, in the present invention, it is also possible to improve vertical lines caused by local deformation due to non-linearity of the exposure apparatus. That is, when the pixel electrode is moved and patterned by a predetermined distance due to a local deviation due to the nonlinearity of the aligner in forming the pixel electrode, the capacity of the overlap capacitor formed between the data line and the pixel electrode is increased to improve the vertical line.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

10: insulating substrate 22: gate line
24: gate line end 25: sustain electrode
26: gate electrode 27: floating electrode
28: gate line of the front stage 29: sustain electrode line
30: Gate insulating film 40: Semiconductor layer
50: resistance contact layer 62: data line
65: source electrode 66: drain electrode
68: data line end 74, 77, 78: contact hole
82: pixel electrode 83:
86: Auxiliary gate line end 88: Auxiliary data line end

Claims (21)

A gate wiring and a data wiring which are insulated from each other and intersected on an insulating substrate to define a pixel region;
At least two pixel electrodes;
A thin film transistor comprising a gate electrode, a source electrode, a source electrode, and a drain electrode, wherein the gate electrode is connected to the gate wiring, the source electrode is connected to the data electrode, At least one thin film transistor connected to one;
A drain electrode extension part extending from the drain electrode and overlapping at least a part of one of the pixel electrodes;
A capacitive electrode which is at least partially overlapped with the data line and is oriented parallel to the data line, a capacitive electrode overlapping with the at least two pixel electrodes and having no opening or slit opposed to the data line, electrode; And
At least a part of which is arranged in parallel with the gate wiring,
The capacitive electrode and the sustain electrode line are arranged on the same layer,
One of the at least two pixel electrodes is disposed adjacent to a first side of the data line and the other of the two pixel electrodes is connected to a second side of the data line that is the opposite side of the first side of the data line And is disposed adjacent to the side surface,
Wherein the sustain electrode line is completely overlapped with the drain electrode extension portion. The thin film transistor array substrate according to claim 1, wherein the gate electrode and the sustain electrode line are disposed on the same layer. 3. The method of claim 2,
Wherein the source electrode, the drain electrode, and the drain electrode extension are disposed on the same layer. The thin film transistor array substrate according to claim 3, further comprising a semiconductor layer disposed between the sustain electrode line and the drain electrode extension portion. delete delete delete delete The thin film transistor array substrate according to claim 1, wherein a contact hole is formed on the drain electrode extension portion. The thin film transistor array substrate according to claim 9, wherein a size of the drain electrode extension is larger than a size of the contact hole. The thin film transistor array substrate according to claim 1, wherein the drain electrode extension portion has a rectangular shape. delete delete delete delete delete The thin film transistor array substrate according to claim 1, further comprising a contact hole formed on the sustain electrode line. 18. The method of claim 17,
And the contact hole is also formed on the drain electrode extension portion. The thin film transistor array substrate of claim 18, wherein the drain electrode extension is larger than the contact hole. 2. The liquid crystal display device according to claim 1, wherein a width of a portion where the capacitive electrode overlaps with one of the at least two pixel electrodes, and a width of a portion where the capacitive electrode and the other of the at least two pixel electrodes overlap, Array substrate.
The thin film transistor array substrate according to claim 1, further comprising a resistive contact layer disposed between the data line and the capacitive electrode and having a width larger than the width of the data line.

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