KR100542769B1 - Liquid Crystal Display And Driving Method Thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a driving method thereof capable of improving luminance and reducing the number of data lines.

A liquid crystal display device according to the present invention comprises: a liquid crystal display panel comprising first and second subpixels connected to an odd gate line and third and fourth subpixels connected to an even gate line; A gate driver for dividing one frame period into an odd subframe and an even subframe, driving the odd gate line during the odd subframe, and driving the even gate line during the even subframe; Supplying first color data to the first subpixel during the odd subframe and supplying second color data to the second subpixel, and data of third color to the third subpixel during the even subframe. And a data driver for supplying data of a fourth color to the fourth sub-pixel.

Description

Liquid Crystal Display And Driving Method Thereof             

1 is a block diagram showing a conventional liquid crystal display device.

2 is a block diagram illustrating a liquid crystal display according to the present invention.

FIG. 3 is a detailed block diagram illustrating the timing controller illustrated in FIG. 2.

4 is a waveform diagram illustrating driving waveforms of gate lines illustrated in FIG. 2.

FIG. 5 is a waveform diagram illustrating pixel voltages charged in the liquid crystal cell of FIG. 2.

          <Explanation of symbols for the main parts of the drawings>

2,52: Timing controller 4,54: Data driver

6,70 gate driver 8,58 liquid crystal panel

10,60: pixel electrode 12,62: thin film transistor

72: selection unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof capable of improving luminance and reducing the number of data lines.

A typical liquid crystal display device displays an image corresponding to a video signal using a pixel matrix arranged at an intersection between gate lines and data lines. Each pixel includes a thin film transistor ("TFT") for switching a video signal to be supplied to the liquid crystal cell from the data line, and a gate so that the video signal supplied from the data line can be supplied to the liquid crystal cell. It is composed of a gate line for supplying a drive signal. Further, in the liquid crystal display device, gate and data driving circuits (not shown) for supplying driving signals to the gate lines and the data lines are provided.

Referring to FIG. 1, a conventional liquid crystal display device includes a liquid crystal panel 8 having a liquid crystal cell matrix, a gate driver 6 for driving gate lines GL1 to GLn of the liquid crystal panel 8, and a liquid crystal panel. A data driver 4 for driving the data lines DL1 to DLm of (8), and a timing controller 2 for controlling the gate driver 6 and the data driver 4 are provided.

The timing controller 2 generates control signals GDC and DDC for controlling the gate driver 6 and the data driver 4, and supplies the pixel data signals R, G, and B to the data driver 4. do. The gate control signals GDC generated by the timing controller 2 include a gate start pulse GSP, a gate shift clock signal GSC, a gate output enable signal GOE, and the like. The data control signals DDC generated by the timing controller 2 include a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, a polarity control signal POL, and the like. .

The gate driver 6 sequentially supplies scan signals to the gate lines GL1 to GLn using the gate control signals GDC. Accordingly, the gate driver 6 causes the thin film transistors 12 to be driven in units of horizontal lines in response to the scan signal.

The data driver 4 converts the input pixel data into an analog pixel signal and supplies one horizontal line of pixel signals to the data lines DL1 through DLm every one horizontal period in which the scan signal is supplied to the gate line GL. do. In this case, the data driver 4 converts the pixel data into the pixel signal using gamma voltages supplied from the gamma voltage generator (not shown).

The liquid crystal panel 8 includes an upper array substrate and a lower array substrate facing each other with the liquid crystal layer interposed therebetween.

The upper array substrate includes red, green, and blue color filters, a black matrix positioned between the color filters, and a common electrode for supplying a reference voltage to the liquid crystal layer.

The lower array substrate includes a thin film transistor 12 formed in each sub pixel region defined by the intersection of the gate lines GL1 to GLn and the data lines DL1 to DLm, and the pixel electrode 10 connected to the thin film transistor. . The thin film transistor 12 supplies the pixel electrodes 10 from the data lines DL1 to DLm in response to the scan signals from the gate lines GL1 to GLn. The pixel electrode 10 drives the liquid crystal positioned between the common electrode (not shown) in response to the pixel signal to adjust the transmittance of light to implement the color of the color filter.

In the conventional LCD, one pixel is represented by a combination of sub-pixels implementing red (R), green (G), and blue (B) arranged side by side. In order to supply a corresponding data signal to each sub-pixel, the data drive IC of the data driver 4 needs an output terminal as many as the number of data lines DL. In addition, as the number of data lines DL increases, the number of data drive ICs increases, leading to an increase in manufacturing cost. Accordingly, there is an urgent need to develop a liquid crystal display device capable of reducing the number of data drive ICs by reducing the number of data lines.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of improving luminance and reducing the number of data lines.

In order to achieve the above object, a liquid crystal display device according to the present invention includes a liquid crystal display panel including first and second subpixels connected to the odd gate line, and third and fourth subpixels connected to the even gate line; A gate driver for dividing one frame period into an odd subframe and an even subframe, driving the odd gate line during the odd subframe, and driving the even gate line during the even subframe; Supplying first color data to the first subpixel during the odd subframe and supplying second color data to the second subpixel, and data of third color to the third subpixel during the even subframe. And a data driver for supplying data of a fourth color to the fourth sub-pixel.
The liquid crystal display includes a selector connected to an output terminal of the gate driver to select the odd gate line and the even gate line for each subframe; A timing controller for controlling the gate driver and the data driver is further provided.
The selector selects the odd gate line and the even gate line in response to the control signal generated by the timing controller.
The control signal is a gate output enable signal.
The selection unit is located in a pad portion of the liquid crystal display panel.
The selector is formed embedded in the gate driver.
The first subpixel implements any one color among red, green, blue, and white, the second subpixel implements any one of the remaining three colors, and the third subpixel implements one of the remaining two colors. The fourth sub-pixel implements the other color.
The method of driving the liquid crystal display device comprises: dividing one frame period into an odd subframe and an even subframe; Supplying a first scan signal to an odd gate line connected to first and second subpixels during an odd subframe; Supplying data of a first color to the first subpixel and simultaneously supplying data of a second color to the second subpixel so as to be synchronized with the first scan signal; Supplying a second scan signal to the even gate line connected to the third and fourth subpixels during the even subframe; And supplying data of a third color to the fourth subpixel while simultaneously supplying data of a third color to the third subpixel so as to be synchronized with the second scan signal.
Other objects and features of the present invention in addition to the above object will become apparent from the description of the accompanying examples.

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Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 2 to 5.

2 is a view showing a liquid crystal display device according to the present invention.

Referring to FIG. 2, a liquid crystal display according to the present invention includes a liquid crystal display panel 58 having a liquid crystal cell matrix and a gate driver 70 for driving gate lines GL1 to GLn of the liquid crystal display panel 58. ), A data driver 54 for driving the data lines DL1 to DLk of the liquid crystal display panel 58, a timing controller 52 for controlling the gate driver 70 and the data driver 54, and And a selector 72 for selecting the gate line GL for each subframe.

The liquid crystal display panel 58 includes a thin film transistor 62 formed at each region defined by the intersection of the gate lines GL1 to GLn and the data lines DL1 to DLk, and a liquid crystal cell including the pixel electrode 60. do. The thin film transistor 62 supplies the pixel signal from the data lines DL1 to DLk to the pixel electrode 60 in response to the scan signal from the gate line GL. The pixel electrode 60 adjusts the light transmittance by driving a liquid crystal positioned between the common electrode (not shown) in response to the pixel signal.

Each pixel of the liquid crystal display panel has a quad structure consisting of R, G, B, and W subpixels. As a result, the luminance is relatively higher than that of the conventional R, G, and B subpixels. In detail, each of the R, G, and B subpixels has only about 27 to 33% of the light emitted from the upper substrate through the color filter when the amount of light emitted from the backlight unit is 100%. On the other hand, among the R, G, B, and W sub-pixels, the W sub-pixels emit more than 95% of the light emitted from the upper substrate through the transparent color filter when the amount of light emitted from the backlight unit is 100%. Accordingly, the luminance deteriorated due to the R, G, and B subpixels can be compensated for, so that the luminance of the liquid crystal display panel consisting of the R, G, B, and W subpixels is higher than that of the R, G, B subpixels Is improved.

As shown in FIG. 3, the timing controller 52 controls the frame memory 80 and the pixel data aligner 82, the gate driver 70, and the data driver 54 to align the pixel data RGBW. The control signal generator 84 generates control signals GDC and DDC.

The frame memory 80 stores and outputs pixel data RGBW input from the outside in units of frames.

The pixel data aligning unit 82 separates the pixel data RGBW from the frame memory 80 into odd pixel data RG and even pixel data BW, and sequentially outputs them. For example, the pixel data alignment unit 82 outputs odd pixel data RG among the pixel data RGBW for one frame, and then outputs even pixel data BW. That is, the pixel data alignment unit 82 supplies odd pixel data, that is, red and green pixel data RG, to the data line DL connected to the odd gate lines GL1, GL3, GL5... Even pixel data, that is, blue and white pixel data BW is supplied to the data line DL connected to the even-numbered gate line GL2, GL4, GL6.

The control signal generator 84 determines a transmission timing of the data enable signal DE, the horizontal sync signal H, the vertical sync signal V, and the pixel data RGBW informing the valid data section input from the outside. The gate clock signal GDC and the data control signal DDC are generated using the dot clock DCLK. The gate control signals GDC include a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, and the data control signals DDC include a source start pulse SSP, The source shift clock SSC, the source output enable signal SOE, the polarity control signal POL, and the like.

The gate driver 70 shifts the gate start pulse GSP according to the gate shift clock GSC to generate a scan pulse of the gate high voltage. In particular, the gate driver 70 separates and drives the gate line GL of the liquid crystal display panel into the odd gate line and the even gate lines. For example, the gate driver 70 supplies gate high voltage scan pulses to the odd gate lines during the odd subframe period in response to the gate output enable (GOE) signal, and the even gate lines during the even subframe period. The scan pulse of the gate high voltage is supplied. The gate driver 70 supplies the gate low voltage to the gate lines GL1 through GLn during the remaining periods in which the gate high voltage is not supplied.

The selector 72 is positioned between the gate driver 70 and the gate line GL to select the corresponding gate line GL for each subframe. That is, the selector 72 is positioned at the output terminal of the gate driver 70 or the pad unit of the liquid crystal display panel 58. The selector 72 selects the odd gate line in the odd subframe and the even gate line in the even subframe in response to the gate output enable signal GOE.

To this end, the scan pulse is supplied to the 3n (n is a natural number) -2 gate line GL1, GL4, GL7 .... by the first gate output enable signal GOE1, as shown in FIG. The scan pulse is supplied to the 3n-1 gate lines GL2, GL5, GL8... By the second gate output enable signal GOE2, and the scan pulse is supplied by the third gate output enable signal GOE3. The scan pulse is supplied to the 3n gate lines GL3, GL6, and GL9.

Alternatively, in response to the selection control signal CS generated by the timing controller 52, the selector 72 selects the odd gate line in the odd subframe, and selects the even gate line in the even subframe.

The data driver 54 converts the input pixel data into an analog pixel signal and supplies one horizontal line of pixel signals to the data lines DL1 through DLk every one horizontal period in which the scan signal is supplied to the gate line GL. do. In this case, the data driver 54 converts the pixel data into the pixel signal using gamma voltages supplied from the gamma voltage generator (not shown).

In detail, the data driver 54 converts pixel data of odd horizontal lines into an analog pixel signal when the odd gate lines are driven, and supplies pixel data of even horizontal lines when the even gate lines are driven. It is converted into an analog pixel signal and supplied.

As described above, in the liquid crystal display according to the present invention, as shown in FIG. 4, the odd gate lines are sequentially driven in the odd subframe SFO during each frame F, and then the even gate line in the even subframe SFE. Are driven sequentially.

When the odd gate lines selected by the selector 72 are driven in the odd subframe SFO, the data driver 54 performs the odd data lines DL1, DL3, DL5 ... at 30 Hz as shown in FIG. R pixel data is supplied to the G pixel data, and G pixel data is supplied to the even data lines DL2, DL4, DL6 .... The R and G pixel data supplied to each liquid crystal cell in the odd subframe SFO are held up to the even subframe SFE of the corresponding frame.

Then, when the even gate lines selected by the selector 72 are driven in the even subframe SFE, the data driver 54 performs W pixel data on the odd data lines DL1, DL3, DL5 ... at 30 Hz. Is supplied to the even data lines DL2, DL4, DL6 .... During this even subframe SFE, the W and B pixel data supplied to each liquid crystal cell are held up to the odd subframe SFO of the next frame. That is, when the pixel voltage charged in the liquid crystal cell of the odd subframe SFO discharges, the pixel voltage starts to be charged in the liquid crystal cell of the even subframe SFE of the frame, and the liquid crystal cell of the even subframe SFE. When the charged pixel voltage is discharged, the pixel voltage starts to be charged in the liquid crystal cell of the odd subframe (SFO) of the next frame, thereby preventing the voltage variation of the pixel voltage and preventing flicker.

As described above, the liquid crystal display and the driving method thereof according to the present invention supply RG data to the first and second sub-pixels connected to the odd gate line selected in the odd sub-frame among the one frame, and select the good sub-frame. The BW data is supplied to the third and fourth subpixels connected to the even gate line, respectively. That is, by supplying two data lines to one data line, the number of data lines can be reduced by half, thereby reducing the number of data driving units. In addition, by reducing the number of data lines in half to reduce the frequency can reduce the EMI caused by the data. Furthermore, power consumption can be reduced.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (14)

A liquid crystal display panel including first and second subpixels connected to the odd gate line and third and fourth subpixels connected to the even gate line; A gate driver for dividing one frame period into an odd subframe and an even subframe, driving the odd gate line during the odd subframe, and driving the even gate line during the even subframe; Supplying first color data to the first subpixel during the odd subframe and supplying second color data to the second subpixel, and data of third color to the third subpixel during the even subframe. And a data driver for supplying data of a fourth color to the fourth sub-pixel at the same time. delete The method of claim 1, A selector connected to an output terminal of the gate driver to select the odd gate line and the even gate line for each subframe; And a timing controller for controlling the gate driver and the data driver. The method of claim 3, wherein And the selector selects the odd gate line and the even gate line in response to a control signal generated by the timing controller. The method of claim 4, wherein And the control signal is a gate output enable signal. The method of claim 3, wherein And the selector is located at a pad of the liquid crystal display panel. The method of claim 3, wherein And the selector is formed in the gate driver. delete The method of claim 1, The first subpixel implements any one color among red, green, blue, and white, the second subpixel implements any one of the remaining three colors, and the third subpixel implements one of the remaining two colors. And the fourth sub-pixel implements the other color. Dividing one frame period into an odd subframe and an even subframe; Supplying a first scan signal to an odd gate line connected to first and second subpixels during an odd subframe; Supplying data of a first color to the first subpixel and simultaneously supplying data of a second color to the second subpixel so as to be synchronized with the first scan signal; Supplying a second scan signal to the even gate line connected to the third and fourth subpixels during the even subframe; And supplying data of a third color to the fourth subpixel while simultaneously supplying data of a third color to the third subpixel to be synchronized with the second scan signal. Way. delete delete delete The method of claim 10, The first subpixel implements any one color among red, green, blue, and white, the second subpixel implements any one of the remaining three colors, and the third subpixel implements one of the remaining two colors. And the fourth sub-pixel implements the other color.

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