JPS6447090U - - Google Patents
Info
- Publication number
- JPS6447090U JPS6447090U JP14176787U JP14176787U JPS6447090U JP S6447090 U JPS6447090 U JP S6447090U JP 14176787 U JP14176787 U JP 14176787U JP 14176787 U JP14176787 U JP 14176787U JP S6447090 U JPS6447090 U JP S6447090U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- electronic components
- laminated circuit
- substrates
- laminated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 4
- 230000004308 accommodation Effects 0.000 description 1
Description
第１図は本考案の一実施例としての積層回路基
板の一部を断面した斜視図、第２図は前記積層回
路基板の断面図、第３図及び第４図は従来例とし
ての積層回路基板の断面図である。
１……積層回路基板、２〜５……グリーンシー
ト、４ａ……収容部、６……電子部品。
FIG. 1 is a partially sectional perspective view of a laminated circuit board as an embodiment of the present invention, FIG. 2 is a sectional view of the laminated circuit board, and FIGS. 3 and 4 are conventional laminated circuits. FIG. 3 is a cross-sectional view of the substrate. DESCRIPTION OF SYMBOLS 1... Laminated circuit board, 2-5... Green sheet, 4a... Accommodation part, 6... Electronic component.
Claims (1)
接続されて回路を構成する積層回路基板において
、 前記電子部品が、電子部品と同じ厚さを有する
基板に設けられた収容部に収容されていることを
特徴とする積層回路基板。[Claims for Utility Model Registration] In a laminated circuit board in which a plurality of substrates are stacked and electronic components are connected to the substrates to form a circuit, the electronic components are provided on a substrate having the same thickness as the electronic components. A laminated circuit board, characterized in that the laminated circuit board is housed in a housing section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14176787U JPS6447090U (en) | 1987-09-17 | 1987-09-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14176787U JPS6447090U (en) | 1987-09-17 | 1987-09-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6447090U true JPS6447090U (en) | 1989-03-23 |
Family
ID=31407126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14176787U Pending JPS6447090U (en) | 1987-09-17 | 1987-09-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6447090U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7169646B2 (en) | 1998-07-13 | 2007-01-30 | Formfactor, Inc. | Interconnect assemblies and methods |
| US7482822B2 (en) | 2002-12-16 | 2009-01-27 | Formfactor, Inc. | Apparatus and method for limiting over travel in a probe card assembly |
-
1987
- 1987-09-17 JP JP14176787U patent/JPS6447090U/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7169646B2 (en) | 1998-07-13 | 2007-01-30 | Formfactor, Inc. | Interconnect assemblies and methods |
| US7618281B2 (en) | 1998-07-13 | 2009-11-17 | Formfactor, Inc. | Interconnect assemblies and methods |
| US7482822B2 (en) | 2002-12-16 | 2009-01-27 | Formfactor, Inc. | Apparatus and method for limiting over travel in a probe card assembly |
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