JPS63236325A - Formation of fine pattern in semiconductor element - Google Patents

Abstract

PURPOSE:To prevent production of an interlayer, by forming a first polymeric intermediate layer soluble in a solvent having no dissolubility to a lower resist between upper and lower resist layers, and then forming a second polymeric intermediate layer soluble in a solvent having no dissolubility to the first intermediate layer. CONSTITUTION:A lower resist layer 12 of chloromethylated polystyrene (CMS) is formed on an underlying substrate 11 and is heated to provide a CMS thin film. A PVA thin film is formed by means of an aqueous solution of PVA and is heated to provide an intermediate layer 13. Subsequently, polysturene (PSt) or PMMA soluble in xylene is applied and heated to provide an intermediate layer 14. Positive resist is applied to provide an upper resist layer 15. The upper positive resist layer 15 masked with a mask 16 is patterned by means of UV light. Using this upper resist pattern 15 as a mask, the subject pattern is transferred to the lower resist layer of CMS by means of DUV light. The upper positive resist 15 and the intermediate PST layer 13 are removed. Then, a solvent is volatilized and water is supplied to dissolve and remove the PVA film, The lower resist 12 is then developed. In this manner, the lower resist can he prevented from being reduced in volume or from being deteriorated in configurations.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for forming fine patterns in semiconductor devices such as ICs (integrated circuits) and LSIs (large scale integrated circuits).

(Prior art) Regarding the formation of fine Rennost patterns, see Oki Electric Research and Development, January 1988, No. 133, Vo154, Nll.
, pages 85-86, Takashi Taguchi and Takayuki Matsui [Pattern Formation Technology in the Saramicron Area], a new resist process that supports submicron pattern formation (reactive ino etching (RIE) development method using Freon gas) (RIEZ layer processing).

As a method for forming fine patterns in IC and LSI,
There is a multilayer resist method. This method uses a structure in which different types of resists are layered, and uses the effect of the lower layer resist to flatten the base substrate or reduce reflection, and increases the resolution in pattern formation of the upper layer resist, thereby increasing the fineness and fineness.
This is a technique that allows for the formation of 6 turns.

The multilayer resist method involves transferring the upper resist pattern to the lower resist, and DUV (Deep Ul).
tra Violet, far ultraviolet) light batch exposure method and RIE
There is a law.

The RIE method is a method in which an upper layer resist pattern is transferred to a lower layer resist by RIE.

In the DUV batch exposure method, a resist having photosensitivity to the DUV source is used as the lower resist, and a pattern of the upper layer Renost is transferred to the lower resist by batch exposure with DUV light using the upper resist pattern as a mask.

FIG. 2 is a process explanatory diagram of a typical example of a method for forming fine grains in a semiconductor device by a two-layer resist method using a one-shot exposure method using DUV light. The example shown here is D
This is a two-layer soaking process using the EAP method, in which the upper resist layer is exposed even after the lower resist layer is developed using a UV light exposure method.

Also, this is an example of a two-layer bottling process in which a bottling resist for UV light is used for the upper resist layer, and a bottling resist for DUV light is used for the lower resist layer.

First, on the Si substrate 1 shown in FIG. 2(aJ),
After forming a lower resist 2 as shown in ), an upper resist 3 is formed thereon as shown in FIG. 2(c).

Next, as shown in FIG. 2 (dl), use the mask 5 to
By photolithography using V light 6, a pattern of the upper resist 3 is formed as shown in FIG. 2(e).

Next, the interlayer 40 portion generated at the interface between the upper resist layer 3 and the lower resist layer 2 is removed by oxygen plasma or isodirectional development as shown in FIG. 2 (fJ).

Next, as shown in FIG. 2e)K, the pattern of the upper resist 3 is transferred to the lower resist 2 by the DUV batch exposure method using the pattern of the upper resist 3 as a mask.

Next, as shown in FIG. 2(h), the lower resist 2 is developed to obtain a final resist pattern.

(Problems to be Solved by the Invention) However, in the above process, the interlayer 4 generated at the interface between the upper layer resist 3 and the lower layer resist 2 makes it difficult to form fine patterns for the reasons described below. Ta.

That is, in the process shown in Figure 2,
When removing the interlayer 4, deterioration of the upper resist pattern or thinning of the lower resist 2 occurs, making it impossible to secure the shape of the upper resist 3 or the remaining film of the lower resist 2 necessary for fine pattern formation.

In addition, in order to avoid the above-mentioned adverse effects, if the lower resist 2 is exposed and imaged without removing the interlayer 4, the lower resist 2 may swell in the interlayer 3 portion or the development rate of the interlayer 4 may increase. Regardless of the difference between 2 and 2,
This results in deterioration of the shape after the formation of the lower resist, making it difficult to form a slightly fine pattern.

This invention solves the problems of the prior art described above, such as the inability to secure the shape of the upper resist or the remaining film of the lower resist necessary for fine pattern formation, and the exposure of the lower resist without removing the interlayer. The present invention provides a method for forming a fine pattern in a semiconductor device, which solves the problem of deterioration of the shape after forming a lower layer when developing.

(Means for Solving the Problems) The present invention provides a method for forming fine patterns in semiconductor devices, in which a negative type resist or a bottom type resist against deep ultraviolet light is used to improve the solubility of the lower resist after forming the lower resist. forming a first intermediate layer made of a polymer film that is soluble in a solvent that has no solubility; a step of forming a second intermediate layer made of a polymer film;
This method introduces a step of forming an upper layer resist on the intermediate layer using a blot resist that is resistant to ultraviolet light.

(Function) According to the present invention, since the above steps are introduced into the method for forming fine patterns in semiconductor devices, two intermediate layers are interposed between the upper resist layer and the lower resist layer, and the upper resist layer and the lower layer resist This prevents the formation of an interlayer at the interface with the resist layer, eliminates the need for a step of removing the interlayer in a subsequent process, and suppresses film thinning or shape deterioration of the underlying resist.

(Example) Hereinafter, an example of the method for forming a fine pattern in a semiconductor device of the present invention will be described based on the drawings.

In this case, the lower layer resist is chloromethylated polystyrene (hereinafter referred to as CM
The method will be explained by taking as an example a method in which a UV light-resistant bollard resist (novolak resin bollard resist) is used as the upper layer resist.

First, as shown in FIG. 1(a), a lower resist 1200MS film is formed on the base substrate 11 by a spin coating method.
It is heated at 90° C. to 130° C. on a hot plate or in an open air to obtain an OMS thin film with a thickness of 0.5 to 2.0 μm.

Next, as shown in FIG. 1(b), using an aqueous solution of polyvinyl alcohol (hereinafter referred to as PVA), which is a water-soluble polymer, a spin coating method was applied. A thin film of 0PVA is formed.

Next, heat at a temperature of 80°C to 110°C, and
A first intermediate layer 13 made of a PVA thin film of approximately 0A is obtained.

Next, as shown in FIG. (hereinafter referred to as PSt) will be described as an example, but it does not necessarily have to be PSt, and may be any one that satisfies the following conditions.

Fi+ Soluble in any organic solvent such as xylene, methyl ethyl ketone, or acetate.

Difficult to crosslink or no crosslinking with +21 DUV light.

(3) Difficult to dissolve in ethylcellosolve acetate, the solvent for Borresist.

(4) A uniform coating film can be formed using the spin coating method.

Next, after forming a PSt film by spin coating method,
Heating at a temperature of 10°C, 1000-3000X PS
A second intermediate layer 14 of a thin film is obtained.

Next, as shown in FIG. 1(d), an upper layer resist 15 is formed by applying a bore resist thereon by a spin coating method.

In the above coating process, the CMS of the lower resist 12
In coating, surface treatment such as HMDS treatment may be necessary in order to increase adhesion to the underlying substrate 11. However, when applying the upper resist 15, surface treatment with a saturated hydrocarbon such as heptane may be necessary to suppress the formation of an interlayer with PST.

Next, as shown in FIG. 1(e), the upper layer resist 15 is formed by lithography using UV light using a mask 16.
Turning the bore resist.

That is, a mask pattern is transferred to a bore resist using UV light, and a pattern as shown in FIG. 1(f) is obtained by alkaline development.

Next, as shown in FIG. 1 (gl), using the bore resist pattern of the upper resist 15 as a mask, the bore resist pattern of the upper resist 15 is exposed as shown in FIG. Lower Resos) 12 C
Transfer to MS. The exposure conditions in this case are, for example, as follows.

When light of 200 to 250 μm is used as a DUV source, CMS with a chloromethylation rate of 15% is used for the lower resist 12, CM 81.0 μs, PVA
0.1 am, PSto, 3 μm, Borresist 1.
With a combination of 2 μm, the exposure amount of DUV light is 500 to 300
In the range of 0 mJ/cfn'', the CMS masking property of the lower resist 12 of the bore resist is sufficient, and CMS pattern formation is also possible within this range.

Next, the positive resist first intermediate layer 1 of the upper resist 15 is
3, PSt is removed. In this case, in order to ensure reliable removal, use a solvent that has strong solubility in Borlenost of pst and upper resist 15, such as xylene or MEK.
(Methyl ethyl Kent) etc. are used. PVA is not removed by this process as it is not soluble in most organic solvents.

The removal method is carried out by spray development or dipping, in which a solvent is supplied to the surface for about 30 to 90 seconds.

Then spin dry or N! Evaporate the solvent by spraying or other methods.

Next, water is supplied to the PVA surface to dissolve and remove the PVA film. The removal method is carried out for 30 to 60 seconds using a static nozzle or a method of continuously supplying water to the surface.

Next, as shown in FIG. 1(i), the lower resist 12 is developed. In this case, pre-wetting (operation of substituting water molecules on the surface with these organic solvents) using isopropyl alcohol or ethylceranulpacetate may be necessary in order to remove water on the surface.

The lower resist 12 may be developed in accordance with the method used for negative-type resists as a single-layer resist method.

This is because in this case, since the interlayer does not exist above the CMS of the lower resist 12, it can be considered to be the same as turning of a single layer resist.

That is, the film is developed by dip or spray development using an organic solvent of an appropriate concentration (acetate is suitable in the case of cMS).

(Effects of the Invention) As described in detail above, according to the present invention, a polymer film soluble in a noisy solvent that is soluble in the lower resist layer is formed between the lower resist layer and the upper layer resist layer. After forming the first intermediate layer, a second intermediate layer of a polymer film that is soluble in a solvent that has no solubility in the first intermediate layer is formed on it, so that the upper resist layer and the lower resist layer are It is possible to create a multilayer resist structure in which no interlayer is formed between the resists, which eliminates the difficulty of forming fine patterns that have hitherto been caused by the formation of interlayers, and also improves the shape after forming the lower layer. Deterioration can be prevented.

[Brief explanation of the drawing]

1(a) to 1(i) are process explanatory diagrams of an embodiment of the method for forming a fine pattern in a semiconductor device according to the present invention, and FIGS. FIG. 3 is a process explanatory diagram of a method for forming a fine pattern in a semiconductor element. 11... Base substrate, 12... Lower layer resist, 13.
...first intermediate layer, 14...second intermediate layer, 15...upper layer resist, 16...mask. Figure 1 Figure 2

Claims (1)

[Scope of Claims] (a) After forming a lower layer resist of a positive resist or a negative resist against deep ultraviolet light on a base substrate, a first layer of a polymer film soluble in a solvent having no solubility in this lower layer resist is formed.
(b) forming a second intermediate layer of a polymer film soluble in a solvent that has no solubility with respect to the first intermediate layer on the first intermediate layer; (c) forming an upper resist of positive resist on the second intermediate layer and forming a pattern of the upper resist by exposure and development with ultraviolet light; (d) using the pattern of the upper resist as a mask and exposing it to deep ultraviolet light. A method for forming a fine pattern in a semiconductor device, comprising the steps of: exposing a lower resist to light using a photolithography method, then sequentially removing the upper resist, a second intermediate layer, and the second intermediate layer and developing the lower resist.