JPS6313516A - Phase comparator - Google Patents

Abstract

PURPOSE:To reduce the time required for synchronization by starting the phase comparison synchronously with the leading or trailing edge of a signal whose phase differs from that of a signal being object of phase comparison by nearly a half period. CONSTITUTION:A signal D is formed by the AND of the inverse of an oscillation signal A of a VCO and its 1/2 frequency division signal B and a signal C is formed by the inner of OR of a signal A and a signal B. With an operation start signal E given at a high level, the inverse of an output signal Q of a flip-flop circuit DFF 3 goes to a low level synchronously with the leading of the signal D, a signal X1 coming earlier is given to a clock terminal CK of the flip-flop circuit DFF1 and the output signal Q goes to a high level. The signal C coming later is given to a clock terminal CK of a flip-flop circuit DFF2 and the output signal Q goes to a high level, then the output signal of a NAND gate circuit G3 goes to a low level. Then the flip-flop circuits DFF1, DFF2 are cleared to form an UP signal UP according to the phase difference between the signals X and C.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a phase comparison circuit, for example, a VFO (variable frequency oscillator) in a floppy desk control device.
It is related to effective technology that can be used for.

[Conventional technology]

In a floppy desk memory device, etc., the read signal contains data and a clock signal.
For example, a semiconductor integrated circuit device for controlling a magnetic disk having such a VFO, which has a data separation VFO for separating the data, is - NEC, 1985
Published in rNEc Device Chiklodge-jlkg, page 21
~ There are 30 pages.

[Problem that the invention seeks to solve]

The phase comparison circuit included in the above-mentioned VFO starts the phase comparison operation when it is activated. Therefore, as shown in the timing chart shown in FIG. 4, if the phase comparison operation is started at time T1, for example, the up signal U according to the phase difference between the signal X1 and the signal C1
This will form P. On the other hand, even if the phase relationship between the two signals X and C is the same, if the phase comparison operation is started at time 1゛2, a down signal DW will be formed according to the phase difference between the signals C1 and X2. Put it away like this,
In conventional VFOs, the phase comparison operation is started asynchronously with respect to the reference signal X and the signal C whose phase should be controlled based on a voltage-controlled oscillator circuit, etc., so there is only a minute phase difference. Even in this case, it is considered that there is a phase difference of about one cycle depending on the timing of starting the phase comparison operation. Therefore, the time required to synchronize both signals X and C becomes longer.

An object of the present invention is to provide a phase comparator circuit that achieves high-speed synchronous operation.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, first and second pulse signals whose phases are approximately half a period are formed based on the oscillation frequency signal of the voltage controlled oscillation circuit, and the first pulse signal and the reference signal are combined. The second control signal for starting the phase comparison operation is
The pulse signal is generated in synchronization with the rising or falling edge of the pulse signal.

[For production]

According to the above-mentioned means, the phase comparison operation with the reference frequency is performed for the first pulse within a phase difference of about half a cycle at most, so the time required to synchronize both signals can be shortened. .

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a phase comparator circuit according to the present invention. Each circuit block in the same figure is
Although not particularly limited, it is formed, for example, on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The phase comparison circuit of this embodiment is broadly divided into a phase comparison section and an operation control signal synchronization circuit.

The phase comparator includes the following flip-flop circuits DFF1 and D
It is composed of an FF2 and a NAND gate circuit G3. That is, the flip-flop circuit DFF
1 and DFF2 are edge trigger type D-type flip-flop circuits, and their data terminals are connected to a high level (logic "1") such as the power supply voltage Vcc through a resistor R.
) is constantly supplied. The output signals sent from the output terminals Q of the flip-flop circuits DFFI and DFF2 are supplied to the Nant gate circuit G3. The output signal of this Nant gate circuit G3 is the flip-flop circuit DFF1. DFF2 clear (reset) terminal CLR
supplied to These flip-flop circuits DFFI
and DFF2 are reset when the signal of the clear terminal CLH is set to low level (logic "0").

The clock terminal CK of the flip-flop circuits DFFI and DFF2 is connected to a NOR gate circuit G1. The reference signal X and the signal C to be phase controlled are supplied via G2 and inverter circuits Nl and N2, respectively. Each of the flip-flop circuits DFFI and DFF2 takes in a signal from a data terminal in synchronization with the timing (edge) when the signal from the clock terminal CK changes from a low level to a high level, in other words, the signal from an output terminal Q. from low level to high level. An up signal UP and a down signal DW are output from the output terminals Q of the flip-flop circuits DFFj and DFF2, respectively.

The synchronization circuit is composed of the following circuits.

A high level as shown in "2" is constantly supplied to the data terminal of the flip-flop circuit DFF3 similar to the above. The clock terminal CK is supplied with a signal l) having the same frequency as the signal C but having a phase different by π (half period). Further, the operation start signal E is supplied to the clear terminal CLR. And the inverted output terminal Q
A control signal 11 is formed which is synchronized with the above-mentioned signal. This control signal is supplied to NOR gate circuits Gl and 02 which receive the reference signal X and signal C.

Figure 2 shows a VFO (P
A block diagram showing an embodiment of the LL circuit (phase locked loop circuit) is shown.

The up signal U of the phase comparator circuit PFC shown in Fig. 1 above
P and the down signal DW are supplied to a loop filter LPF. The loop filter LPF performs an integral operation on the up signal UP and the down signal DW, forms a control voltage VC, and supplies the control voltage VC to the control terminal of the voltage controlled oscillator circuit ■CO. The oscillation signal A of this voltage-controlled oscillator circuit VCO is supplied to the frequency divider circuit DV on the one hand to form signals C and D whose phases are made to differ by the above-mentioned half cycle, where the frequency is reduced to 1/2. It is converted into a signal B whose frequency is divided into .

The signal A and the frequency-divided output B are supplied to a NOR gate circuit G4, and the signal C is generated from its output terminal. Further, the output signal of the inverter circuit N3 receiving the signal A and the frequency-divided output B are supplied to the Nant gate circuit G5. The output signal of this Nant gate circuit G5 is supplied to the input of an inverter circuit N4, and the above signal is formed from its output terminal.

FIG. 3 shows a timing diagram for explaining an example of the operation of the embodiment circuit of FIGS. 1 and 2. In FIG.

A signal is formed from the AND (A·B) of the inverted signal of the oscillation signal A of the voltage-controlled oscillation circuit VCO and its 1/2 frequency-divided signal B. Then, a signal C is formed from the inverted logical sum (A+B) of the signals A and B. by this,
For example, with respect to the rising edge of the signal C (C1), the rising edges of the signals D (Di and D2) are made to have a phase difference of T/2 (T is the period of the signals C and D).

Furthermore, when the operation start signal E is changed from low level to high level at an arbitrary timing, the flip-flop circuit DF
The clear state of F3 is released.

Therefore, the inverted output signal Q of the flip-flop circuit DFF3 is changed from high level to low level in synchronization with the rising edge of the signal. This opens the gates of NOR gate circuits G1 and 02.

In this state, the signal Xl that arrived first is transmitted to the clock terminal CK of the flip-flop circuit DFF 1 via the NOR gate circuit G1 and the inverter circuit N1.
The output signal Q is changed from low level to high level.

The signal C1 that arrived late is sent to the flip-flop circuit DFF via the NOR gate circuit G2 and the inverter circuit N2.
Since the signal is transmitted to the clock terminal CK of No. 2, its output signal Q is changed from low level to high level. This results in
The output signal of the Nant gate circuit G3 becomes low level and clears (resets) the flip-flop circuits DFFI and DFF2.

By the above operation, from the rising edge of signal X1 to signal C
In other words, an up signal UP according to the phase difference between the signal X and the signal C is formed until the rise of the signal. By outputting this up signal UP, the loop filter LP
F increases the control voltage VC (not shown) to increase the frequency (advance the phase) of the oscillation signal A of the voltage-controlled oscillation circuit VCO. By repeating such operations, a signal C (A, B) synchronized with the reference signal X can be obtained.

In this embodiment, the synchronization circuit causes the phase comparison section in the phase comparison circuit to always start its operation in synchronization with the rising edge of the signal C. Therefore, the phase comparison operation always starts at the rising edge of the signal C. This is performed for a reference signal X that arrives within a half period (T/2) in the positive and negative directions. As a result, for example, as shown in FIG. 4, the phase comparison between the signal CI and the signal X2, which are different in phase by more than half a cycle, is not performed.

As a result, PLL using the phase comparison circuit of this embodiment
Since the circuit (V F O) performs a synchronization operation on signals having a phase difference of approximately half a period at most, the PLL pull-in time can be shortened.

The effects obtained from the above examples are as follows. That is, (1) Form a second signal whose phase is different from the first signal by about an interval, and synchronize it with the 1γ rising or falling edge of this second pulse signal. By starting the phase comparison operation, the phase comparison operation with the reference frequency is performed within a phase difference of about half a period at most with respect to the first pulse, and the time required to synchronize both signals is reduced. You can get the effect of being able to make it shorter.

(2) According to (1) above, since the pull-in range can be set relatively narrow, it is possible to achieve the effect that highly accurate synchronization can be achieved.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, if the phase comparison section forms a phase comparison output signal according to the phase difference between the falling edges of the pulse signal, the operation start control signal should also be generated in synchronization with the falling edge of the signal. Moreover, the specific structure of the phase comparator may be various embodiments, such as one using the above-mentioned flip-flop circuit or a combination of logic gate circuits. Accordingly, a control circuit is provided to control the operation start timing.

The present invention can be widely used in various PLLLH paths as a phase comparator circuit in addition to the V 1''O described in -.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, a second signal whose phase is different from that of the first signal to be phase-compared by about an hour period is formed, and the phase comparison operation is started in synchronization with the rising or falling edge of this second pulse signal. By doing so, the phase comparison operation with the reference frequency is performed within a phase difference of about half a period at most with respect to the first pulse, so that the time required for synchronizing both signals can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a phase comparison circuit according to the present invention, FIG. 2 is a block diagram showing an embodiment of a VFO using the above phase comparison circuit, and FIG. 3 is its operation. Timing diagram for explaining an example FIG. 4 is a timing diagram for explaining an example of the prior art. DFF1~DFF3...Flip-flop circuit, Gl,
G2. G4... Noah gate circuit, G3. G4...Nant gate circuit, N1~N4...Inverter circuit, PFC...
・Phase comparison circuit, LPF...Loop filter, VCO・
・Voltage controlled oscillator circuit, DV... Frequency divider circuit Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. I T2

Claims (1)

[Claims] 1. A pulse generation circuit that forms first and second pulse signals whose phases are made to differ by approximately half a period based on an oscillation frequency signal of a voltage-controlled oscillation circuit, and a pulse generation circuit that starts operation. a first circuit that receives a control signal and forms a control signal synchronized with a rising or falling edge of the second pulse signal, and a rising or falling edge of the reference frequency signal and the first pulse signal according to the control signal; a second circuit that starts an operation of forming an output signal proportional to the phase difference between the edges. 2. In the first circuit, a high-level signal is constantly formed at the data terminal, the second pulse signal is supplied to the clock terminal, and the operation start control signal is supplied to the reset terminal to enter the reset state. 2. The phase comparator circuit according to claim 1, wherein the phase comparator circuit is an edge-trigger type flip-flop circuit that forms the control signal from an output terminal. 3. The second circuit has a constant high-level signal formed at its data terminal, and receives the control signal at its clock terminal. 2. The phase shifter according to claim 1, wherein the phase shifter comprises a pair of edge-triggered flip-flop circuits, each of which is supplied with a frequency signal and whose reset terminal is supplied with an AND signal of the output signals. Comparison circuit.