JPS627149A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To provide memory function in an MOS transistor itself by controlling the amplitude and timing of a voltage applied to the gate and drain of an MOS transistor formed on an insulator. CONSTITUTION:An N-type impurity is doped in a P-type silicon layer 21 formed on an insulator 10 to form source and drain regions 22, 23, a gate electrode 25 is formed through a gate oxide film 24, thereby forming an N-type MOS transistor 20. The layer 21 is formed by single crystallizing the silicon film after polycrystalline or amorphous silicon film is formed on the insulator 10 such as SiO2 film. The source 22 of the transistor 20 is grounded, and a drain 23 and a gate 25 are connected with a sensing circuit 30. The circuit 30 writes and reads out memory information of the transistor 20 to control the amplitude and timing of the voltage applied to the gate and drain.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device using a MOS transistor formed in a semiconductor layer on an insulator.

(Technical background of the invention and its problems) Although it is formed by individual MOS capacitors, there is a limit to reducing the capacitance of the capacitor, and as long as this structure is used, it is desirable to improve the degree of integration. has become almost impossible.

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances, and its purpose is to make it possible to realize a smaller dynamic memory element structure by using a MOS transistor formed on an insulator, and to achieve high performance. It is an object of the present invention to provide a semiconductor memory device that can achieve higher integration and higher speed.

[Summary of the invention]

The gist of the present invention is to realize one memory element with one Mo8 transistor, and by controlling the magnitude and timing of the voltage applied to the gate and drain of the Mo8h transistor formed on the insulator. ,M
The purpose is to provide the OS transistor itself with a memory function.

That is, the present invention provides a semiconductor memory device for writing and reading information, in which an electrically floating voltage is added and then the gate voltage is adjusted according to the information to be written.

The applied voltage is zeroed in the order of drain voltage or drain voltage and then gate voltage, and the number of majority carriers in the channel region is
) and a reading means for reading out the written information by detecting a change in the conductance of the MOS transistor.

(Effects of the Invention) According to the present invention, one memory element can be realized with one MOS transistor, so the area occupied by the element is smaller than that of the conventional structure. It is possible to realize a storage device.
Since one memory element can be realized with an S transistor,
There are also advantages such as the structure is simple and manufacturing can be facilitated.

[Embodiments of the invention]

Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a schematic configuration diagram showing a semiconductor memory device according to an embodiment of the present invention. A type MOS transistor 20 is formed on the insulator 10 .

Here, the silicon layer 21 is formed by, for example, forming a polycrystalline or amorphous silicon film on the insulator 10, such as a 5iOz film, and then converting this silicon film into a single crystal by beam annealing. Ru. Further, an oxide film for element isolation is formed by oxidizing the single crystal silicon layer other than the element formation region.

The source 22 of the MOS transistor 20 is grounded,
The drain 23 and gate 25 are connected to a sense circuit 30. The sense circuit 30 includes a MOS transistor 20
It is used to write and read out stored information, and to control the magnitude and timing of the voltage applied to the gate and drain.

Here, the sense circuit 30 has two application timing modes when writing information. In the first mode, as shown in Fig. 2(a), after applying a voltage (5V) about the threshold voltage to the gate and drain, the gate voltage G is set to zero, and after 100 psec, the drain voltage is A voltage (2.5 V) is applied to the extent that no ionization occurs, and a voltage approximately equal to the threshold value is applied to the gate.

Then, from the current flowing at this time, the MOS transistor 2
The information written in 0 is read out.

Note that the MOS transistors 20 described above are arranged in a matrix like a normal semiconductor memory element, and the gates and drains are connected to word lines and bit lines, respectively, thereby forming a memory circuit. It is functional.

Next, the operation of the present gastric insufflation constructed as described above will be explained.

First, the source voltage of the MOS transistor 20 is set to 0, and a voltage of 5 V is applied to the gate and drain, respectively. At this time, as shown in FIG. 3(a), the concentration of electrons forming the channel increases, the holes are pushed into the lower part of the silicon layer 21, and the absolute amount also decreases. Furthermore, since the drain voltage is high, holes generated by impact ionization near the drain constantly recombine near the source.

Therefore, when the gate voltage is set to Ov, the generated holes are accumulated in the silicon layer 21.

-''''''' When the drain voltage is set to Ov 100 psec after the tip voltage is set to Ov, a state close to an equilibrium state is realized.

On the other hand, the drain voltage is set to 0 from the state shown in Fig. 3(a), and after 100 psec, the gate voltage is set to Ov.
Then, as shown in FIG. 3(C), the electrons forming the channel flow out in both the source and drain directions. However, since both the source and drain are 0■, the potential gradient is small and impact ionization hardly occurs. Therefore, the silicon layer into which the electrons have flowed is in a non-equilibrium state with too few holes.

As mentioned above, whether holes are sufficiently accumulated in the silicon layer or
Alternatively, the MOS transistor 20 can be provided with a write function as a memory element by selecting either of two directions: a state with an insufficient number of holes or a state with an insufficient number of holes.

Now, at the time of reading, a drain voltage that does not cause impact ionization is applied. The state where the silicon layer 21 is close to an equilibrium state ff! In (the state shown in Figure 3 (1)),
When a gate voltage of about the threshold value is applied, Fig. 4(a)
As shown in the figure, there are many holes in the silicon layer 21, and a drain current flows due to overshoot. On the other hand, when the silicon layer 21 is in a non-equilibrium state (the state shown in FIG. 3(C)), as shown in FIG. 4(b), even if the same voltage is applied to Since the amount is small, the substrate potential is low and almost no drain current flows.

By doing the above, it is possible to distinguish between two types of information: whether holes are sufficiently accumulated in the silicon layer 21 or not.

Thus, according to this embodiment, the MOS transistor 20 can have the function of a memory element.

That is, one memory cell can be realized from one MOS transistor 20. Therefore, higher integration and higher speed can be achieved compared to the conventional one using a memory cell consisting of one transistor/one capacitor.

Furthermore, since the element structure is simple, there are also advantages such as ease of manufacturing.

Note that the present invention is not limited to the embodiments described above. For example, the MOS transistor is not limited to N type, but may be P type.

Furthermore, the silicon layer is not formed on an amorphous insulator such as SiO2 (SoI), but is formed on a single crystal insulator such as sapphire (SO8). It can be implemented by

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram showing a semiconductor memory device according to an embodiment of the present invention, and FIGS. 2(a) and 2(b) are signal waveform diagrams for explaining the operation of the sense circuit used in the above device. , 3rd
FIGS. 4A to 4C are schematic diagrams for explaining the write operation, and FIGS. 4A and 4B are schematic diagrams for explaining the read operation. DESCRIPTION OF SYMBOLS 10... Insulator, 20... N channel MOS transistor, 21... P-type silicon layer, 22... Source, 23... Drain, 24... Gate oxide film, 25
...Gate electrode, 30...Sense circuit. Applicant Tatsu Todoroki Director General of the Agency of Industrial Science and Technology Figure 2 (a) (b) No. 352

Claims (3)

[Claims] (1) A source layer consisting of an impurity layer of a conductivity type opposite to that of the semiconductor layer is placed at both ends of an electrically floating semiconductor layer of one conductivity type.
A MOS transistor has a drain formed therein and a gate electrode formed on the semiconductor layer via an insulating film, and after applying a gate voltage and a drain voltage to this transistor, a gate voltage and a drain voltage are applied depending on the information to be written. a writing means for controlling the number of majority carriers in the channel region by reducing the applied voltage to zero in the order of the drain voltage or the drain voltage and then the gate voltage; and reading the written information by detecting a change in the conductance of the MOS transistor. 1. A semiconductor memory device comprising: reading means. (2) The semiconductor layer forming the MOS transistor is
The semiconductor memory device according to claim 1, wherein the semiconductor memory device is formed on an insulator. (3) A patent claim characterized in that the voltage applied to the drain during writing is such a drain voltage that impact ionization occurs, and the voltage applied to the drain during reading is such a drain voltage that impact ionization does not occur. The semiconductor memory device according to item 1.