JPS62191971A - Image memory device - Google Patents

Abstract

PURPOSE:To execute any of a bit writing and a word writing without lengthening a memory writing cycle by inputting the output of a gate group as the memory writing enable signal in a bit unit to the memory group in the bit unit. CONSTITUTION:Bit mask data are outputted to the first half of a memory writing cycle, writing data are outputted to the second half, the bit mask data on a data bus 2 when a clock CLK 10 of a register 8 rises are latched to a register 8, inputted to a NAND gate group 9, AND with a writing enable signal WE 11 is obtained, and the reverse of writing enable signal WE 12 to a DRAM group 1 is generated. In such a case, at the second half of the writing cycle, the WE signal 11 is generated so that the inverse WE of signal can fall. The DRAM group 11 is activated by the inverse of RAS signal 6 and the inverse of CAS signal 7, in accordance with the latched bit mask data, a DRAM, in which the inverse of WE 0-WE 15 signals 12 are not in the enable condition, preserves the previous data and only the DRAM in the enable condition writes the equivalent writing data.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an image memory device for storing image information of bitmap displays, graphic displays, image workstations, etc. as dot images.

(Prior Art) Conventionally, writing to a memory is performed in units of words, with a bit length of, for example, 16 bits forming one word. Therefore, when a certain address is designated and a write operation is performed on the memory, the 16 bits at that address are replaced with new data regardless of the previous value. For example, when drawing a straight line, it is necessary to save previous data in memory except for the corresponding pixel in a certain word, so it is necessary to write in units of pixels. However, since data that has already been written is erased in word units, conventionally a read-modify-write cycle has been used to perform a logical sum (OR) with data that has already been written.

(Problem to be solved by the invention) However, the read-modify-write cycle has a longer cycle length than the normal write cycle.
There was a drawback that the performance of the image processing device deteriorated. Furthermore, word writing is suitable for transferring rectangular image data to an image memory for multi-window display, but if the image memory device is configured in a fixed bit writing manner.

It had the disadvantage that Word writing was no longer possible and multi-window display was troublesome.

Therefore, recently there has been a demand for an image memory device that can write with a short write cycle length for both bit writing and word writing.

(Means for Solving the Problem) The present invention uses a normal memory write cycle that enables both bit writing and word writing without lengthening the memory write cycle, and writes a word in the first half of the cycle. Latch the bit mask data that indicates the bits you want to rewrite among the bits that make up the data into a register.

In the second half of the cycle, the memory write enable signal and the bit mask data latched in the register mentioned above are ANDed bit by bit, and the output for each bit is output to the data bus as a bit-by-bit memory write enable signal. It is configured to write write data to memory.

(Embodiment) FIG. 1 shows a block diagram of an embodiment of the present invention. 1
is a bit-based dynamic random access memory (DRAM) group with a word length of 1 bit, and 16 DRAMs constitute a memory with 1 word of 16 bits. 2 is a 16-bit data bus (Do-D15), each pin is connected to the data input of the corresponding DRAM group 1.

3 is an address bus, which is connected in parallel to 16 DRAMs. 4 is a memory write command (MWT C) signal which gives a write command to the memory; 5
is a timing controller that generates various necessary timings based on the MWTC signal 4. 6 RAS and 7'
? 17TT are DRAM group 10πI]-signals and dez]-signals, respectively, which are connected in parallel to the 16 DRAMs. 8 is a 16-bit register, 9 is a group of NAND gates, 10 is CLK&”! Clock of register 8, 11
WE is a write enable signal for gate group 9.

12 WEO to WI]]- is a write enable signal for DRAM group 1.

(for production) Access to normal memory (DRAM group 1).

A writing device (not shown) outputs data to be written to the data bus 2 and an address to be written to the address bus 3, and sets the state of the MWTC signal 4, which is a memory write command, to an enabled state.

In the present invention, as described above, both bit writing and word writing are possible.

Data bus 2 is used in time division.

FIG. 2 is a diagram showing the data write timing of the image memory device of the present invention. As shown in FIG. 2, the writing device outputs bit mask data in the first half of a memory write cycle and outputs write data in the second half. Here, the bit mask data indicates the bits you want to write out of 16 bits of data.9For example, if you want to rewrite all 16 bits as a word write, write F in hexadecimal.
Output FFF to data bus 2iC. Also, like bit writing, only 1 bit is rewritten (other 15 bits)
If you want to leave the previous data as is in LX, set only the data line at the corresponding bit position to 1. For example, if only the least significant bit is to be rewritten, 0001 in hexadecimal is output to the data bus 2.

-RAS and στ]- in Figure 2 shows the timing of the RAS signal 6 and CAS signal 7 necessary to operate the DRAM group 1, and the state of the external MWTC signal 4 is enabled. is generated by the timing controller 5.

CLK in FIG. 2 is generated by the timing controller 5, and the clock input of the register 8 and the null clock 10
It shows the timing of.

The data on the data bus 2 is latched into the register 8 by the rising edge. Here, bit mask data is output on the data bus 2 at the time when CLK rises, and this data is latched into the register 8. The 16-bit parallel output data latched in the register 8 is input to a group of 16 NAND gates 9.

A logical AND operation is performed with the write enable signal WEII from the timing controller 5 to generate write enable signals 1W10,000 to WE1512 for the DRAM group 1.

The operating mode of the DRAM is 1/1-1, which is determined by the mutual positional relationship of the AS and WE multiplication signals, but this device uses a late write cycle, which is one of the basic operating modes of the DRAM. In the late write cycle, the write data is written to the DRAM by the falling edge of the WT double signal.

As shown in the second graph, a WE multiplier signal (WEI 1 in FIG. 1) is generated on the data bus 2 by the write device 5.

In the DRAM group 11, 16 metal parts are activated by the τT signal 6 and the CAgo signal 71C at the timing shown in FIG. 2, but in the latter half of the memory write cycle.

WE multiplied signals WEO to WE are supplied individually according to the bit mask data already latched in register 8.
15H2 is not enabled DRAM&! The previous data is saved and only the enabled DRAM writes the corresponding data of the write data output to the data bus 2.

Through the operations described above, a single image memory device capable of both bit writing and word writing is realized with just a memory write cycle.

(Effects of the Invention) As explained above, the present invention uses a normal memory write cycle, latches bit mask data indicating the bit to be rewritten among the bits constituting a word in the first half of the cycle, and In the latter half of the process, a bit-by-bit memory write enable signal is sent to the bit-by-bit memory group according to the bit mask data latched in the register, and the write data is written to the memory, thereby reducing the memory write cycle length. Both bit and word writes can be performed without increasing the length.

This has the effect of improving the performance of the image processing device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention. FIG. 2 is a diagram showing the data write timing of the image memory device of the present invention. 1...Dynamic random access memory (
DRAM) group, 5...timing controller. 8...Register, 9...NAND'y''-)W.

Claims (1)

[Claims] In an image memory device that inputs memory mask data in the first half of a memory write cycle and write data in the second half of the cycle, a memory group in bit units equal to the number of bits constituting a word, and a register that latches the memory mask data; A gate group that performs an AND operation between the parallel output of the register and a memory write enable signal on a bit-by-bit basis, and a timing controller that generates a timing signal group such as the memory write enable signal; An image memory device characterized in that a memory write enable signal is input in bit units to a unit memory group.