JPS6144785A - Manufacture of thin film of semiconductor single crystal - Google Patents

Abstract

PURPOSE:To obtain a thin film of a semiconductor single crystal having high quality and resistant to the formation of crystal boundary, by applying a heat-dissipation controlling layer to form a double-humped temperature distribution selectively to a semiconductor layer interposing a reaction-prevention layer therebetween. CONSTITUTION:A polycrystalline semiconductor layer 2 is formed in stripe form on the insulating substrate 1 made of e.g. quartz. A reaction-prevention layer 8 made of SiO2, etc. and having a thickness of about <=5,000Angstrom is applied to the substrate 1 and the polycrystalline semiconductor layer 2. A highly heat-conductive layer 9A is applied to the center of the polycrystalline semiconductor layer 2 along its longitudinal direction. A linear heating means is placed nearly perpendicularly to the longitudinal direction of the polycrystalline semiconductor layer 2, and transferred along the longitudinal direction. The polycrystalline semiconductor layer 2 just below the heater is melted and then cooled, solidified and recrystallized spontaneously. The temperature distribution along the width of the semiconductor layer 2 becomes a double-humped distribution by this process. Accordingly, the conversion to single crystal takes place from the center of the semiconductor layer 2, and proceeds gradually toward both ends. Consequently, the formation of crystal grain boundary at the center part of the semiconductor layer 2 can be prevented.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a method for manufacturing a semiconductor single crystal thin film.

BACKGROUND OF THE INVENTION A conventional method for manufacturing a semiconductor single crystal thin film will be described with reference to FIGS. 11 and 12. First, referring to FIG. 11, a semiconductor device in which a semiconductor single crystal thin film is to be formed will be described. (1) is an insulating substrate made of quartz or the like (8102 eyebrows formed on a St substrate is also possible), and (2) is formed in a band shape by low-pressure chemical vapor deposition, etc. The polycrystalline silicon layer (3) is a cap layer, such as 8102, deposited over the substrate (1) and the polycrystalline silicon layer (2).

As shown in FIG. 12, a Kerr heater and laser beam generator are applied to the belt-shaped polycrystalline silicon layer (2) in the longitudinal direction (scanning direction) (5) via the cap layer (3). A linear heating means (4) such as a source, a halogen lamp, an IR lamp, an electron beam generator source, etc. is scanned. Thus, the heating means (4) K through the cap layer (3)
The heated polycrystalline silicon layer (2) melts, and as the heating means (4) moves away, it naturally cools and solidifies.
Recrystallizes to become a single crystal.

In this case, since the cooling progresses from both sides of the band-shaped polycrystalline silicon layer (2) toward the center, the isothermal line of the part where the heating means (4) has already passed is as shown by the broken line a in the figure. It forms a convex curve downwards (in the direction opposite to the scanning direction a). In this way, the polycrystalline silicon layer (2) is cooled and solidified to become a single crystal from both side edges toward the center as shown by the arrow (6). Therefore, a crystal grain boundary (7) is formed in the center of the obtained single-crystal silicon layer (1), as shown by the symbol (7), and the quality of the crystal deteriorates.

Such grain boundaries (7) are undesirable because leakage current will occur at these grain boundaries when a semiconductor (integrated) circuit is formed by implanting impurities into this single crystal layer.

Problems to be Solved by the Invention In view of these points, the present invention seeks to propose a method for manufacturing a semiconductor single crystal thin film that can manufacture a high quality semiconductor single crystal thin film in which grain boundaries are unlikely to occur. It is something.

Means for Solving the Problems The method of manufacturing a semiconductor single crystal thin film according to the present invention involves scanning a heating means over a semiconductor layer to melt the semiconductor layer, and then cooling and solidifying the semiconductor layer to form a semiconductor single crystal thin film. In the method for manufacturing a semiconductor single crystal thin film, a heat dissipation control layer that makes the temperature distribution in a direction substantially orthogonal to the heating scanning direction of the semiconductor layer bimodal is formed on the semiconductor layer through a reaction prevention layer of about 50,000 mm or less. It is designed to be applied selectively.

In this way, after the semiconductor layer heated and melted by the heating means passes through the heating means, cooling progresses from the center to both sides, and recrystallization progresses from the center to both sides. It is possible to obtain a high-quality semiconductor single-crystal thin film in which crystal grain boundaries are less likely to occur.

Example An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 shows a semiconductor device in which a semiconductor single crystal thin film is to be formed, and (1) is an insulating substrate made of quartz or the like.

This insulating substrate (1) may also be one in which a 5IO2 layer is deposited on an S1 substrate. A polycrystalline semiconductor layer (2) made of silicon, for example, is formed in a band shape on the substrate (1). Then, a reaction prevention layer (8) made of, for example, 8102 and having a thickness of approximately 5000× or less is deposited over the substrate (1) and the polycrystalline semiconductor layer (2). A high thermal conductivity layer (9A) having higher thermal conductivity than the polycrystalline semiconductor layer (2) is placed in the center of the polycrystalline semiconductor layer (2) along its longitudinal direction via a reaction prevention layer (8). Form the adhesion. This high thermal conductivity layer (9A) includes Mo*Ta,
W.

Pt, Nb, etc. are used. Thermal conductivity of these substances at the melting point of Sl (1412°C) ('/see, (W
I-deg) is Huo Mo: 0.21, Ta:
0.19, W: 0.25. Pt: 0.157
, Nb: 0.154, St: 0.058 3
That's more than double that. Further, the specific heat of these substances is lower than that of St.

Note that the width and thickness of this high thermal conductivity layer (9A) are arbitrarily set depending on the heating means, the thickness and width of the polycrystalline semiconductor layer (2), etc.

Therefore, the above-mentioned carden heater, laser beam generation source, halogen lamp, IR rung, electronic beam J
・A linear heating means such as a generation source is connected to a band-shaped polycrystalline semiconductor layer (2
) and move it in the longitudinal direction. As a result, the polycrystalline semiconductor layer (2) immediately below the heating means is melted, and as the heating means moves away, that portion is solidified by natural cooling and recrystallized.

In this case, since the high thermal conductivity layer (9A) is provided in the center of the polycrystalline semiconductor layer (2), the heat in this area is quickly radiated to the outside through the high thermal conductivity layer (9A).
Since the portion without the high thermal conductivity layer (9A) radiates heat slowly, the temperature distribution in the width direction of the band-shaped semiconductor layer (2) is bimodal. Therefore, single crystallization (recrystallization) starts from the center of the polycrystalline semiconductor layer (2) and gradually progresses toward both sides. In this way, there is almost no possibility that grain boundaries will be formed in the center of the single crystal semiconductor layer as in the conventional case.

In the embodiment shown in FIG. 1, the case was described in which the high thermal conductivity layer (9A) was provided on the polycrystalline semiconductor layer (2) through the reaction prevention layer (8), but as shown in FIG. A high thermal conductivity layer (9A) may be provided below the polycrystalline semiconductor layer (2), that is, between the substrate (1) and the polycrystalline semiconductor layer (2), with a reaction prevention layer (8) interposed therebetween. .

In this case, the high thermal conductivity layer (9) of the polycrystalline semiconductor layer (2)
Heat is dissipated from the portion where A) is provided to the substrate (1) side more quickly than from other portions.

Further, as shown in FIG. 3, a high thermal conductivity layer (9Aa) is formed on the polycrystalline semiconductor layer (2) via a reaction prevention layer (8a), and the lower side of the polycrystalline semiconductor layer (2) is coated with a high thermal conductivity layer (9Aa). , that is, a reaction prevention layer (
A high thermal conductivity layer (9Ab) may be disposed via the layer 8b). Thus, a high thermal conductivity layer (9Aa).

Compared to other parts of the polycrystalline semiconductor layer (2) sandwiched by (9Ab), heat is quickly dissipated from the upper high thermal conductivity layer (9Aa)', and the lower high thermal conductivity layer (9Ab
) and the substrate (1).

In the embodiments of FIGS. 1 to 3 described above, the reaction prevention layer (8)
This is a case in which a high thermal conductivity layer (9A) is provided in the center of the polycrystalline semiconductor layer (2) through a reaction prevention layer (8) on both sides of the polycrystalline semiconductor layer (2). It is also possible to deposit a low thermal conductivity layer that has a lower thermal conductivity than the polycrystalline semiconductor layer (2). That is, as shown in FIG.
), low thermal conductivity layers (9B) are deposited on both sides of the polycrystalline semiconductor layer (8) and on the substrate (1) so that a groove is formed in the center of the polycrystalline semiconductor layer (8).

This low thermal conductivity layer (9B) is 3A/1.203-
28102, At203, Z rO2, etc. are possible, and their thermal conductivity (m/see, crn, deg)
is 31120. -2s102: 0.013, At
203: 0.014°Z rO2: 0.005 or less, Si: 0.058 or less.

Incidentally, the specific heat of these substances is even greater than that of 81.

As a result, heat dissipates more quickly in the central part of the polycrystalline semiconductor layer (2) than in other parts, and single crystallization (recrystallization) by cooling and solidification starts from this part, which gradually progresses to both sides. As a result, grain boundaries hardly occur in the center as in the conventional case.

In the example of FIG. 4, the low thermal conductivity layers (9B), (9B)
In this case, the low thermal conductivity layer (9B) is placed on both sides of the polycrystalline semiconductor layer (2) via the reaction prevention layer (8). It is not only provided on both sides of the layer (2), but also under the polycrystalline semiconductor layer (2) via the reaction prevention layer (8), that is, between the substrate (1) and the polycrystalline semiconductor layer (2). It is also possible to provide one. In this case, heat dissipates more quickly in the center of the polycrystalline semiconductor layer (2) than in other parts.

Furthermore, as shown in FIG. 6, the low thermal conductivity layers (9B) and (9B) are connected to the polycrystalline semiconductor layer (9B) via the reaction prevention layer (8).
2), that is, on both sides between the substrate (1) and the polycrystalline semiconductor layer (2).

FIG. 7 is a compromise between the embodiments shown in FIGS. 1 and 4, and according to this, a high thermal conductivity layer (9A) is provided in the center of the polycrystalline semiconductor layer (2), and a low heat conductivity layer (9A) is provided on both sides of the polycrystalline semiconductor layer (2). Conductivity layer (9B
), the speed of heat dissipation to both sides of the central portion of the semiconductor polycrystalline layer (2) is significantly increased.

In the embodiment shown in FIG. 8, a high thermal radiation multilayer (9C) having a higher thermal emissivity than the polycrystalline semiconductor layer (2) is placed on the polycrystalline semiconductor layer (2) via a reaction prevention layer (8) in the longitudinal direction. This is the case where it is provided in the center along the This high heat radiation multilayer (9C
), use Kargan. Melting point of Sl (1412℃
) is the emissivity at Kerr? silicon is 0.8°
．． It is 5.

According to this, the polycrystalline semiconductor layer (2) is heated and melted by the heating means, and after the heating means passes, thermal radiation of the polycrystalline semiconductor layer (2) occurs more quickly in the center than on both sides. As a result, crystallization by cooling and solidification starts from the center and progresses to both sides, making it difficult to form grain boundaries as in the conventional case.

FIG. 9 shows a case where the high thermal radiation multilayer (9C) in FIG. 8 is divided in a direction perpendicular to the longitudinal direction of the polycrystalline semiconductor layer (2) to increase its surface area and improve radiation efficiency.

Incidentally, the embodiments shown in FIGS. 1 to 9 can be modified as appropriate. In that case, a combination of a high thermal conductivity layer or a high thermal radiation overlay and a low thermal conductivity layer will be used.

An example of a method for manufacturing an MO8 field effect transistor in which the high thermal conductivity layer as the heat dissipation control layer used in the present invention is also used as the f-) electrode will be described below with reference to FIG. In FIG. 10A, (1) is an insulating substrate made of quartz or the like, on which an insulating layer a1 such as 5102 is formed. A polycrystalline semiconductor layer (2) made of silicon is deposited on this insulating layer (10), and a reaction prevention layer (8) such as an 8102 layer of 100 OX or less is deposited thereon. 2) On top, a high thermal conductivity layer (9A) made of metal is placed in the center with a reaction prevention layer (8) interposed therebetween.
Form the adhesion. Then, the polycrystalline semiconductor layer (2) is heated and melted by heating means and cooled and solidified in the same manner as described above, thereby converting the polycrystalline semiconductor layer (2) into a single-crystalline semiconductor layer.

Next, as shown in FIG. 10B, p-type or n-type impurities are implanted into regions on both sides of the single-crystal silicon semiconductor layer by a technique such as ion implantation. Regions (20a) and (20b) are formed.

Thereafter, as shown in FIG. 10C, holes are etched on the impurity regions (201L) and (zob) of the reaction prevention layer (8), and the metal electrode layer (201L), which will become the drain and source electrodes, is etched. 21a), (21b) are deposited through the holes over the impurity regions (20a), (20b) and the reaction prevention layer (8). In this case, the reaction prevention layer (8) under the high thermal conductivity layer (9A) as a dirt electrode functions as an insulating film between the single crystal semiconductor layer and the thickness thereof is approximately 1000X or less as described above. is suitable.

In FIG. 10, the polycrystalline semiconductor layer (2) is converted into a single-crystalline silicon semiconductor layer (a) and then doped with impurities. It is also possible to dope with impurities.

According to the embodiment shown in FIG. 10, a high thermal conductivity layer made of a metal used to improve the quality of crystal when converting a polycrystalline semiconductor layer into a single-crystalline semiconductor layer is used as a gate electrode of an MO8 field effect transistor. MO8 field effect transistors can be easily manufactured using crystalline thin films at reduced manufacturing costs.

Effects of the Invention According to the present invention described above, it is possible to obtain a method for manufacturing a semiconductor single crystal thin film that can form a semiconductor single crystal thin film of good quality in which grain boundaries are unlikely to occur in the central portion.

[Brief explanation of the drawing]

1 to 9 are cross-sectional views showing each embodiment of the method for manufacturing a semiconductor single crystal thin film according to the present invention, and FIG. 10 is a manufacturing method for an MO3 field effect transistor applying the method for manufacturing a semiconductor single crystal thin film according to the present invention. 11 is a cross-sectional view showing the steps of the method; FIG. 11 is a cross-sectional view explaining the conventional method for manufacturing a semiconductor single crystal thin film; FIG. 12 is a line along the line showing the crystallization of the polycrystalline semiconductor layer in FIG. . (1) is a substrate, (2) is a polycrystalline semiconductor layer, (8) is a reaction prevention layer, (9A) to (9C) are heat dissipation control layers, of which (9A) is a high thermal conductivity layer, and (9B) is a Low thermal conductivity layer, (
9C) is a high thermal conductivity layer.

Claims (1)

[Claims] In a method for producing a semiconductor single crystal thin film, the semiconductor layer is melted by scanning a heating means over the semiconductor layer, and then cooled and solidified to form a semiconductor single crystal thin film. A semiconductor single crystal characterized in that a heat dissipation control layer that makes the temperature distribution in a direction substantially orthogonal to the scanning direction bimodal is selectively deposited on the semiconductor layer via a reaction prevention layer of approximately 5000 Å or less. Method for manufacturing thin films.