JPS6061999A - Thin film shift register circuit - Google Patents

Abstract

PURPOSE:To avoid the malfunction of a thin film shift register and to improve the performance of said register by adding especially a malfunction preventing capacity with use of an insulated thin film such as an inter-layer insulated film, etc. of a thin film transistor as a dielectric matter. CONSTITUTION:A thin film transistor constituting a shift register contains an insulated substrate 401, a channel part 402, a gate oxide film 403, a gate electrode 404, an inter-layer insulated film 405 and a power supply line 406. A malfunction preventing capacity is provided with the electrode 404, the film 405 and the line 406. Plural units of such malfunction preventing capacities are set in parallel to each other, and only the capacity having a short circuit trouble is cut off. This improves the performance and the yield of an active matrix substrate incorporating peripheral drive circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thin film shift register circuit, and particularly to a thin film shift register circuit in an active matrix substrate with a built-in peripheral drive circuit.

Currently, active matrix substrates include gate lines, data lines, MOS (MOS) provided at the intersections of the gate lines and the data lines, and MOS transistors (MOS) provided on a single crystal silicon substrate.
) Those using peripheral drive circuits based on transistors, or those using gate lines and data lines provided on an insulating substrate, and thin film transistors provided at the intersections of the gate lines and the data lines, are being actively manufactured and prototyped. .

By the way, in an active matrix substrate using thin film transistors provided on an insulating substrate, in order to reduce the size, performance, and cost of an active matrix type liquid crystal display device using the active matrix substrate, it is necessary to use thin film transistors on the active matrix substrate. Built-in peripheral drive circuits are required.

In a conventional shift register using a MOS3) register formed on a single crystal silicon substrate, there is a junction capacitance between the source or drain part and the substrate, and wiring capacitance is also easily added, so a capacitor for preventing malfunction is especially provided. There was no need. An example is shown in FIG. In KTh in the figure, 100 and 101 are clock lines to which clock signals having opposite phases are applied. 102 is a data input terminal, 10
3 is the power line, 110 to 113, 120 to 123゜1
30 to 133 etc. are MOS transistors, 112-4.124 and 134 are MOEI capacitors using MOS transistors, 115, 125 and 135 are MOI 3) transistors and MO8 capacitors 111 and 114, respectively.
, 121 and 124, 131 and 134 etc. gates, 1
16, 126, 136, etc. are output terminals of the shift register, and the figure shows an example of a single channel dynamic type shift register. FIG. 2 shows examples of voltage waveforms at various parts. 200 and 2゜1 are clock signals applied to the clock lines 100 and 01 respectively, 202 is a data signal applied to the data input terminal 102, and 203 is a MOS register 111.
and the signal waveform observed at the gate 115 of the MO8 capacitor 114, 204 is the signal waveform observed at the shift register output terminal 116, 2o5 is the signal waveform observed at the gate 125 of the MOS transistor 121 and the MO8 capacitor 124, 206 is the signal waveform observed at the shift register output terminal 126, 207 is the MOS) register 131 and MO
8 is a signal waveform observed at the gate 135 of the capacitor 134. The figure shows an example of driving a P-channel dynamic shift register. In FIG. 1, MOS registers 110 to 13 and MOB capacitor 114 form one bit of shift register.

Here, consider a situation where no wiring capacitance is added to the common gate 115, etc. of the MOEI), the transistor 111, etc., and the MO8 capacitor 114, etc., and there is no junction capacitance between the source or drain portions such as 131, 114, etc. and the substrate. In the MOS transistor 1 and the MOI3 capacitor 114, there is an overlap capacitance between the source or drain part and the gate part, but the second
Considering the operation at time t4 in the figure, the clock line 10
0 rises from low to high), and the M08 transistor 110 becomes non-conductive. Further, the potential of the clock line 101 becomes low, and the potential of the clock line 115 drops to a low potential due to the heavy force capacity. Then, since the MOS transistor 111 becomes conductive and the potential of the output terminal 116 decreases, and the MOS transistor 120 is conductive, the MOS transistor 111 becomes conductive.
The potential of the common gate 125 of the B transistor 121 and the MOEI capacitor 124 falls. Therefore, the potential of the output terminal 116 becomes low during the period from t4 to 4-1s.

During periods from tb to t6, the output terminal 126 and M
The potential of the common gate 135 of the O0 day transistor 13 and the MO day capacitor 134 decreases. The above mechanism causes the shift register in Figure 1 to malfunction, but in reality, the MO+3 register and the MO! 3 capacity common game) 1
Wiring capacitance is added between 15, 125, 135, etc. and the power supply (of the potential supplied to the power supply line 103), and junction capacitance exists between the source or drain part of the MOS), transistor, and MO capacitance and the power supply. KM such as the period from t4 to 1s
O8) Common gate 115 for register and MOEI capacitor
etc. suppresses the potential drop. The potential drop of 115 etc. is Vd
, the voltage amplitude of the clock is V, 115 and 111 and 1]4
etc.) and the junction capacitance between the source or drain part of C17, 111, 114, etc. and the power supply, and 11
If the sum of the wiring capacitance added between 5 and the power supply is 08, then
The potential drop vd of 115 etc. is Vd = Cg, V/(C
g + CB).

Therefore, the above-mentioned malfunction does not occur. Therefore, in a shift register using a conventional MOS register, there is no need to provide a special capacitor, since the pn junction region and wiring region play the role of a capacitor for preventing malfunctions.However, in a thin film integrated circuit, Generally, the board is insulated and P? There is no capacitance due to the L junction region, and no capacitance is added to the wiring region.

An object of the present invention is to provide a thin film shift register circuit with a capacitor, use the capacitor to prevent malfunction of the thin film shift register, and improve the performance of the thin film shift register circuit. It is built into an active matrix substrate.

The gist of the present invention is that an insulating thin film such as an insulating film between the eyebrows is used as a dielectric, and a capacitor for preventing malfunction is specially provided.

Hereinafter, the present invention will be described in detail based on Examples.

3 and 4 are examples of the present invention. In FIG. 3, reference numerals 300 and 301 are clock lines to which clock signals having opposite phases are applied. 302 is a data input terminal, 303 is a power line, 31o to 313.32
0 to 323, 330 to 333 etc. are thin film transistors, 314, 324 and 334 etc. are MOE+ capacitors using thin film transistors, 315.325, 335 etc. are common gates of thin film transistors and MO8 capacitors 311 and 334 etc., 316.326 and 336 etc. is the output terminal of the shift register, 317, 327, 337, etc. are capacitors for preventing malfunction provided using insulating thin films, 318, 328, 3
38 etc. is a power source with a potential supplied to the power line 303;
Thin film transistors 310 to 313, MO8 capacitor 314
．． and the malfunction prevention capacitor 317, the shift register 1
A bit is formed. The operation example of the shift register in FIG. 3 is the same as that in FIG. 1, and is as shown in FIG.

FIG. 4 is an example of the structure of the present invention, and is a simplified diagram when a multi-channel portion such as a thin film transistor 311 is cut in the channel width direction. 401 is an insulating substrate; 402 is a thin film transistor cut in the channel width direction; 403 is a gate oxide film;
4 is a gate electrode, 405 is an interlayer insulating film, and 406 is a power supply line. Gate electrode 4042 interlayer insulating film 405. A malfunction prevention capacitor is formed by the power supply line 406.

FIG. 5 shows another embodiment of the invention. The same symbols as in FIG. 3 represent the same things as in FIG.

510. 512, 520, 522, 530, 532, etc. are capacitors for preventing malfunction provided using insulating thin films; 511.
513,521,523,531.

533 and the like are potential power sources supplied to the power line 303. In FIG. 5, thin film transistors 310 to 313
．． MO8 capacity 314. Malfunction prevention containers 1510 and 51
2 forms a 1-bit shift register. In thin-film shift register circuits, defects are most likely to occur in the malfunction prevention capacitor section, because short circuits occur in the insulating thin film section due to dust or the like. Therefore, it is sufficient to provide a plurality of capacitors for preventing singing operation in parallel so that only the capacitor in which a short circuit occurs can be disconnected or separated, and the yield can also be improved. Therefore, in FIG. 5, two malfunction prevention capacitors are provided in parallel in one bit. The operation example of the shift register shown in FIG. 5 is also as shown in FIG. 2.

As described above, by using the present invention, a high-performance thin film shift register without malfunction can be realized, and a high-performance, high-yield active matrix substrate with a built-in peripheral drive circuit can be realized.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining an example of a conventional shift register circuit using a MOS transistor provided on a single crystal silicon substrate. FIG. 2 is a diagram showing applied waveforms to each part of the shift register in FIG. 1. FIG. 3 and FIG. 4 are diagrams for explaining the present invention in detail. FIG. 5 shows the applicant illustrating another embodiment of the present invention.
Suwa Seikosha Co., Ltd. Agent Patent Attorney Tsutomu Mogami 9-

Claims (1)

[Claims] A thin film shift register circuit comprising thin film transistors provided on an insulating substrate or an insulating thin film, characterized in that the thin film shift register circuit uses an insulating thin film such as an interlayer insulating film and is provided with a capacitor for preventing malfunction.