JPS58202560A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To prevent the concentration of an electric field, and to improve reliability by removing an acute angle section of a corner of a convexo-concave section of a device storing and transferring charges in the convexo-concave section formed to a substrate. CONSTITUTION:An n type diffusion layer 52 is formed onto the p type Si substrate 51, and a hole 24 with corner sections 23, 25 from which the acute angle sections are removed is formed. The hole section 24 is formed in such a manner that a mask is formed, the corner section 23 is formed through light etching, a hole is deepened through anisotropic etching, and the corner section 25 is rounded through isotropic etching. A gate electrode is formed to the hole section through a gate insulating film 53, and an MOSFET using the hole is prepared. Accordingly, field concentration at the corners formed to the substrate is avoided, and the reliability of the device is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which uneven portions are formed on a substrate and a method for manufacturing the same, and more particularly to a semiconductor device that prevents electric field concentration at the corners of the uneven portion and a semiconductor device in which diagonal portions at the corners of the uneven portion are removed. The present invention relates to a method for manufacturing a device.

Taking MO8 type capacitors as an example, the area of capacitors is becoming smaller as LSIs become more highly integrated. Miniaturization of the capacitor area causes a decrease in capacitance, that is, a decrease in the amount of stored signals, leading to malfunction of a memory element using this.

Conventionally, in a capacitor with a planar structure shown in FIG.
Decrease in capacitance has been prevented by making the insulating film 2 thinner. However, there is a limit to how thin the insulating film can be made, since making the insulating film thinner may cause insufficient withstand voltage of the capacitor or short circuits. For this reason, a capacitor with a three-dimensional structure as shown in Fig. 2 has been proposed, which occupies a small area on an LSI chip but can increase the capacitor area.
83) That is, by forming the hole 12 in the semiconductor substrate 11 and using the side surface 13 of the hole 12 as a capacitor,
This increases capacity. Conventionally, directional etching methods such as etching or dry etching that depend on the crystal plane orientation of the substrate have been considered for forming the minute holes 12. Sharp corners are formed in the end portions 14 and 15, and electric field concentration and defects in the insulating film 16 are likely to occur at the corners.
This has been a major problem in the formation of three-dimensional capacitors.

SUMMARY OF THE INVENTION In order to solve the above problem, an object of the present invention is to provide a semiconductor device in which the upper and lower corners of the hole are rounded to prevent defects at the corners, and a method for manufacturing the same.

The present invention focuses on the fact that sharp corners at pattern edges that occur during normal fine pattern formation have a negative effect on the electrical characteristics of devices, and performs etching to remove sharp corners in addition to normal pattern formation etching. It is something.

Hereinafter, the present invention will be explained in detail with reference to Examples.

Example 1 FIG. 3 is a sectional view showing the manufacturing process of a three-dimensional MO8 capacitor according to the present invention. As shown in FIG. 3 (1), after a mask 22 with openings in the capacitor formation area is completely formed on a silicon (hereinafter referred to as Si) substrate 21 by normal photoetching, a mixed solution of hydrofluoric acid and nitric acid is applied. The Si is lightly etched by wet etching or plasma etching using Freon gas. This etching is performed to round the corners 23 of the pattern, and any etching that involves undercutting is sufficient, and the etching amount is suitably 10 to 200 nm. As the material of the mask 22, it is necessary to select a material having good etching selectivity with respect to 3i, such as sho, Si, or N4. Subsequently, deep anisotropic etching is performed to approximately determine the shape of the hole, resulting in the result as shown in FIG. 3(2). This etching method uses CCl4 and O! Reactive sputter etching using a mixed gas of 8F or microwave plasma etching using an 8F gas is suitable, and the hole 24 can be formed with high processing accuracy without undercutting. At this time, a substantially right-angled corner 25 is formed at the bottom of the hole 24, so light isotropic etching is subsequently performed to round this corner 25. The amount of isotropic etching is suitably in the range of 10 to 200 nm to the extent that pattern dimensions are not impaired by side etching. In this way, rounded holes are obtained at the upper and lower corners 23 and 26' as shown in Figure 3 (3).Subsequently, the mask 2
After removing 2, an insulating film is formed by thermal oxidation of, for example, Si0,27e, and a gate is formed of Po1yS i (
Polycrystalline silicon) 28 is formed to complete the MO8 capacitor shown in FIG. 3(4). The insulating film 27 may be a combination of several different insulating films.

SiQ by thermal oxidation as the insulating film 27! 5 nm.

S 1BN4 13 nm by CVD (Chemical Vapor Deposition)
In the case of using a film made of thermally oxidized Sin, 3im, a capacitor having a square planar structure with a -side of 0.5 wn had a withstand voltage of about 20V and a short-circuit occurrence rate of almost 0%. On the other hand, in a square with -side 0.5 square, one side is 2μm.
When a constant three-dimensional structure capacitor with 10,000 square holes i of 2 μm in depth is arranged using the above manufacturing method,
With a withstand voltage of 19.5 V, the occurrence rate of short circuits is also almost 0%.
Met. When a capacitor with a similar three-dimensional structure was fabricated without performing the conventional etching to round the corners, the occurrence rate of short circuits was more than 50%, and the withstand voltage varied between 10 and 19V.

In this way, it is important to round the sharp corners at the top and bottom ends of the hole to improve the yield of three-dimensional structure capacitors. It has become clear that it is possible to produce

It is thought that the causes of poor control in a three-dimensional structure capacitor with unrounded corners are that defects tend to occur in the film quality of the insulating film at sharp corners and that the electric field is concentrated at the corners.

Embodiment 2 FIG. 4 shows another embodiment of the present invention, and is a process diagram of a method in which light etching with side etching is performed before forming holes.

StO on the (100) crystal plane Si substrate 31.

A mask pattern consisting of two layers of 32, Si, N, and 33 is formed. The two-layer mask uses photoresist as a mask and uses CHF, CF, -H! Patterns can be formed without side etching by reactive sputter etching using mixed gas. S i02 f, the lower layer of the two-layer mask
After light side etching with a heptonic acid solution, Si is anisotropically etched using an alkaline solution such as hydrazine or KOH. In this way, the (1111 crystal plane is not etched and the (100)
Sloped side surfaces 34 are formed. As shown in FIG. 4(1), this side surface 34 is etched by anisotropic etching with a casing extending inward from the edge of the mask pattern toward the inside of the hole, and then etched to form the hole as described in Example 1. The shape is shown in FIG. 4. At the upper and lower ends of the hole 35, the slopes formed in the first etching are divided and remain, resulting in slopes 36 and 37 that round the corners.

The holes formed in this manner also had the same effects as in Example 1, and the capacitor formed above the holes had good electrical characteristics.

Embodiment 3 FIG. 5 is a process diagram of a method in which holes are formed and then light etching is performed with five side etching.

A two-layer mask pattern consisting of St Ot 42 and Si3N, 43 is formed in the same manner as in Example 2, and then holes 44v are formed.
An il-forming etching process is performed to obtain the shape shown in FIG. 5(1). Next, sto! +2-, after light side etching, light isotropic etching results in Figure 5 (2)
As shown in FIG. 3, a shape is obtained in which the upper and lower corners 45° 46 of the hole 44 are rounded by isotropic etching. This shape is the same as in Example 1, and by using a two-layer mask, the number of isotropic etching steps is reduced by one. It is obvious that the same effects as in the first embodiment can be obtained for devices such as capacitors.

Example 4 FIG. 6 is a structural diagram of an n-channel MO8 field effect transistor using holes formed by the manufacturing method of the present invention, which was obtained by the following manufacturing process. After forming an n-type diffusion layer 52' (l-) on a p-type Si substrate 51, a hole is formed in the gate portion using the manufacturing method described above.

Next, the gate insulating film ``''''''''''1. ．． A gate electrode 54 is formed in the hole through the sixth electrode 53.
The structure of the figure is obtained.

In such MO8 field effect transistors, the gate dimensions are determined by the hole dimensions11, and the gate is automatically aligned with the n-type diffusion layer that becomes the source and drain (self-alignment), so it is advantageous for high integration. It is. Cabinet,
As described above, since defects in gate breakdown voltage due to the corners of the holes are prevented, a highly reliable transistor can be obtained.

Note that the above explanation was made using a Si substrate as an example, but Q
The same is true when other semiconductor substrates such as aAs are used, and in devices other than capacitors and MO8 field effect transistors, rounding the corners of holes formed in the substrate to avoid electric field concentration improves device reliability. There is no denying that it is effective for improvement.

As explained above, according to the present invention, by rounding the corners of the holes formed in the semiconductor substrate, it is possible to prevent the concentration of electric fields at the corners and the occurrence of defects in the insulating film at the corners.
This has the effect of preventing breakdown voltage defects in MOS capacitors, MO8 field effect transistors, etc. and providing highly reliable semiconductor devices.

[Brief explanation of the drawing]

Figure 1 is a conventional planar structure MOS capacitor, Figure 2 is a cross-sectional view of a conventional three-dimensional structure MOS capacitor, Figures 3 and 4.
5 is a cross-sectional view showing the manufacturing process of the present invention, and FIG. 6 is a cross-sectional view of an MO8 field effect transistor according to the present invention. 23.36.45... Rounded corner above the hole, 26°3
7.46... Rounded part of the bottom corner of the hole. Agent Patent Attorney Toshiyuki Usuda! 1 Figure 3 High school 2nd figure Figure 3 (1) (2nd vine 3 Figure (3) (4) 8 Tomi 4 figure (1) (2)

Claims (1)

[Scope of Claims] 1. In a semiconductor device in which electric charge is stored or transported using an uneven portion formed on a semiconductor substrate, a structure is provided in which electric field concentration is prevented by removing the diagonal corners of the uneven portion. A semiconductor device comprising: 2. It is characterized by including the step of creating slopes at the upper and lower ends of the unevenness by performing etching with side etching either before or after performing anisotropic etching to form unevenness on the semiconductor substrate. A method for manufacturing a semiconductor device.