JPH08330532A - Dram cell device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DRAM cell device, including one-transistor memory cells as memory cells, capable of being manufactured with a packaging density which is necessary for 1 Gbit generation. SOLUTION: A DRAM cell device includes a vertical MOS transistor per memory cell, and a first source/drain region thereof is connected with a memory node of a memory capacitor, and a channel region 3 therof is surrounded by a gate electrode 13 in a ring shape, and a second source/drain region thereof is connected with a buried bit line. The DRAM cell device can be manufactured under the use of only two masks having a memory a cell area of 4F<2> . Here, F is a minimum structure size capable of being manufactured according to the technology at that time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM cell device and its manufacturing method.

[0002]

2. Description of the Related Art In DRAM cell devices, ie, dynamic random access memory cell devices, so-called one-transistor memory cells are almost exclusively used. The one-transistor memory cell includes a read transistor and a memory capacitor. In a memory capacitor, information is stored in the form of charge, which represents a logical value of 0 or 1. This information is read out via the bit line by driving the read out transistor via the word line.

As the memory density increases from memory generation to memory generation, the required area of a one-transistor memory cell must be reduced from generation to generation. This is also linked to the modification of the one-transistor memory cell, since the reduction in the structural size is limited by the smallest structural size F that can be manufactured in each technology. For example, up to the 1 MBit generation, both the read transistor and the memory capacitor have been realized as planar components. From the 4M Bit generation, further area reduction had to be performed by the three-dimensional arrangement of the read transistor and the memory capacitor. One possibility is to realize the memory capacitor in the trench (eg K. Yamada).
Others "Deeply dug capacitor technology for 4M Bit DRAM" International Electronic Devices and Materials IED
M85, Proc. 702).

Further, it has been proposed to configure the memory capacitor as a stack capacitor, a so-called multilayer capacitor (eg, K. Yamada et al., “1.28μ for 64M Bit DRAM Technology”).
m ² bit line shielded memory cell technology ”VLSI Symposium 1990 abstract, page 13). A structure of polysilicon, which is in contact with the substrate, is then formed on the word line, for example a crown structure or a cylinder. This polysilicon structure forms the memory node. A capacitor dielectric and a capacitor plate are provided at this node. This concept has the advantage of being compatible with a wide range of logical processes.

The area of the memory cell of the 1 GBit generation DRAM must be about 0.2 μm ² or less. The memory capacitor then has a capacitance of 20 to 30 fF. Such capacitance is 1 GBi
It is only feasible with the relatively complex structure of polysilicon structures in stack capacitors in the cell area available in generation t. These complex structures are additionally often difficult to manufacture due to their technology.

In addition, it has been proposed to increase the achievable capacitance per area by using a dielectric with a high dielectric constant. Paraelectric and ferroelectric substances are particularly suitable as the dielectric substance having a high dielectric constant (see, for example, International Patent Application Publication No. WO93 / 12542).

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide a DRAM cell device which includes a one-transistor memory cell as a memory cell and which can be manufactured at a mounting density required for the 1 GBit generation. is there. Furthermore, a manufacturing method for such a DRAM cell device must be shown.

[0008]

This problem is solved by a DRAM cell device according to claim 1 and a method for its manufacture according to claim 7. Embodiments of the invention are set out in the dependent claims.

The DRAM cell device according to the invention is provided with a one-transistor memory cell, in which the read transistor is constructed as a vertical MOS transistor. At that time, the first source / drain regions of the vertical MOS transistor are in contact with the main surface of the semiconductor substrate on which the DRAM cell device is realized. The second source / drain region borders the buried bit line.

The memory capacitor is arranged above the main surface. It includes a memory node electrically connected to the first source / drain region. The memory nodes may be configured in a planar or slightly more complex polysilicon structure as is known from stack capacitors.

In one embodiment, a capacitor dielectric is disposed on the surface of the first source / drain region bordering the major surface, and a capacitor plate is disposed thereon.
The first source / drain region bordering the main surface is
In this embodiment, it is additionally used as a memory node for the memory capacitor formed from the capacitor plate, the capacitor dielectric and the source / drain regions.
To achieve sufficient capacitance in small areas of memory nodes, 100 and 10 capacitor dielectrics are used.
It is advantageous to use materials with relative dielectric constants in the range between 00 and 00.

A channel region surrounded by a gate oxide and a gate electrode in a ring shape is arranged in the semiconductor substrate between the first source / drain region and the second source / drain region. The gate electrodes of the vertical MOS transistors adjacent to each other along the word line are adjacent to each other.

The DRAM cell device is preferably implemented in a semiconductor substrate that includes single crystal silicon at least in the range for the DRAM cell device. The substrate may be a disk made of single crystal silicon only,
It may be an SOI substrate including an insulating layer on a silicon disk and a thin single crystal silicon layer thereon.

The DRAM cell device according to the invention can be manufactured with a flat surface or with a surface having a flat topology when using the first source / drain regions as memory nodes. , A ferroelectric or paraelectric layer may be used as the capacitor dielectric. 50 for the ferroelectric and paraelectric layers
It has a high relative dielectric constant ε r in the range 0 to 1000. If these layers are deposited by sputtering, they can only be used on flat surfaces or surfaces with a flat topology. Even with CVD or sol-gel processes with better edge covering, the required thickness of the layers makes it impossible to produce complex three-dimensional structures. As the capacitor dielectric, preferably,
Barium-strontium-titanate, strontium-titanate or lead-zirconia-titanate are used. Further, International Patent Application Publication No. WO93 / 12
The materials known from 542 are suitable as capacitor dielectrics. With this dielectric having a high relative dielectric constant, the required capacitance of 20 to 30 fF can be achieved even on an area of about 0.1 to 0.4 μm.

It is within the scope of the invention that the word lines are formed from gate electrodes that are adjacent to each other.

The manufacture of the DRAM cell device according to the invention is
Preferably, it is carried out by a self-regulating method. Regions are formed in the semiconductor substrate which extend over the area for the DRAM cell device and have a corresponding doping for the source / drain regions, and the channel regions which are arranged between them. Subsequently, a first trench for cutting the region for the source / drain region, the channel region and the bit line is formed. The bit lines are thus defined during the etching of the first trench. After filling the first trench with an insulating structure, a second trench extending transversely thereto is etched, which cuts the region for the source / drain region and the channel region, Do not cut the line. Second
A second insulating structure is provided in the trench. continue,
The first insulating structure and the second insulating structure are exposed to the semiconductor material until the surfaces of the channel region and the doped regions for the first source / drain regions are exposed at the sides of the first trench and the second trench. It is selectively etched. The gate oxide is then formed. Subsequently, a doped polysilicon layer having substantially the same edge covering is formed to form the gate electrode.

The first trench is formed as having a smaller width than the second trench. The thickness of the polysilicon layer is selected such that the polysilicon layer fills the first trench but not the second trench. Anisotropic back etching of the polysilicon layer partially exposes the surface of the second insulating structure in the second trench. The doped polysilicon spacers then remain on the sides of the second trench. During this anisotropic back etching, the polysilicon layer remaining in the first trench is also eroded, but the surface of the first insulating structure in the first trench is covered with the doped polysilicon. Stay in the state. In this way, the gate electrode results as a ring-shaped structure made of doped polysilicon, the structural parts being respectively arranged in the first trenches belonging to two adjacent gate electrodes and Connect to each other in manufacturing.

The gate electrode is finally covered by a third insulating structure. The third insulating structure fills the first trench and the second trench almost completely above the gate electrode. In the second trench, the third insulating structure insulates the gate electrodes arranged on the opposite side surfaces. The capacitor dielectric and the capacitor plate are subsequently coated. The third insulating structure is preferably formed by deposition of a layer and back-etching of this layer, which also have approximately the same edge covering.

Due to the self-aligned fabrication, the width of the first and second trenches is different so that the polysilicon layer fills the first trench but not the second trench. Is important. This allows structuring of the gate electrodes which simultaneously form the word lines without photolithographic processes. This method requires only two photolithographic processes. The etching of the first trench and the etching of the second trench are each performed by a trench mask. However, these trench masks are completely non-critical in their adjustment.

To etch the first trench,
It is particularly advantageous to use a first trench mask manufactured as follows. A first SiO ₂ layer is deposited and structured using the photolithographic method. in addition,
A _second SiO ₂ layer having approximately the same edge covering is deposited so that SiO ₂ spacers that define the width of the first trench are produced on the sides of the structured first SiO ₂ layer, and are also anisotropic. To be etched. In this way, the minimum manufacturable structural dimension F in each technology is
It is possible to manufacture a first trench having a width smaller than the width of In this way the width of the second trench can be the smallest structural dimension F in the respective technology, eg 0.25 μm, and the width of the first trench can be twice the spacer width smaller. . This is because the structure formed in the first SiO ₂ layer is also limited by the minimum structure width F. This produces a DRAM cell device having 4F ² occupied space per memory cell.

It is within the scope of the invention to epitaxially grow the source / drain and channel regions and the regions for the bit lines as blanket layers. In doing so, when using a substrate containing single crystal silicon within the DRAM cell device, CoSi epitaxially grown under the second source / drain regions to improve the conductivity of the bit lines. A conductive layer of ₂ is formed. This conductive layer is likewise cut during the etching of the first trench and is also a component of the bit line.

[0022]

The present invention will be described in more detail with reference to the embodiments shown in the drawings.

The starting materials are range 1 consisting of, for example, p-doped monocrystalline silicon having a doping concentration of, for example, 10 ¹⁷ cm ^-3 and n ⁺ -doped silicon having a doping concentration of, for example, 10 ²⁰ cm ^-3. And a second layer ³ of p-doped silicon having a doping concentration of, for example, 3 × 10 ¹⁷ cm ^−3.
And n with a doping concentration of, for example, 10 ²¹ cm ^{−3
And a} third layer 4 of ⁺ doped silicon (see FIG. 1). The first layer 2, the second layer 3 and the third layer 4 are preferably formed by epitaxial growth. The third layer 4 forms the major surface 5 of the substrate. The first layer 2 has a thickness of, for example, 500 nm, the second layer 3 has a thickness of, for example, 200 nm, and the third layer 4 has a thickness of, for example, 1 nm.
It has a thickness of 00 nm.

A first SiO ₂ layer 6 is coated and structured on the major surface 5. The first SiO ₂ layer 6 is deposited to a thickness of 150 nm by the TEOS method, for example. First S
A photoresist mask (not shown) is used to structure the iO ₂ layer 6. Structuring takes place in a dry etching process. At that time, the main surface 5 is exposed.

After removal of the photoresist mask, SiO ₂ spacers 7 are formed on the vertical sides of the structured first SiO ₂ layer 6. In addition, a second SiO ₂ layer is deposited by TEOS to a thickness of, for example, 80 nm. A second Si selective to silicon by anisotropic dry etching
Spacers 7 are formed from the O ₂ layer (see FIG. 2).

Structured first SiO ₂ layer 6 and S
The first trenches 8 are etched in an anisotropic dry etching process using the SiO ₂ spacers 7. As the etching process, for example, HBr, NF ₃ , H
e and O ₂ are suitable. The first trench 8 is, for example, 1
It is formed with a depth of 000 nm. Thereby the first trench 8 extends into the p-doped region 1 of the semiconductor substrate. The first trench 8 cuts through the first layer 2, the second layer 3 and the third layer 4. Parallel to the main surface 5, the first trench 8 has a strip-shaped cross section. The first trenches 8 extend substantially parallel over the entire cell area. The first trenches 8 are, for example, 90 nm wide and 6
It has a length of 4 nm. The spacing between the centers of adjacent first trenches 8 is, for example, 500 nm, which is the minimum structural dimension F = 250 nm of the technology used.
Equivalent to double.

Then, for example, NH ₄ F (30%) / HF
First structured by wet etching (6%)
The SiO ₂ layer 6 and the SiO ₂ spacer 7 are removed.

The first trench 8 is filled with the first insulating structure 9 (FIG. 7) by depositing another SiO ₂ layer with a layer thickness of 100 nm by the TEOS method. To form the first insulating structure 9, the SiO ₂ layer is back-etched and planarized until the main surface 5 is exposed outside the trench 8. Back etching is for example CH
It is performed by a dry etching process using F ₃ and O ₂ .

Subsequently, another trench mask used as an etching mask for etching the second trench 10 is formed by the photolithography method (see FIG. 3). To form the second trench 10, an etching method that selectively erodes silicon with respect to SiO ₂ must be used. Especially for that purpose HB
r, Cl ₂ , He, O ₂ are suitable. The second trench 10 extends, for example, perpendicularly to the first trench 8 (FIG. 3 shows a cross section through the device perpendicular to FIG. 2). It is important that the silicon on the sidewalls of the first insulating structure 9 is removed without residue during the etching of the second trench 10 in order to prevent a short circuit later from occurring. To ensure this, a wet etching, for example with Cholin, is also added after the anisotropic dry etching. The second trench 10 is, for example, 500
Etched to a depth of nm. The second trench 10 extends into the first layer 2 but does not cut it. In the completed DRAM cell device, the through parts of the first layer 2 each act as a bit line. Parallel to the major surface 5, the second trench 10 has a strip-shaped cross section. They extend approximately parallel and have a width of 250 nm and a length of 128 μm. The center interval between the adjacent second trenches 10 is, for example, 500 nm, that is, 2F.

After the trench mask has been removed, the second trench 10 has a layer thickness of, for example, 300 nm and is S-doped by TEOS.
Filled by depositing the iO ₂ layer 11 '.

The SiO ₂ layer 11 'is back-etched by anisotropic dry etching using CHF ₃ and O ₂ , for example. At that time, the second insulating structure 11 is formed in the second trench 10 (FIG. 4). The anisotropic dry etching process attacks SiO ₂ selectively with respect to silicon. The etching process is continued until the surface of the second insulating structure 11 is located 400 nm below the main surface 5. The dry etching process also erodes the first insulating structure 9, the surface of which is located at the same height as the surface of the second insulating structure 11 after the dry etching process. The first trench 8 and the second trench 1 during back etching
The surfaces of the third layer 4 and the second layer 3 bordering the sides of the respective trenches in 0 are completely exposed. If necessary, this is ensured by an additional wet etching step, for example with HF (1%).

To form the gate oxide 12 on the surface of the second layer 3, a subsequent thermal oxidation, for example at 800 ° C., is carried out. Gate oxide 12 is formed to have a thickness of 5 nm, for example. Upon thermal oxidation, a 5 nm thick SiO ₂ layer forms on all exposed silicon surfaces. Finally, the in-situ doped polysilicon layer 13 'is deposited. A doped polysilicon layer, for example an n-doped polysilicon layer with a doping concentration of 10 ²¹ cm ^{-3 with} phosphorus, is deposited to a thickness of 80 nm (see FIG. 4). The doped polysilicon layer 13 'is deposited as having the same edge covering. As a result, the second trench 10 is not filled. However, at that time, the first trenches 8 having a smaller width than the second trenches 10 are filled.

To form the gate electrode 13, the doped polysilicon layer 13 'is back-etched in an anisotropic dry etching process. At that time, the surface of the second insulating structure 11 is exposed in the second trench 10. The portion of the gate electrode 13 arranged in the second trench 10 occurs as a spacer along the side surface of the second trench 10. Anisotropic etching is performed using, for example, HBr, Cl ₂ ,
He, O ₂ is used, with a polysilicon thickness of 150 nm being etched. That is, the etching is strongly covered so that the side surfaces of the third layer 4 covered with the gate oxide are exposed within the second trenches 10 (see FIG. 5). The thin SiO ₂ layer formed during gate oxidation on the surface of the third layer 4 within the major surface 5 acts as an etching stop during anisotropic etching.

During the anisotropic etching to form the gate electrode 13, the doped polysilicon layer 13 ′ in the first trench 8 filled with the doped polysilicon layer 13 ′ has a main surface. Back etching is performed to the lower side of the height of 5 (see FIG. 7). Each of the gate electrodes 13 has a ring shape surrounding a portion of the second layer 3 bounded by two adjacent first trenches and two adjacent second trenches (see FIG. 6). First trench 8
Has a small width, the adjacent gate electrodes 13 are connected to each other via the portions arranged in the first trench 8 in each case.

Another SiO ₂ layer is, for example, 1 by the TEOS method.
It is deposited to a thickness of 50 nm and anisotropically back-etched by a dry etching method. Thereby, the third insulating structure 14 is formed. The third insulating structure 14 insulates the gate electrodes 13 arranged on opposite side surfaces of the same second trench 10 from each other (see FIG. 5). The third insulating structure 14 covers the gate electrode 13 in the first trench. The second trench 10 is likewise substantially filled with the third insulating structure 14. Only a small amount of non-planarity remains, which can be avoided by depositing the SiO ₂ layer with a larger thickness.

Subsequently, the capacitor dielectric 15 is coated. The capacitor dielectric 15 is made of a material having a high relative dielectric constant εr. Preferably the capacitor dielectric 15 is formed from one of barium-strontium-titanate, strontium-titanate or lead-zirconia-titanate. These ferroelectric and paraelectric layers are for example sputtered or by CV
It is coated by the D or sol-gel method. The capacitor dielectric 15 is formed with a layer thickness of 50 nm, for example.

If the silicon of the third layer 4 is compromised by the material of the capacitor dielectric 15, the third layer 4 is
Between the capacitor and the capacitor dielectric 15, for example TiN, P
It is within the scope of the invention to provide an intermediate layer of t, W or RuO ₂ .

If the leakage current in the capacitor dielectric is unacceptable for memory applications, the capacitor dielectric may be structured. However, this requires an additional mask.

A capacitor plate 16 is coated on the entire surface of the capacitor dielectric. Therefore, for example, TiN, P
A conductive layer of t, W, RuO ₂ or n ⁺ doped polysilicon is deposited. The capacitor plate 16 is formed to have a thickness of 100 nm, for example.

In the DRAM cell device, each memory cell is bounded by an adjacent first trench and an adjacent second trench, and is disposed in the first layer as a source / drain region. 2. A read transistor comprising a vertical MOS transistor including a portion of the second layer 3 as a channel region and a third layer 4 as a source / drain region. The through portion of the first layer 2 (see FIG. 5) acts as a bit line. Adjacent to the bit line direction perpendicularly, and also the first
The gate electrodes 13, which are connected to each other within the trenches 8, form a buried word line. Adjacent word lines are insulated from each other by the third insulating structure.
The memory cell further comprises a memory capacitor formed from the respective part of the third layer 4 as a memory node, the capacitor dielectric 15 and the capacitor plate 17.

Only two masks are needed to fabricate a DRAM cell device. A first mask for structuring the first SiO ₂ layer 6, a second mask for etching the second trenches 10. If the structures in both masks are manufactured with the respective technology corresponding to the smallest manufacturable structure size F, there will be an occupied area of 4F ² per memory cell. Based on a technology with F = 0.25 μm, there will be occupying 0.25 μm ² per memory cell. Both masks used are non-critical with respect to their adjustment. No additional mask is required for the structuring of the gate electrode and thus also of the word line.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor substrate having a first structured SiO ₂ layer.

FIG. 2 is a cross-sectional view of the semiconductor substrate after formation of the first trench mask and etching of the first trench.

3 is a cross-sectional view perpendicular to the cross-section shown in FIG. 2 through the semiconductor substrate after etching the second trench and filling the second trench.

4 is a cross-sectional view shown in FIG. 3 through the semiconductor substrate after formation of the gate oxide and deposition of the doped polysilicon layer.

5 is a cross-sectional view shown in FIG. 4 through the semiconductor substrate after formation of the gate electrode and completion of the memory capacitor.

6 is a sectional view through the semiconductor substrate indicated by VI-VI in FIG.

FIG. 7 is a sectional view through the semiconductor substrate indicated by VII-VII in FIG.

[Explanation of symbols]

 2 2nd source / drain region 3 Channel region 4 1st source / drain region 5 Main surface 8 1st trench 9 1st insulating structure 10 2nd trench 12 Gate oxide 13 Gate electrode 15 Capacitor dielectric 16 Capacitor plate

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Franz Hoffmann, Federal Republic of Germany 80995 Miyunchen Herberg Schyutraße 25B

Claims (14)

[Claims] 1. A memory cell, each comprising a read transistor and a memory capacitor, each read transistor being configured as a vertical MOS transistor integrated on a semiconductor substrate, the first source / source of which is The drain region (4) borders the major surface (5) of the substrate and its second source / drain region (2) borders the bit line (2) buried in the substrate, and its gate oxide. (12) and gate electrode (13)
Surrounds the channel region (3) arranged between the source / drain regions (2, 4) in a ring shape, and the gate electrodes (13) of the vertical MOS transistors adjacent to each other along the word line are mutually adjacent. DRAM cell device, characterized in that it has a memory node having a memory node connected to a first source / drain region (4) which is adjacent to the main surface (5). . 2. A vertical MOS adjacent along a bit line.
A gate electrode (13) in which the second source / drain regions (2) of the transistor are connected to each other through the doped region and the word lines are respectively bordering each other.
The DRA according to claim 1, wherein the DRA is formed of
M cell device. 3. The semiconductor substrate comprises monocrystalline silicon at least within the area of the DRAM cell device, and the source / drain regions (2, 4) and the channel region (3) are arranged in the semiconductor substrate as doped regions. The bit line is formed as a layer of doped regions (2) in the semiconductor substrate and / or of epitaxially grown CoSi ₂ , and the gate electrode (13) comprises doped polysilicon. A DRAM cell device according to claim 1 or 2, characterized in that: 4. The main surface of each of the memory capacitors (5)
A first source / drain region (4) as a memory node bordering on the memory node, a capacitor dielectric (15) located above the memory node, and a capacitor plate (16).
4. The DRAM cell device according to claim 1, wherein the DRAM cell device comprises: 5. The capacitor dielectric (15) is barium-
5. The DRAM cell device of claim 4 including one of strontium-titanate, strontium-titanate or lead-zirconia-titanate. 6. The capacitor dielectric (15) is constructed as a continuous layer.
DRAM cell device as described. 7. A memory cell is manufactured by one read transistor and one memory capacitor, respectively, and a bit line (2) buried in the semiconductor substrate is manufactured, and the read transistor is formed in the semiconductor substrate as a vertical MOS transistor. The first source / drain regions (4) are in contact with the main surface (5) of the semiconductor substrate, and the second source / drain regions (2) are filled with bit lines ( The channel region (3), which is bordered by 2) and whose gate oxide (12) and gate electrode (13) are arranged between both source / drain regions (2, 4), has a ring shape. Vertical MOS transistors that surround and are adjacent to each other along the word line are arranged such that their gate electrodes (13) are adjacent to each other. A DRAM characterized in that the memory capacitors are each manufactured by memory nodes electrically connected to the first source / drain regions (4).
Manufacturing method of cell device. 8. A first layer (2) in which the semiconductor substrate is doped to a first conductivity type and a second layer (2) to a second conductivity type opposite to the first conductivity type. 3) and a third layer (4) which is doped to the first conductivity type and borders the major surface (5), each strip-shaped extending substantially parallel to each other, and A first trench (8) that cuts the first layer (2), the second layer (3) and the third layer (4) is etched, and the first trench (8) is first.
A first layer (2) without being cut off by cutting the first layer (2), each of which is filled with an insulating structure (9) of the type and extends in parallel in strips and intersects the first trench (8). The second trench (10) reaching into the interior is etched, and the second trench (10) becomes the second insulating structure (1
1) and the width of the second trench (10) is greater than the width of the first trench (8) and is structured on the sides of the first trench (8) and the second trench (10). Until the surfaces of the second layer (3) and the third layer (4) are exposed, the first insulating structure (9) and the second insulating structure (11) are selective to the semiconductor material. A gate oxide (12) is formed to cover at least the exposed surface of the second layer (3), and the gate electrode (1) is formed.
A doped polysilicon layer (13 ') with substantially matched edge covering is produced to form 3), the thickness of which fills the first trench (8) but not the second trench (10). And a doped polysilicon spacer is formed on the sides of the second trench, and a second insulating structure (1) is formed in the second trench.
The surface of 1) is partially exposed, while the surface of the first insulating structure in the first trench (8) remains anisotropically backed so that it remains covered by the doped polysilicon. Method according to claim 7, characterized in that a third insulating structure (14) is produced which is etched and covers the gate electrode (13). 9. A first trench mask is used to etch the first trench (8), a first SiO ₂ layer (6) is deposited to form the first trench mask, and A second SiO ₂ layer, which is structured using the photolithographic method and has substantially conforming edge covering, is deposited and the structured first SiO ₂ layer (6)
SiO ₂ spacer occurs in the side surface, whereby as the width of the first trench (8) is defined, The method of claim 8, characterized in that it is back etched anisotropically. 10. The semiconductor substrate comprises monocrystalline silicon at least within the DRAM cell device, and the first layer (2), the second layer (3) and the third layer (4) are grown epitaxially. 10. The method according to claim 8 or 9, characterized in that: 11. A conductive layer of CoSi ₂ epitaxially grown under the first layer (2) is produced,
11. Method according to claim 10, characterized in that the conductive layer is cut during the etching of the first trench (8). 12. A capacitor dielectric (15) above the first source / drain region (4) so that the first source / drain region (4) simultaneously acts as a memory node to form a memory capacitor. ) And the capacitor plate (16) are coated.
The method according to any one of 1 to 11. 13. The capacitor dielectric (15) according to claim 12, characterized in that it is formed from one of barium-strontium-titanate, strontium-titanate or lead-zirconia-titanate. Method. 14. The capacitor dielectric (15) is formed as a through layer.
3. The method described in 3.