JPH08171463A - Data read method in disk array device, and disk array device - Google Patents

Abstract

PURPOSE: To reduce the read time of data in the disk array system of RAID (level 3). CONSTITUTION: A microprocessor 6 responds to a read request from a CPU 1 and instructs the read of the plural pieces (n) of sub data for constituting the data to be read and error correction codes for them to plural drives 13. A parity generation circuit 10 restores the other sub data which are not read yet by using the parity generation circuit 10 from a part of the sub data and the error correction code which are read at the point of time when a part of the sub data and the error correction code are read to a drive selection part 11. The microprocessor 6 combines a part of the sub data which are already read and the other restored sub data and supplies them to the CPU 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reading method in a disk array device and other disk array devices described therein.

[0002]

2. Description of the Related Art A disk storage device (hereinafter referred to as a drive) using a non-volatile storage medium such as a magnetic recording medium or an optical recording medium is generally used as a secondary storage device of a current computer system. Among them, a disk array, which is relatively inexpensive and uses a plurality of drives with small capacities, has attracted attention because of its large capacity, low price, and high reliability.

In the disk array, the cost is reduced by using a large number of relatively inexpensive drives. Further, by accessing these drives in parallel, the data transfer time between the CPU and the drives is reduced. In addition, it also stores information for disaster recovery,
When a drive fails, the data on that drive is recovered from the data on the other drive and the disaster recovery information. This improves the reliability of the device.

For example, D. Patterson, G. Gibson, and
RH Kartz, "A Case for RedundantArrays of Inexpen
sive Disks (RAID) ", ACM SIGMOD Conference, Chicag
According to O., IL, (June 1988), pp.109-116 (hereinafter referred to as the first prior art), in a RAID level 3 disk array, the write data associated with one write request supplied from the CPU is written. Data is divided into a plurality of sub data, and parity data is created from these sub data. These sub data and parity data are stored in parallel in a plurality of different drives. When the CPU issues an instruction to read data, a plurality of sub-data forming the data are read in parallel from different drives, combined with each other, and transferred to the CPU. An error correction code (ECC) determined by each sub-data or parity data is added to each sub-data and parity data, and each sub-data and parity data is stored in one drive. Therefore, when the sub data and the parity data are read from the drive, the ECC can be checked to detect and correct the error of the sub data and the parity data. If an error is detected in a large range that cannot be corrected by ECC, it is determined that the drive has a failure. In addition, regarding drive failure,
If no response is returned from the drive when issuing a read or write request from the initiator, the initiator determines that the drive has failed. As described above, the drive failure is detected in the disk array. By such detection, if the sub data held in that drive cannot be read due to the failure of one of the drives, it corresponds to the remaining sub data and its sub data from the drives other than that drive. Parity data is read, sub-data that cannot be read from these data is recovered, sub-data that has already been read is combined with this recovered sub-data, and the data obtained as a result of the combination is supplied to the CPU.

In Japanese Patent Laid-Open No. 4-228153 (hereinafter referred to as the second prior art), in addition to detecting a drive failure due to a command error as described above, parity data is created from sub data read from each drive, and A method of detecting a drive failure by comparing the created parity data with the parity data read from the drive is disclosed.

Generally, a set of a plurality of data and parity data generated from them is called a parity group. In general, other error correction codes can be used instead of parity data. In that case, the set is called an error correction data group. Further, a set of a plurality of drives holding data belonging to the same error correction data group is called a logical group.

As described above, in the conventional disk array,
Data access time is shortened by accessing multiple drives in parallel.

Incidentally, JP-A-2-56019 (hereinafter referred to as "3rd
Prior art) or JP-A-3-305928.
(Hereinafter, referred to as a fourth conventional technique) discloses a disk array called a mirror type, which is different from the RAID 3 disk array. In this device, in processing a write request from the CPU, the data supplied from the CPU is written in parallel to the two drives. CPU
In the processing of the read request from, the two drives are accessed in parallel and the data requested by the read request are read in parallel. When the data requested by one of these drives is supplied before the other, the data is supplied to the CPU. In this way, the waiting time due to the rotation of the drive is reduced.

[0009]

In the level 3 disk array, when processing a read request transferred from the CPU, it is necessary to read all of the plurality of sub-data forming the data designated by the request. Normally, multiple drives rotate asynchronously. Therefore, the read time of these sub data is dominated by the read time of the sub data having the longest rotation waiting time. Therefore, RAID
When reading data from the disk array of No. 3, when the number of drives increases, the waiting time of one rotation at the maximum may be stochastically increased. Therefore, it is desirable to shorten the data read time in the level 3 disk array.

In the mirror type disk arrays shown in the third and fourth prior arts, since the same data is held in two drives, the data read is more than in the case where the data is held in one drive. It often happens that the time is shortened. However, if the rotation waiting times of the two drives are both long, the reading time is not shortened even by this method.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a data reading method and a disk array suitable for the method which can more surely shorten the data reading time in the level 3 disk array.

[0012]

Therefore, in the data reading method according to the present invention, the write data supplied from the host device is divided according to RAID3, the plurality of sub-data obtained and the error correction generated from them are divided. When the host device requests to read the written data after writing the code to different drives, the read request of the error correction code is issued to a plurality of drives together with the sub data, and When the error correction code is read before the sub data of the copy is read, at that time, the reading is performed from the already read partial sub data and the read error correction data. Recovers delayed sub-data, combines recovered sub-data with some previously read sub-data, and reads Data is formed, and supplies to the host device. As the error correction code, for example, parity data including 1-bit parity bit corresponding to 1-bit of each of n sub-data can be used. It is also possible to use a plurality of different error correction codes.

[0013]

According to this method, the requested read data is generated by using the error correction code read before the sub data whose reading is delayed before being read. The data requested by the device can be supplied without waiting for the sub-data whose reading has been delayed to be read.

When a plurality of different error correction codes are used, and when a plurality of error correction codes are read before a plurality of sub data, they are read without waiting for the reading of the plurality of sub data. Not able to recover multiple sub data.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A disk array according to the present invention will be described below in more detail with reference to some embodiments shown in the drawings. In the following, the same reference numbers represent the same or similar items. <Embodiment 1> In FIG. 1, 2 is a control unit and 13 is a drive. The control unit 2 executes write requests from the CPU 1 and accesses the drive specified by those requests. The plurality of drives 13 are the plurality of logical groups 1
It is divided into four. In this embodiment, each logical group 14 is composed of five drives 13, but the present invention is not limited to this number of drives.

In the control unit 2, reference numeral 4 denotes a channel interface circuit (CH I) which receives a request issued from the CPU 1 or supplies data to the CPU 1.
F) 5 is a data transfer control circuit (DCC) for controlling transfer of data received from the CPU 1 or data to be supplied thereto, and 6 is an internal part of the control unit 2 in accordance with a write request and a read request received from the CPU 1. Is a microprocessor (MP) that controls the operation of the circuit of FIG.
Reference numeral 9 is a cache memory that temporarily holds the write data received from the CPU 1 and the data read from the drive, and also holds an address conversion table and the like described later. 10 is a parity generation circuit (PG), 1
Reference numeral 1 is a drive selection circuit, and 100 is a recovery data combining circuit.

The parity generation circuit 10 generates parity data for a plurality of sub-data obtained by dividing the data to be written at the time of writing the data, and at the time of reading the data, one of the drive If there is an error in the sub data read from or one of the drives has failed,
When the sub data of the drive cannot be read, it has a function of recovering the sub data having the error or the sub data in the drive in which the failure has occurred.

The recovery data combining circuit 100 is a circuit for combining such recovered sub data with other read normal sub data.

In this embodiment, the control unit 2 controls the writing and reading of data to these logical groups so that each logical group constitutes a RAID 3 disk array. That is, the write data supplied from the CPU 1 is divided into a plurality of (four in this embodiment) sub-data, and parity data of these sub-data is generated as an error correction code for these sub-data. The sub data and the parity data are written in different drives. This parity data is used to recover the data in the drive in which a failure has occurred when one of the drives has a failure.

In this embodiment, this parity data is also used when reading normal data. That is, CP
When U1 issues a read request for this write data, it issues an instruction to read the four sub data and parity data forming this write data. If the reading of some of these sub-data is delayed, the sub-data is recovered from the read-completed sub-data and parity data before it is read, and the recovered sub-data is read and not completed. It is used instead of the sub data of. Thus, even if the reading of a part of the sub-data is delayed, the data specified by the read request can be sent to the CPU 1 before it is read.

More specifically, the write data from the CPU 1 is divided into four sub data, parity data for these sub data is generated, and these sub data and the generated parity data are combined into one logical group. Write to the five drives that belong to it.

When the CPU 1 issues a read request later, the read request is issued to the five drives in which the four sub-data forming the data designated by the request and the parity data for them are stored.
Each drive responds to these read requests and the reading is completed in sequence. In the drive in which reading has been completed in this order, it is determined whether or not all the sub-data forming the data designated by the read request are included.

If any of the sub data is not included, it means that the parity data is read before the sub data whose reading is not completed. In this case, the unread sub-data is recovered from the already read partial sub-data and parity data, and the recovered sub-data and the already-read partial sub-data are recovered. The data is combined and the data specified by the read request is generated and sent to the CPU 1.

When all the sub-data is included in the read-completed data as described above, or when there is sub-data that has not been read yet, the number of sub-data required to recover the sub-data is as large as possible. The circuit that determines whether the reading of sub data and parity data is complete
It is included in the drive selection unit 11. The details of the operation of this embodiment will be described below.

(Data Write Operation) The write request supplied from the CPU 1 is received by the channel adapter 4 via the line 3 and supplied to the microprocessor 6. The write data accompanying this write request is further held in the cache memory 9 via the data control circuit 5. In response to the write request, the microprocessor 6 divides and reads into a plurality of sub-data constituting the write data, four sub-data in this embodiment, and restores the sub-data via the line 9A. It is supplied to the data combination circuit 100. Recovery data combining circuit 100
Is instructed by the microprocessor 6 so that the line 9A,
This is a switch for switching the connection between 10A and 9B. When writing data, each sub-data read from the cache memory 9 to the line 9A is directly transferred to the parity generation circuit 10 via the line 100A.

As shown in FIG. 2, the parity generation circuit 10
Is an active switch 140 and an exclusive OR circuit 13
0, a switch 120. Among them, the exclusive OR circuit 130 is used to generate parity data at the time of writing data and to recover sub data having an error or sub data in a drive in which a failure has occurred at the time of reading data. Active switch 14
0 and the switch 120 are switch circuits that switch the input and output of the exclusive OR circuit 130 according to the instruction of the microprocessor 6.

When the microprocessor 6 transfers a plurality of sub-data to be written to the parity generation circuit 10,
Direct the active switch 140 to line 100A and line 3
00 is directly connected to transfer all sub data to the EOR circuit 130. EOR circuit 13 that received all sub data
At 0, the exclusive OR of the corresponding bits of each sub data is taken, and the parity data for these sub data is created. The EOR circuit 130 transfers the created parity data and the plurality of sub-data relating to the creation of the parity data to the switch 120 via the line 200A. In the data write operation of the microprocessor 6, the switch 120 transfers each sub data and parity data on the line 200 to the line 10A as they are.

Although each sub data and parity data is added with an ECC determined by the respective data as in the prior art, it is stored in the drive.
This circuit is omitted here for simplification. E attached to each sub data or parity data
In the CC, if an error occurs when the sub data or parity data is read, as in the conventional technique,
It is used to correct errors in the sub data or parity data. Hereinafter, these ECCs are treated as a part of each sub-data or parity data, and unless otherwise required, these ECCs will not be mentioned.

The microprocessor 6 determines the drive and the storage location in the drive to which these sub data and parity data should be written, using the address table (address conversion) (step 42). This table is held in the cache memory 9 and has the contents shown in FIG. 4, for example. The CPU 1 designates the name of the write data as a logical address as a part of the write request, and from this logical address 20, five drive numbers 21 for these sub-data and parity data and common to these data are determined. The in-drive address 22 is determined. In the figure, the name DATA #
The drive number for the sub data for writing 1 is
Drives # 1 to # 5, with internal drive number DAD
It shows that it is R1. In this embodiment, the sub-data is a drive dedicated to data, for example, # 1-4 or #
The parity data is stored in n− # n + 4, and the parity data is stored in a drive of the parity data, for example, # 5 and # n + 5.
In the figure, the cache address 23 indicates the address in the cache memory 9 that holds the write data. The microprocessor 6 gives an instruction to write these sub data and parity data.

As shown in FIG. 3, the drive selecting section 11 includes a selector buffer 18 formed of a buffer area provided corresponding to the five drive interfaces 12,
The selector buffer 18 includes a switch circuit 17 that connects the cache memory 9 and the parity generation circuit 10 and a response determination circuit unit 16.

Since the microprocessor 6 has previously converted the address using the address table, the microprocessor 6 recognizes the drive to which each sub data and the parity data should be written and the storage position in the drive. Therefore, the microprocessor 6 sends the sub data and the parity data to the switch circuit 17 via the line 10A and controls the switch circuit 17 to transfer them to the drive interface circuit 12.

Each drive interface circuit 12 has an S
Sub data or parity data to be written via the CSI bus 15 is written to a storage location designated by an in-drive address in the drive having the drive number obtained by the above-mentioned address conversion in accordance with the SCSI write processing procedure. In this way, the plurality of sub data constituting the write data supplied from the CPU 1 and the parity data for them are written to the plurality of drives belonging to the same logical group.

(Data Read Operation) The data read operation will be described below with reference to the flow chart shown in FIG.

When a read request is issued from the CPU 1 (step 41), the microprocessor 6 holds a plurality of sub-data forming the data and parity data for them from the name of the data designated by the read request. The number of the drive to be used and the address in the drive are converted (step 42). The method is performed using the address conversion table (FIG. 4) as in the case of the write request.

The microprocessor 6 uses these addresses to instruct the response determination circuit section 16 in the drive selection section 11 to read out these sub data and parity data (step 43). Response determination circuit unit 16
Is composed of a judgment processor 101 and a parity register 102, and the operation of the application judgment circuit 16 described below is executed by the judgment processor 101.

The response determination circuit section 16 follows this instruction and
A sub data or parity data read request is instructed to each drive interface (step 43).

The response determination circuit section 16 registers the drive number that issued this read request (step 44).

Each drive interface circuit 12 is an SC
A read command is issued to each desired drive via the SCSI bus 15 in accordance with the SI bus read processing procedure.

After the access processing is completed, each drive 13 issues a completion report of the access processing to the drive interface circuit 12, and the drive interface circuit 12
Notifies the response determination circuit unit 16 in the drive selection unit 11 of the completion report of the access processing of the drive 13.

The response determination circuit section 16 instructs the drive interface circuit 12 to transfer data into the selector buffer 18, and the drive interface circuit 12 stores the read sub data or parity data in the selector buffer 18 ( Step 45).

After the sub data from the drive 13 is stored in the selector buffer 18, the response judgment circuit section 16 makes a judgment (step 45).

FIG. 6 shows a flow chart of a concrete judging method in the response judging circuit section 16 at this time.

The response determination circuit unit 16 stores sub data or parity data in the selector buffer 18 from the interface circuit 12 (step 50), and then checks whether the drive 13 that has transferred the data is the drive 13 which has issued the read request. (Step 51). As shown in step 44 of FIG. 5, the microprocessor 6 is
At the same time as instructing the drive interface circuit 12 to issue a read request to the drive 13, the drive number that issued the read request is registered in the response determination circuit unit 16 in the drive selection unit 11. It is compared whether or not the drive 13 that issued the access processing completion report is the same as the registered drive number. If drive 1 has not issued a read request
If it is the completion report from 3, the response determination circuit unit 16 reports this completion report to the microprocessor 6 as a completion report of the writing process (step 65).

When this completion report is from the drive 13 to which the read request is issued, the response determination circuit section 16 reports it to the microprocessor 6 as a read report completion report (step 52). Next, the response determination circuit unit 16 adds 1 to the determination counter (step 53). The response determination circuit unit 16 determines whether the value of the determination counter added with 1 is 4 or not.
Is determined (step 54). If the counter value is not 4 in the determination in step 54, the response determination circuit unit 16 holds the sub data or parity data in the selector buffer 18 as it is (step 64).

When the result of the judgment in step 54 is that the judgment counter value is 4, the response judgment circuit section 16 judges whether the parity data is stored in the selector buffer 18 (step 55). When the parity data is stored in the selector buffer 18 according to the determination in step 55, the parity data is stored in the selector buffer before any of the four sub-data necessary to compose the data to be read is read. The data has been read.

In this embodiment, the disk array 2 is level 3
Therefore, the parity data is stored in the dedicated drive 13. Specifically, all the parity data of the logical groups corresponding to the drives # 5 or # 5 + n in FIG. 1 are stored. Therefore, the completion report of the access processing from the drive interface circuit # 5 is stored in the parity register in the response determination circuit unit 16, and the parity register in the response determination circuit unit 16 is checked to see Step 5
The judgment of 5 is possible.

If parity data is stored in the selector buffer 18 according to the determination in step 55,
It reports to the microprocessor 6 that the parity data is stored in the selector buffer 18 (step 5
6), the selector buffer 18 and the parity generation circuit 10 are connected to the switch circuit 16 according to an instruction from the microprocessor 6.
To connect (step 57). When this connection is completed, the microprocessor 6 transfers the sub data (this is three sub data in this embodiment) read from the selector buffer 18 to the parity generation circuit 10 and the parity data (step 58), and The read sub data is recovered by the parity generation circuit 10 (step 5).
9). When recovering the unread sub-data, the microprocessor 6 transfers the read three sub-data and the recovered sub-data to the cache memory 9 (step 60).

Data recovery by the parity generation circuit 10 is performed as follows.

When the parity data is read before reading any of the sub data as described above, when the microprocessor 6 recognizes the drive whose reading is delayed, the switch circuit 17 is switched to switch the parity generation circuit. The sub data and the parity data that have already arrived at 10 are transferred to the parity generation circuit 10 via the line 10A. At this time, this sub-data is not transferred to one of the lines 10A for transferring the sub-data whose reading is delayed. Since the microprocessor 6 already knows which sub-data is delayed in reading, and therefore knows which of the lines 10 is inactive, it instructs the switch 120 in the parity generation circuit 10 to: , Only the active line of the lines 10A is selected and connected to the line 200A. Thus, the three sub data and the parity data which have already been read are transferred to the EOR circuit 130 via the line 200A. The EOR circuit 130, which has received the sub data and the parity data from the switch 120, takes the exclusive OR of the sub data and the parity data in the same manner as when the parity data is created, so that the sub data that has not yet been read out is read. Recover. At this time, the EOR circuit 130 informs the microprocessor 6 that the recovery of the sub data is completed.
Report to. The sub data thus recovered is transferred to the active path switch 140 via the line 400. At the direction of the microprocessor 6, the active path switch 140 selects the line to which the recovery data is to be transferred in the line 100A, outputs the recovered sub-data on the line 400 to the line, and outputs the selected sub-data to the other line 100A. The three sub-data already read are output to the three lines. In this way, four normal sub-data are output to the line 100A. The recovery data combination circuit 100 connects the line 110A to the line 9B according to an instruction from the microprocessor 6, and transfers these four sub-data to the cache memory 9 via the line 9B. Thus, the normal reading of the four sub-data including the recovered sub-data is completed.

FIG. 7 shows a timing chart in the data read processing in this embodiment at this time. In the present embodiment, the rotation waiting time of the data reading process is that of the drive # 3 having the second longest rotation waiting time among the five drives # 1 to # 5 forming the logical group 14. Data can be supplied to the CPU 1 earlier than that of the drive # 3 having the longest rotation waiting time. In the conventional read processing, four sub data are read from four drives among all five drives 13 forming the logical group 14. Therefore, as shown in FIG. 7, the rotation waiting time of the read processing in the disk array 2 is 4
It is that of the longest drive # 3 of the drives 13 of the unit.

If no parity data is stored in the selector buffer 18 according to the determination in step 55, the four sub-data necessary for forming the data to be read have already been read in the selector buffer. Will be there. At this time, the response determination circuit unit 16
Reports to the microprocessor 6 that parity data is not stored in the selector buffer 18 (step 61), and the switch circuit 16 connects the selector buffer 18 and the cache memory 9 in response to an instruction from the microprocessor 6. (Step 62). When this connection is completed, the microprocessor 6 transfers the sub data read from the selector buffer 18 to the cache memory 9 (step 63). After that, these sub-data are combined and transferred to the CPU 1 (step 47). Therefore, the operation at this time is similar to the conventional one.

If the parity data described above is stored in the disk storage device for use when a failure occurs in any of the disk storage devices, the disk storage device for storing the error correction code is used. This embodiment can be realized without newly using.

The parity generation circuit 10 used in this embodiment is also used to recover the sub data in one drive from the sub data in another drive when a failure occurs in one of the drives. it can. The parity generation circuit capable of recovering the sub data in such a failed drive may be the same circuit used in a normal RAID 3 disk array. Therefore, the present embodiment can be said to be easy to implement because it can use the parity generation circuit used in a normal disk array.

<Second Embodiment> In the first embodiment, the parity data is used as the error correction code of the parity group.
In this embodiment, a plurality of different error correction codes (EC
Use C). The present embodiment can be realized by modifying the first embodiment as follows.

In the present embodiment, the write data supplied from the CPU 1 is divided into, for example, three sub-data, and a plurality of, for example, two types of ECC data are generated as error correction codes for these sub-data. Then, these sub data and these ECC data are written in different drives. It is known that when two types of ECC data are prepared in this way, even if a failure occurs in up to two drives, the data in the failed drive can be recovered.

In this embodiment also, this ECC data is used when reading out normal data. That is, CPU
When 1 issues a read request for this write data, it issues an instruction to read the three sub-data and two ECC data that make up this write data. In this embodiment, since there are two types of ECC data, up to two sub-data items are recovered from the sub-data items and the ECC data items that have been read before the sub-data items have been read, Data is read and used in place of uncompleted sub data.

More specifically, when a read request is issued later from the CPU 1, five drives storing three sub-data forming the data designated by the request and two types of ECC data for them are stored. A read request is issued to. Each drive responds to these read requests and the reading is completed in sequence. In the drive in which reading has been completed in this order, it is determined whether or not all the sub-data forming the data designated by the read request are included.

If any one or two sub data is not included, one or two ECC data is read before one or two sub data whose reading is not completed. become. In this case,
From the already read partial sub-data and the read one or two ECC data, the one or two un-read sub-data is recovered, and the recovered one or two sub-data is recovered. The sub data and a part of the sub data that has already been read are combined to generate the data specified by the read request, and the data is sent to the CPU 1. Therefore, in the present embodiment, before reading of maximum two sub-data,
When two pieces of sub data are read, all the necessary sub data can be obtained without waiting for the reading of those pieces of sub data to be completed.

FIG. 8 shows a timing chart in this embodiment and the conventional read processing at this time.

In the present embodiment, the rotation waiting time of the data read process is the same as that of the drive # 5 having the third longest rotation waiting time among the five drives # 1 to # 5 forming the logical group 14. Become. Drive # 3 with the longest rotation wait time and drive # 1 with the next longest rotation wait time
The data can be supplied to the CPU 1 earlier than the rotation waiting time. In the read processing of the first embodiment, logical group 1
The rotation waiting time of the drive # 1 having the second longest rotation waiting time among all the five drives 13 included in the drive No. 4 is the rotation waiting time. Therefore, in this embodiment, the number of cases in which all sub-data can be read out faster than in the first embodiment increases.

<Embodiment 3> In the present embodiment, as shown in FIG. 9, the logical group 14 is duplicated to form a large logical group 70.
In the large logical group 70 according to the first embodiment.
Read control is performed. The two logical groups 14 forming the large logical group 70 hold the same data, and both have a so-called mirroring relationship. That is, each drive of one logical group 14, eg, # 1, forms a pair with one of the other logical group 14, eg, # 6. Both of these two drives share a common SC for one drive interface circuit 12.
It is connected via the SI bus 15. Hereinafter, the present embodiment will be described focusing on the points different from the first embodiment.

(Data Writing Operation) Each of a plurality of sub data obtained by dividing the write data supplied from the CPU 1 and the parity data generated from the sub data is
It is written to two drives that are paired with each other in two logical groups, for example, drives # 1 and # 13. The position in the drive to be written is the same. An address table as shown in FIG. 10 is used to determine the write position. In other words, each drive interface circuit 12 is notified from the drive selection unit 11 of any sub data or parity data to be written, the numbers of the two drives determined by this table, and the drive addresses common to them. At this time, the microprocessor 6 instructs the drive interface circuits 12 via the drive selection unit 11 to write the data to the pair of drives 13 connected thereto by mirroring. Each drive interface circuit 12
Sends the same data and in-drive address to a pair of drives connected to it via the SCSI bus 15 connected to it, and sequentially writes the sub data or parity data to these two drives.

(Data Read Operation) Unlike the first embodiment, each drive interface circuit 12 instructs both of a pair of drives connected thereto to read sub data or parity data. The number of the drive to be read out and the storage position in the drive are determined using the address table in FIG. Each drive interface circuit 12 sequentially issues a read request to a pair of drives connected to it. Each drive interface circuit 12 receives the read completion report and the read sub data or parity data from each of the pair of drives, and the read completion notification and the read sub data or parity. The data is transferred to the drive selection unit 11.

The drive selecting section 11 responds to the first read completion report supplied from the pair of read completion reports supplied from the pair of drives in the mirror relationship,
Store the sub data or parity data transferred accompanying it in the select buffer, ignore the read completion report supplied late, and do not capture the sub data or parity data transferred accompanying it in the select buffer. Further, it differs from the first embodiment in that it has a circuit for controlling the storage in the select buffer. The other operations of the drive control unit 11 are the same as those in the first embodiment. As a result, as shown in FIG. 11, as shown in FIG. 11, before the sub data # 3 is read, the sub data # 1, 2, 4 and
And the parity data is read, the sub data #
Can recover 3. Moreover, this recovery can be executed when the parity data used for this recovery is read from one of the drives # 5 and # 10. The same applies to other sub data.

After all, in this embodiment, as in the first embodiment,
One of the sub-data has not been read yet, but when the parity data and the other three sub-data have been read, the sub-data not read from the read sub-data and the parity data is read. Recover data. However, in this embodiment, as compared with the first embodiment, each sub data or parity data is held in a pair of drives,
When the sub data or the parity data is read earlier than one of the pair of drives, the reading of the sub data or the parity data is completed, so that the necessary data can be read faster than in the first embodiment. I can. The technique adopted in this embodiment is also applicable to the second embodiment.

[0066]

According to the present invention, when a plurality of sub-data written so as to form a level RAID 3 disk array is read out, a part of the sub-data and the error correction code are read out, and the other sub-data is read out. Since the unread sub data is recovered at the time when it has not been read yet, it is not necessary to wait for the completion of the reading of the other sub data. Therefore, the data read time from the disk array can be substantially shortened.

Moreover, if this error correction code is stored in the disk storage device for use when a failure occurs in any of the disk storage devices,
The present invention can be implemented without newly using a disk storage device for storing the error correction code.

[Brief description of drawings]

FIG. 1 is a schematic circuit diagram of Embodiment 1 of a disk array according to the present invention.

FIG. 2 is a parity generation circuit (1 used in the device of FIG.
0) Schematic circuit diagram.

3 is a schematic circuit diagram of a drive selection unit (11) of the apparatus of FIG.

FIG. 4 is a diagram showing an example of an address translation table used in the device of FIG.

5 is a flowchart of a data read operation in the device of FIG.

6 is a flowchart of a determination method in a response determination circuit section of the device shown in FIG.

7 is a timing chart of a read operation in the device of FIG.

FIG. 8 is a timing chart of a read operation in the second embodiment of the disk array according to the present invention.

FIG. 9 is a schematic circuit diagram of Embodiment 3 of the disk array according to the present invention.

10 is a diagram showing an address conversion table used in the device of FIG.

11 is a timing chart of a data read operation in the device of FIG.

[Explanation of symbols]

2 ... Control unit, 5 ... Data control circuit, 10 ... Parity generating circuit (parity generating circuit), 12 ... Drive interface circuit, 13 ... Drive

Claims (11)

[Claims] 1. In a disk array device having a plurality of disk storage devices, write data is divided into a plurality of sub data in response to a write request supplied from a host device, and an error correction code for these sub data is provided. These sub data and the created error correction code are written in different ones of the plurality of disk storage devices, and in response to a data read request supplied from the host device, Instructing the disk storage device to read the sub-data and the error correction code, a part of the plurality of sub-data and the error correction code are read from the plurality of disk storage devices, and the other sub-data is still read. At the time when it is not output, the above-mentioned reading is performed from the above-mentioned read partial sub-data and the above-mentioned read error correction code. Is another sub-data is not recovered, the data reading method for supplying to the host device by combining a portion of the sub data and the recovered other sub data read above. 2. The error correction code is held in a plurality of disk storage devices other than the disk storage device where the failure occurs when any of the plurality of disk storage devices fails. 2. The data read method according to claim 1, wherein the error correction code is used to recover the sub data held in the disk storage device in which the failure has occurred, from the plurality of sub data and the error correction code. 3. The data reading method according to claim 1, wherein the error correction code is parity data for the plurality of sub data. 4. In a disk array device having a plurality of disk storage devices, write data is divided into a plurality (n) of sub-data in response to a write request supplied from a host device, and the sub-data for these sub-data is divided. A plurality of (m) different error correction codes are created, and the plurality of sub-data and the created plurality of error correction codes are created as a plurality of (n + m) different ones in the plurality of disk storage devices. Write to the disk storage device, and instruct the plurality (n + m) disk storage devices to read the n sub-data and the m error correction codes in response to a data read request supplied from the host device. However, a part of the plurality of sub-data and one or more of the plurality of error correction codes are stored from the plurality (n + m) of disk storage devices. At the time when the other one or more sub-data that has been read out has not yet been read, from the read partial sub-data and the read one or more error correction codes, Recovers the one or more sub-data that has not been read and combines the recovered one or more sub-data and the read partial sub-data to the host device. Method of reading data to be supplied. 5. The plurality of error correction codes are used for a disk other than the plurality of disk storage devices where the failure occurs when any one of the plurality of disk storage devices in the plurality of disk storage devices fails. An error correction code used to recover the sub data held in a plurality of failed disk storage devices by using a part of the sub data held in the storage device and the plurality of error correction codes The data reading method according to claim 4, wherein 6. A disk array device having a plurality of pairs of disk storage devices, wherein write data is divided into a plurality of sub-data in response to a write request supplied from a host device, and an error correction code for these sub-data is divided. And these sub-data and this created error correction code,
In the plurality of pairs of disk storage devices, each sub data and error correction code are written so as to be redundantly held in the same pair of disk storage devices, and in response to a data read request supplied from a host device, Instructing the plurality of pairs of disk storage devices to read the plurality of sub data and the error correction code, and a part of the plurality of sub data and the error correction code are read from the plurality of pairs of disk storage devices, and others. When the sub-data of is not yet read, the other sub-data not read is recovered from the read partial sub-data and the read error correction code, A data read method for combining a part of the read sub-data and the recovered other sub-data and supplying the sub-data to the host device. 7. A plurality of disk storage devices and a control unit for executing write requests and read requests to the plurality of disk storage devices, which are supplied from a host device, and the control unit is provided from the host device. In response to the supplied write request, means for dividing the write data into a plurality of sub data, means for creating an error correction code for these sub data, these sub data and the created error correction code For writing to different ones of the plurality of disk storage devices, and for reading the plurality of sub-data and the error correction code in response to the data read request supplied from the host device. Means for instructing the disk storage device, and a part of the plurality of sub-data and the error correction code are read from the plurality of disk storage devices. When the other sub-data has not been read yet, the other non-read sub-data is recovered from the read partial sub-data and the read error correction code. And a means for combining the read partial sub-data and the recovered other sub-data and supplying the combined sub-data to the higher-level device. 8. When a failure occurs in any of the plurality of disk storage devices, sub-data held in the failed disk storage device is used as a plurality of disk storage devices other than the disk storage device. 8. The disk array device according to claim 7, further comprising means for recovering by the recovery means using the sub data and the error correction code in the. 9. The storage device comprises: a plurality of disk storage devices; and a control unit, which is supplied from a host device, for executing a write request and a read request to the plurality of disk storage devices. In response to the supplied write request, the write data is divided into a plurality (m) of sub-data, a plurality of different error correction codes for the sub-data, and a plurality of these sub-data and the sub-data. Means for writing the created error correction code in different ones of the plurality of disk storage devices, and in response to a data read request supplied from a higher-level device, the plurality of sub-data and the plurality of sub-data Means for instructing the plurality of disk storage devices different from each other to read out the error correction code, and the plurality of disk storage devices different from each other. At the time when a part of the plurality of sub-data and one or more of the plurality of error correction codes are read, and one or more other sub-data has not yet been read,
Means for recovering the one or more other sub-data not read from the read partial sub-data and the read one or more error correction codes, A disk array device comprising means for combining the read partial sub-data and the recovered one or more other sub-data and supplying the combined sub-data to the higher-level device. 10. When one or more disk storage devices among the plurality of disk storage devices fail, the one held in the one or more disk storage devices in which the failure has occurred Alternatively, means for recovering the plurality of sub-data by the sub-data recovery means using the plurality of other sub-data held in another disk storage device other than the disk storage device and the plurality of error correction codes The disk array device according to claim 9, further comprising: 11. A plurality of pairs of disk storage devices, and a controller for executing write requests and read requests to the plurality of pairs of disk storage devices supplied from a host device, wherein the controller is a host device. In response to the write request supplied from the device, means for dividing the write data into a plurality of sub data, means for creating an error correction code for these sub data, and those sub data and the created error correction. A code for writing to the plurality of pairs of disk storage devices such that each sub-data and error correction code are redundantly held in the same pair of disk storage devices, and data reading supplied from the host device. A means for instructing the plurality of pairs of disk storage devices to read the plurality of sub data and the error correction code in response to the request; When a part of the plurality of sub-data and the error correction code are read from several pairs of disk storage devices and the other sub-data is not yet read, the read partial sub-data and A means for recovering the other sub-data that has not been read from the read error correction code, and combining the read partial sub-data and the recovered other sub-data. And a means for supplying the host device to the host device.