JPH0730781A - Contour correcting circuit - Google Patents

Abstract

PURPOSE:To provide a contour correcting circuit halving contour signal width with small circuit scale by solving the problem of enlarging the circuit scale because of a 1/2 power circuit and a multiplier required. CONSTITUTION:After the absolute value of the quadratic differential signal and linear differential signal of an input luminance signal 1 are calculated by absolute value circuits 7 and 9, the output of the absolute value circuit 9 is delayed by a delay circuit 10 by a prescribed amount T, and either the output of the absolute value circuit 7 or the output of the absolute value circuit 10 provided with a smaller level is outputted by using a comparator 11 and a selecting circuit 12. The output of the selecting circuit 12 is branched into two and turned to a signal provided with a code matching with the code bit of the quadratic differential signal by using a selecting circuit 14 and an inverting circuit 13, and the contour signal provided with 1/2 signal width is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contour correction circuit used for improving image quality in image signal processing of an image pickup device or the like.

[0002]

2. Description of the Related Art In recent years, in an image pickup device or the like, a contour correction circuit has become more and more important in order to reproduce an image having a more natural and clear contour.

As a conventional contour correction circuit, for example, as disclosed in Japanese Patent Publication No. 5-6392, by reducing the contour signal width to 1/2, particularly in an image portion having a large brightness amplitude difference, There is a contour correction circuit that widens the width generated when contour correction is performed at a low emphasis frequency and makes a high-level contour signal less noticeable, thereby improving image quality deterioration.

A conventional contour correction circuit will be described below. FIG. 3 is a block diagram showing the configuration of this conventional contour correction circuit. In FIG. 3, 1 is an input luminance signal, 2 is a coefficient multiplier, 3 is a first delay circuit, 4 is a first adder, 5 is a second delay circuit, 6 is a second adder, and 8 is subtraction. , 9 is an absolute value circuit, 10 is a third delay circuit, 16 is a 1/2 power circuit, 17 is a multiplier, and 15 is an output, which is composed of a digital circuit.

The operation of the contour correction circuit configured as described above will be described below with reference to FIG.

FIG. 4 is a signal waveform diagram showing an operating state in the conventional contour correction circuit shown in FIG. First, when the input luminance signal 1 is input as shown in FIG. 4A, the polarity of the input luminance signal 1 is inverted by the coefficient unit 2 and at the same time the level thereof is reduced to 1/2. A signal obtained by delaying the output signal of the coefficient unit 2 by the first delay circuit 3 for a predetermined time 2T and the input luminance signal 1 are added by the first adder 4, and the adder 4
The signal obtained by delaying the output of the second delay circuit 5 by a predetermined time 2T and the output signal of the coefficient unit 2 by the second adder 6 are added to input as shown in (c) of FIG. A second derivative signal of the luminance signal is obtained. Further, the subtractor 8 subtracts the output of the first delay circuit 3 from the output of the coefficient unit 2 to obtain a primary differential signal of the input luminance signal as shown in FIG. 4B. The primary differential signal obtained by the subtractor 8 takes its absolute value by the absolute value circuit 9 and becomes a signal as shown in FIG. 4 (d). The delay circuit 10 of 3 delays for a predetermined time T. The output of the adder 6 and the output of the third delay circuit 10 are
After being squared by the squaring circuit 16 and then multiplied by the multiplier 17, the output 15 is output as shown in (f) of FIG.
The contour signal having the contour signal width ½ of the original contour signal width shown in (c) of FIG. 4 is output.

[0007]

However, the above-mentioned conventional configuration has a problem that the circuit scale becomes large because the 1/2 power circuit and the multiplier are required.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a contour correction circuit in which the circuit scale is reduced and a 1/2 circuit and a multiplier are not required.

[0009]

In order to achieve this object, a contour correction circuit of the present invention is a circuit for outputting a secondary differential signal of an input luminance signal and a circuit for outputting a primary differential signal of an input luminance signal. And a first absolute value circuit for obtaining the absolute value of the secondary differential signal, a second absolute value circuit for obtaining the absolute value of the primary differential signal, and a delay for delaying the output of the second absolute value circuit for a predetermined time. Circuit, a comparator for comparing the levels of the outputs of the first and second absolute value circuits, and a comparator for comparing the outputs of the first and second absolute value circuits. A first selection circuit that switches and selects and outputs the output, an inverting circuit that inverts the positive / negative of the output of the first selection circuit, and an output of the first selection circuit and an output of the inverting circuit, the sign of the secondary differential signal. A second selection circuit for switching output according to the bit.

[0010]

According to the present invention, with the above configuration, the timing of the absolute value of the secondary differential signal of the input luminance signal and the absolute value of the primary differential signal of the input luminance signal are matched, and the levels of both are compared by the comparator. , The smaller one is output, and the sign of the output signal is made to coincide with the sign of the secondary differential signal, so that the contour signal width at the low emphasis frequency is ½ without the need of the ½ power circuit and the multiplier. The contour correction can be performed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a contour correction circuit according to an embodiment of the present invention. In FIG. 1, 1 is an input luminance signal, 2 is a coefficient multiplier, 3 is a first delay circuit, 4 is a first adder, 5 is a second delay circuit, 6 is a second adder, and 7 is a second adder. 1 is an absolute value circuit, 8 is a subtractor, 9 is a second absolute value circuit, 10 is a third delay circuit, 11 is a comparator, 12
Is a first selection circuit, 13 is an inverting circuit, 14 is a second selection circuit, and 15 is an output. This embodiment is composed of a digital circuit, and the same components as those in the conventional example are designated by the same reference numerals.

The operation of the contour correction circuit of the present embodiment having the above-described structure will be described below with reference to FIG. FIG. 2 is a signal waveform diagram showing the operating state of this embodiment. First, the operation of obtaining the secondary differential signal and the primary differential signal from the input luminance signal 1 is the same as the conventional example.
Now, when the obtained secondary differential signal is a signal as shown in FIG. 2A, and the primary differential signal is a signal as shown in FIG. 2B, the secondary differential signal is converted into an absolute value circuit 7 2C shows the absolute value thereof, and the absolute value circuit 9 similarly obtains the absolute value thereof as shown in FIG. 2D. As shown by the alternate long and short dash line in FIG. 2E, the output signal of the absolute value circuit 9 is changed to the third delay circuit 1
The value is delayed by a predetermined amount T by 0, and the output of the absolute value circuit 7 is compared with the comparator 11. The comparator 11 outputs LOW level when the output of the absolute value circuit 7 is smaller than the output of the delay circuit 10, and HIGH level otherwise.
To control. The selection circuit 12 switches and outputs the output of the absolute value circuit 7 and the output of the delay circuit 10, and the comparator 11 outputs the LO signal.
At the W level, the output of the absolute value circuit 7 is selected and the comparator 1
When the output of 1 is HIGH level, the output of the delay circuit 10 is selected and output. The output of the selection circuit 12 is shown in FIG. The output of the selection circuit 12 is branched into two, one of which is input to the selection circuit 14, and the other of which is inverted by the inverting circuit 13 and then input to the selection circuit 14. The selection circuit 14 is controlled by the sign bit (polarity signal) of the secondary differential signal (output signal of the adder 6) of the input luminance signal. When the sign bit is positive, the output of the selection circuit 12 is selected, and the sign bit is When it is negative, the output of the inverting circuit 13 is selected and output, and is output as a signal having the same sign as the secondary differential signal as shown in (g) of FIG.

As described above, according to this embodiment, the timing of the absolute value of the secondary differential signal of the input luminance signal and the absolute value of the primary differential signal of the input luminance signal are matched, and the levels of both are obtained by the comparator. Are compared, the smaller one is output, and the sign of the output signal is made to match the sign of the secondary differential signal.
The contour signal width at a low emphasis frequency can be halved without requiring the / square circuit and the multiplier.

Although the contour correction in the horizontal direction has been described in the present embodiment, the delay amount T of the delay circuit is set to 1 horizontal.
It is self-evident that the contour correction in the vertical direction can be performed if the line portion is included.

[0016]

As described above, according to the present invention, the timing of the absolute value of the secondary differential signal of the input luminance signal and the absolute value of the primary differential signal of the input luminance signal are matched, and the levels of the two are determined by a comparator. By comparing and outputting the smaller one and matching the sign of the output signal with the sign of the secondary differential signal, a contour correction circuit that can be configured by a small-scale circuit that does not require a 1/2 power circuit and a multiplier Can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a contour correction circuit according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram for explaining the operation of the contour correction circuit in the embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional contour correction circuit.

FIG. 4 is a signal waveform diagram for explaining the operation of a conventional contour correction circuit.

[Explanation of symbols]

 2 coefficient device 3 first delay circuit 4 first adder 5 second delay circuit 6 second adder 7 first absolute value circuit 8 subtractor 9 second absolute value circuit 10 third delay circuit 11 Comparator 12 First Selection Circuit 13 Inversion Circuit 14 Second Selection Circuit 16 1/2 Power Circuit 17 Multiplier

Claims (1)

[Claims] 1. A circuit for outputting a secondary differential signal of an input luminance signal, a circuit for outputting a primary differential signal of the input luminance signal, and a first absolute value circuit for obtaining an absolute value of the secondary differential signal. A second absolute value circuit that obtains the absolute value of the first-order differential signal; a delay circuit that delays the output of the second absolute value circuit for a predetermined time; and an output of the first absolute value circuit and the first absolute value circuit. A second comparator for comparing the output levels of the absolute value circuit, and a first output for selectively switching between the output of the first absolute value circuit and the output of the second absolute value circuit by the output of the comparator. A selection circuit; an inverting circuit for inverting the positive / negative of the output of the first selection circuit; and a switching output of the output of the first selection circuit and the output of the inverting circuit according to the sign bit of the secondary differential signal. A contour correction circuit comprising: