JPH07253924A - Information processor - Google Patents

Abstract

PURPOSE:To speed up data transfer processing by providing each CPU with a storage block transfer means, and then immediately referring to a command word on a main storage by a data transfer control part (MOVER) and also writing data elements which need to have speediness in the processing of a CPU directly in a cache memory at need. CONSTITUTION:To request a synchronous transfer instruction which does not perform next instruction processing until data transfer ends when one CPU 11 requests the MOVER 15 to perform the data transfer between a main storage part (MSU) 3 and an external storage part, a storage block transfer means 11A transfers a storage block including the command word and data to be transferred from the cache memory (LBS) 14 to the MSU 3. Consequently, when the storage control part (MCU) 12 is requested of the command word and data to be transferred, the command word and the data to be transferred which are on the MSU 3 can be supplied from the MSU 3 to the MOVER 15 immediately.

Description

Detailed Description of the Invention

(Table of Contents) Industrial Application Field of the Prior Art (FIGS. 10 to 16) Problems to be Solved by the Invention (FIGS. 13, 14, and 1)
6) Means for Solving the Problem (FIG. 1) Operation (FIG. 1) Embodiment (a) Description of the configuration of the information processing apparatus of this embodiment (FIG. 2) (b) Description of an operation example when a synchronous transfer request is made (FIGS. 2 and 3) (c) Description of operation example during standby for synchronous transfer (FIG. 4) (d) Description of operation example of storage block transfer by operation code (FIG. 5) (e) Operation example at the end of synchronous transfer (FIGS. 6 and 7) (f) Description of another operation example at the end of synchronous transfer (FIGS. 8 and 9)

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides information in which a plurality of central processing units that operate in parallel using data in a common main memory unit are provided with a cache memory for holding data in the main memory unit in a swap system. The present invention relates to a processing device, and more particularly, to an information processing device further including an external storage unit to supplement the storage capacity of the main storage unit.

Recently, information processing apparatuses are required to process a large amount of data at high speed. However, the growth of the amount of data is much larger than that of the capacity of the main storage device, which is inevitable. An external storage device such as an extended storage device, a semiconductor disk, or a magnetic disk is required. Further, since the data transfer performance between the external storage device and the main storage device greatly affects the throughput of the system, higher speed data transfer capability is required.

[0004]

2. Description of the Related Art In general, with the speeding up of information processing, a large number of processor units are operated in parallel. In such an information processing apparatus, for example, FIG.
0, a plurality of central processing units (hereinafter, CPU
1) is connected to a common main storage unit (hereinafter referred to as MSU) 3 via a storage control unit (hereinafter referred to as MCU) 2.

In addition, each CPU 1 has an MSU 3 to an MC.
There is provided a local buffer storage unit (cache memory; hereinafter referred to as LBS) 4 which holds data and the like read via U2 by a swap (store-in) method. The LBS4 has a smaller capacity than the MSU3 but is capable of high-speed processing. By alleviating the processing speed difference between the CPU1 and the MSU3, the speed of the arithmetic processing in each CPU1 can be increased. ing.

In recent years, in order to supplement the storage capacity of the MSU 3, the data transfer control unit (hereinafter referred to as M
An external storage unit (hereinafter referred to as ESU) via an OVER 5.
It is also provided with 6. here,
The MOVER 5 refers to a command word created by the CPU 1 in the LBS 4 or the MSU 3 (to be described later, refer to reference numeral 4A in the LBS 4 in FIG. 10) and refers to the storage mechanism (MSU 3 or L
The data transfer operation is performed between the BS 4) and the ESU 6, and the ESU 6 stores and reads the data according to an instruction from the MOVER 5.

As shown in FIG. 12, the MOVER 5 has a latch section 51, an MSU access control mechanism 52, a data / command discrimination section 53, and a synchronous / asynchronous transfer discrimination section 5.
4, latch section 55 for synchronous transfer, latch section 5 for asynchronous transfer
6, selectors 57 and 58, and an adder 59. The function of each part will be described in the following operation description.

In FIG. 12, 50A is a data bus from MOVER5 to MCU2, and 50B is a data bus from MCU2 to MO2.
Data bus to VER5, 50C is from MOVER5 to E
Data bus to SU6, 50D is MOVE from ESU6
It is a data bus to R5. In the above-mentioned information processing apparatus, MSU3, MOVE5, LBS4 mutually transmit and receive data via MCU2.

In FIG. 10, reference numeral 7 denotes a selector provided on the MCU 2, and this selector 7 outputs either one of the LBS 4 and the MSU 3 via the MOVER 5
It is for switching connection so as to be communicable with the SU 6. Further, 8A is a tag portion of the LBS 4 on the CPU 1, and the tag portion 8A stores tag information which is entry information for identifying data registered in the LBS 4, and the LBS 4 stores the tag information and the data. And are held as one entry.

As shown in FIG. 15, the tag unit 8A holds, as LBS tag information, an MSU absolute address of data, an attribute bit for exclusive control with data of LBS4 in another CPU 1, and the like. ing. further,
As shown in FIG. 15, a tag unit 8B is also provided on the MCU 2, and the tag unit 8B holds a copy of the tag information held by the tag unit 8A of the LBS 4 of each CPU 1.

Now, a case where the CPU 1 requests data transfer between the ESU 6 and the MSU 3 will be described with reference to FIGS. In this case, first, the CPU 1 associates the addresses of the MSU 3 and the ESU 6 and describes the data length and the content of the transfer operation (command word LB in FIG. 10).
The reference numeral 4A in S4) is created on the MSU 3 or LBS 4 (see A1 in FIG. 13).

The command word 4A is, for example, as shown in FIG. 11, MSW (Mover Status Word) and MCW (Move).
r Command Word).
The MCW designates the transfer content, and the MSW stores the processing result by the MOVER 5 of the transfer operation designated by the MCW. The CPU 1 can know whether the designated data transfer has been correctly processed by referring to the MSW.

The contents of the MCW are composed of the MSU absolute address of the transfer data, the address data length of the ESU 6 and the transfer direction. When the MOVER 5 is started by the CPU 1, it starts MC from the MSU absolute address of the specified MCW.
W is read out, the designated data transfer is performed, and the result is stored in MSW. In the MSW, all bits are set to 0 when the command word 4A is created by the CPU 1. MOVER5 is ESU6 and MS
At the end of the data transfer with U3 or LBS4, write the end information to MSW and write the end information of the transfer to C
Used to communicate to PU1. Also, the transfer length of ESU6 of transfer data, the transfer start real address of ESU6, the transfer length of MSU3, and the transfer start absolute address of MSU3 are set in MCW, and the ESU real address and the MSU absolute address are associated with each other. .

Generally, the storage mechanism of the information processing apparatus is constructed as an aggregate of predetermined storage capacities called pages, and the storage mechanism cannot simply transfer data across pages. This is because such a storage device generally adopts a virtual storage system, and even if there are two consecutive pages in a logical address, they may exist discretely in a physical view. Because it is unknown.

In the MSU2 example described here,
The page size of ESU6 is 16 kbytes, the page size of MSU3 is 4 kbytes, and the transfer is ESU6.
Since the transfer start address can be specified in 8-byte units, a maximum of 5 MSU pages are associated with one ESU page, and the transfer length specified in ESU 6 is in effect. Indicates the total transfer length in one transfer request. The five or less pages that physically exist in the MSU3 are stored in one continuous real address page in the ESU6 page.

Swap type cache memory (LBS
In 4), when the CPU 1 updates the data for an arbitrary address, only the data on the LBS 4 is updated, and a cache entry replacement occurs, or another CPU 1 updates the same storage block. When the update is performed, the update data is written from the LBS 4 to the MSU 3 to update the data on the MSU 3. Therefore, when the CPU 1 writes the command word 4A for the MOVER 5 in the storage space, it is written only on the LBS 4 (see A2 in FIG. 13).

CPU 1 sends command word 4A to LBS4
At the time of writing, the attribute information of the tag indicating that the command word 4A exists on the LBS 4 is rewritten for the corresponding tag portion 8A. After that, CPU1 moves to MOVER5
The head MSU absolute address of the command word 4A, access attribute information, etc. are sent to the device to issue a transfer start request (see A3 in FIGS. 10 and 13). The CPU1 that issued the synchronous transfer request to the MOVER5 is interlocked, and when the MOVER5 finishes the transfer between the ESU6 and the MSU3, it notifies the CPU1 of the end of the transfer.
The CPU 1 is stopped.

Since the transfer start request from the CPU 1 has attribute information indicating whether the transfer request is an asynchronous transfer or a synchronous transfer, the MOVER 5 determines whether the access is a synchronous transfer or an asynchronous transfer by the synchronous / asynchronous transfer discriminating unit 54. (See A4 in FIG. 13), and if the requested access is executable, the MSU access control mechanism 52 requests the MCU 2 to read the command word 4A through the data bus 50A (FIG. 12, FIG. (See A5 in FIG. 13). MOVE
When R5 is executing a synchronous transfer from another CPU and when an asynchronous transfer request is received from CPU1 during the execution of an asynchronous instruction, MOVER5 can execute the transfer request from CPU1, and CPU1 issues a transfer start request after a fixed time. MOVER
Reissue to 5.

In the MCU 2, L in each CPU 1
Since the copy of the tag portion 8A of BS4 is held in the tag portion 8B (see FIG. 15), the MCU 2 receives the request to read the command word 4A from MOVER 5, and then moves to MOVE.
It is possible to judge whether or not it is on LBS4 by referring to the MSU absolute address of the MCW received from R5. If it is held in LBS4, the CPU 1 makes a request to eject the entry, and if it is not held in LBS4. A command word read request is issued to MSU3.

In the case of synchronous transfer, the CPU 1 creates the command word 4A necessary for accessing the ESU 6 and moves it.
After the access request is issued to R5, the command word 4A is in the LBS4 because it is in the interlock state until the transfer is completed.
Very likely to be above. Therefore, MOVER5
When a command word 4A transfer request comes from MC,
U2 will issue a transfer request to LBS4 with a very high probability (see A6 in FIG. 13).

If the command word 4A is in the LBS4 and the transfer request is issued from the MOVER5, the LBS is sent to the LBS4.
The command word 4A in 4 is once transferred to the MSU 3 in block units, and then MO from the MSU 3 via the MCU 2
It is transferred to the VER5 (see A7 and A8 in FIG. 13), and at the same time, in the tag units 8A and 8B of the LBS4, the command word 4
The entry holding A is invalidated.

When the command word 4A is supplied to the MOVER 5 (see A8 in FIGS. 12 and 13) and stored in the latch section 51, the MSU access control mechanism 52 transfers the data of the MCW from the MSU 3 to the ESU 6. If specified, whether the data transferred from the MCU 2 through the data bus 50B is MSW, MCW, MS
The data / command determination unit 53 determines whether the data is the transfer target data between U3 and ESU6 (A in FIG. 13).
9).

Here, MOVER5 is executed during asynchronous transfer execution.
If a synchronous transfer request is transferred to, the synchronous transfer is processed first. Therefore, in the MOVER 5, the synchronous transfer latch unit 55 and the asynchronous transfer latch unit 5 serve as control information holding means for at least the synchronous transfer and the asynchronous transfer.
6 is provided, and the specified data transfer type is synchronized /
The asynchronous transfer determination unit 54 makes a determination, and holds the MSW and MCW in the latch unit 55 or 56 according to the determined type. Then, in MOVER5, the command word for synchronous transfer is analyzed, the instruction latch (latch section 55 or 56) currently being executed is selected by the selector 57, and the ESU6 is activated to transfer the data between the MSU3 and the ESU6. Is started (see A10 in FIG. 13).

In the case of data transfer from the MSU 3 or LBS 4 to the ESU 6, the LB is also referred to for the data by referring to the tag section 8B in the MCU 2 as in the command word 4A.
Whether it is in S4 or in MSU3 is determined, and after being read, MOVER5 (data bus 50B, determination unit 5
3, ES via selector 57, data bus 50C)
Transferred to U6. When data is transferred from ESU6 to MSU3, it is not clear whether CPU1 needs the data transferred from ESU6 immediately.
The transfer data from the SU6 is not transferred to the LBS4 and is all stored in the MSU3.

Next, the operation at the time of data transfer from MSU 3 to ESU 6 will be described. After the ESU 6 is activated, the MSU and ESU transfer start addresses sent by the MCW are added by the adder 59 for each data request length, and the MSU access control mechanism 5 is added.
2 requests the MCU 2 to read data from the MSU 3. When data is supplied from the MCU 2 through the data bus 50B, the MSU access control mechanism 52 determines the transfer target data transferred from the MCU 2 as the determination unit 53, the selector 57, as in the case of the command word 4A.
Send to ESU 6 via data bus 50C.

When the MSU and ESU addresses are added, the transfer length of the MSU and ESU is subtracted corresponding to the added amount of the addresses, so that the remaining transfer length can be determined. After that, until the remaining transfer length becomes 0, MS
Data transfer request to U3, ES of transferred data
The transfer to U6 is repeated while adding each address.

After transferring the last data to ESU6, MOVE5 sends to ESU6 a flag indicating that all the data has been transferred to ESU6. ESU6
Notifies the MOVER 5 of the transfer end command and the end information such as an error after the processing of all data is completed or when an error is detected (see B1 in FIG. 14).
After the transfer of all data is completed, the MOVER 5 writes error information and the like in a predetermined field in the MSW of the command word (see B2 in FIG. 14).

MOVER 5 requests the MCU 2 to store the MSW containing error information and the like (B in FIG. 14).
3), when data is sent from MOVER 5 to MCU 2 through the data bus 50A, MCU 2 causes MSU 3
Is requested to store the MSW (see B4 in FIG. 14), and all the data is stored in the MSU3. MSU3
When it completes the MSW store, it sends a normal termination notification to MCU2 (see B5 in FIG. 14).
The normal end notification is sent to MOVER 5 (Fig. 1
4 B6).

In this way, the MOVER 5, which has finished storing the MSW in which the error information and the like have been written in the MSU 3 and has received the normal end notification, issues an interrupt request to the CPU 1 which is the access request source to notify the end of command transfer. (Fig. 1
0, see B7 in FIG. 14), the CPU 1 releases the interlock. After that, the CPU 1 asks the MCU 2 to check the transfer end information stored in the MSW.
MS command word including end information (error information, etc.)
A request for transfer from U3 to CPU1 is made (see B8 in FIG. 14). Receiving this request, the MCU2 requests the MSU3 to read the command word (see B9 in FIG. 14), and the command word is transferred from the MSU3 to the CPU1 and is also written in the LBS4 (B in FIG. 14).
10). When the command word reaches the CPU 1 (see B11 of FIG. 14), the CPU 1 checks the error information and status information of the MSW and ends the synchronous transfer.

On the other hand, when MOVER 5 receives a transfer activation request from CPU 1 (see C1 in FIG. 16), ESU 6 determines that a new transfer activation request cannot be immediately accepted during data transfer by MOVER 5 (FIG. 16). C
2), the MOVE5 returns a code indicating that it was not accepted to the MCU2 (see C3 in FIG. 16).

M receiving the code from this MOVER5
CU2 waits for a while, and after a certain time
The transfer request is issued again to VER5 (see C4 in FIG. 16). If the MOVER 5 is in a receivable state at the time of this re-request, the MOVE 5 determines whether the access is a synchronous transfer or an asynchronous transfer as in FIG. On the other hand, the read of the command word 4A is requested (see C5 in FIG. 16).

When the MCU 2 receives the read request for the command word 4A from the MOVER 5, the MCU 2 refers to the tag section 8B and issues a command word read request to the LBS 4 (see C6 in FIG. 16). The LBS4 writes the command word 4A to the MSU3 and then transfers it to the MCU2 (see C7 in FIG. 16), and the MCU2 transfers the command word 4A to MOVER5 (C8 in FIG. 16).
reference).

After that, the MOVER 5 analyzes the command word 4A to determine the process to be executed, and then
The ESU6 is activated to start data transfer between the MSU3 and the ESU6 (see C9 in FIG. 16).

[0034]

By the way, during the synchronous transfer, the CPU 1 enters the interlock state after creating the command word 4A on the LBS 4, and stops until the transfer is completed and the interlock state is released. There is. Therefore, when MOVE5 tries to read the command word, the probability that the command word exists in LBS4 is very high. In addition, the data to be transferred is immediately before the CPU1.
Is created by performing a store access,
High probability of being present in LBS4.

In order for MOVE5 to read the data, it takes less time to process the data in MSU3 than in LBS4. It is LBS4 to MOVER5
When the data is transferred to the
This is because the data is transferred from MSU3 to MOVER5 after being transferred to U3 (see B7 to B8 in FIG. 13). Moreover, since the LBS 4 exists in each individual CPU 1, it is extremely difficult to continuously eject a plurality of blocks.

When a copy of the LBS tag for each CPU1 in the tag section 8B in the MCU2 is checked when the data request signal is issued from the MOVE5 to the MCU2, it is determined that the data to be transferred is in the LBS4. , The MCU 2 issues a request to the LBS 4 having the latest data to eject the data to the MSU 3. MSU
The LBS 4 which has received the data extraction request to 3 transfers the requested data to the MCU 2 and invalidates the data attribute of the LBS entry. If the data to be transferred to MCU2 is shared by multiple LBSs 4, the data is transferred to LBS.
At the same time as the transfer from 4 to the MCU 2, the entry of the transfer target data of each LBS 4 is invalidated. After that, LBS4
After receiving the data from MCU 3, it transfers it to MSU 3 and then transfers it from MSU 3 to MOVER 5.

When a data transfer request is issued from MOVE5 to MCU2, if the data is in MSU3, MCU2 only issues a data transfer request to MSU3, and tag section 8A of LBS4 is used. No operation is required. Therefore, in the above-described conventional information processing apparatus, when the command word and data read request is issued from MOVE5, there is a high probability that the operation of moving the command word and data from LBS4 to MSU3 is required, and the transfer performance is high. Had become a factor of decrease.

On the other hand, at the time of data transfer from ESU6 to MSU3, the data read from ESU6 is written to MSU3. However, at the time of data transfer from ESU6 to MSU3, the data is written to MSU3 instead of LBS4.
When the CPU 1 uses the data written in the MSU 3 immediately after the transfer of the data is completed, the data is M
It is necessary to transfer from SU3 (B8 to B1 in FIG. 14).
0 (see 0), which causes a time loss.

Further, if all the data is written to the LBS4, if it cannot be guaranteed that the written data is used by the CPU1, a situation will occur in which a necessary cache entry is pushed out to the MSU3, and vice versa. Since it may reduce the processing performance of
The data from SU6 cannot be registered in LBS4.

Therefore, in the above-mentioned conventional information processing apparatus, even for data elements that require high speed, M is uniformly applied.
Since the data is written in SU3, the CPU1 has to access the MSU3 via the MCU2 in order to retrieve necessary data, which has been a barrier to improvement in processing performance. Furthermore, as described above with reference to FIG. 16, in the configuration in which the MOVER 5 is shared by the plurality of CPUs 1,
When 5 receives from the CPU 1 the start address of the command word 4A and the transfer request, the MOVER 5 has already received another CPU.
It is conceivable that the transfer request from 1 has been received and the previously accepted transfer is being executed. If the data transfer request currently being executed and received by the mover 5 is synchronous transfer, even if a new transfer request is received, the execution is kept waiting until the synchronous transfer being executed is completed.

At this time, if the data transfer request sent to MOVER 5 later is asynchronous transfer, the CPU 1 executes the next processing even if the execution of data transfer is waited, so that the newly sent instruction is transferred synchronously. Although there is no problem compared to the case where the data transfer is delayed, if the data transfer is waited in the case of the synchronous transfer, the data transfer can be executed after the preceding data transfer is completed, and the CPU 1 is executed until the transfer is completed.
Remains stopped, which causes a decrease in processing efficiency.

Further, the MOV is re-requested by the MCU 2
If ER5 is available, as described above, M
When a command word and data read request is issued from OVER5, the command word and data are transferred to the LB.
There is a high probability that an operation of moving from S4 to MSU3 is necessary, which is also a cause of deterioration in transfer performance. The present invention has been devised in view of such problems, and is
The command word can be referred to by R immediately on the MSU, and the data element that requires high speed in the CPU processing is directly written to the LBS as needed to speed up the data transfer processing. It is an object of the present invention to provide an information processing device.

[0043]

FIG. 1 is a block diagram showing the principle of the present invention. In FIG. 1, 11 is a central processing unit (CPU), and 13 is a main memory shared by a plurality of central processing units 11. Units (MSU), 12 are central processing units 11
A storage control unit (MCU) that controls data transfer between the main storage unit 13 and the main storage unit 13 is a cache memory (LBS) provided for each central processing unit 11, and this cache memory 14 is a storage control unit. Main memory 13 via 12
The data transferred from is held by the swap method.

Reference numeral 15 is a data transfer control unit (MOVE).
In R), the data transfer control unit 15 refers to the command word created in the cache memory 14 or the main storage unit 13 by each central processing unit 11 triggered by the activation instruction from each central processing unit 11. Then, the data transfer control between the main storage unit 13 and the external storage unit 16 is performed via the storage control unit 12.

Each central processing unit 11 is provided with storage block transfer means 11A. The storage block transfer means 11A transfers the command word and the transfer when the own central processing unit 11 requests the data transfer control unit 15 for a synchronous transfer instruction between the main storage unit 13 and the external storage unit 16. A storage block including target data is transferred from the cache memory 14 to the main storage unit 13 (claim 1).

The memory block transfer means 11A of the central processing unit 11 is controlled by the data transfer control unit 15 when the central processing unit 11 requests the data transfer control unit 15 to activate a synchronous transfer instruction. When the data transfer instructed by the command word cannot be immediately started when the activation request is received from the arithmetic processing unit 11, the command word and the transfer target data are included before the processing of the data transfer control unit 15 is started. The storage block may be transferred from the cache memory 14 to the main storage unit 13 (claim 2).

In addition, the data transfer control unit 15 analyzes the command word and the storage address of the data created by the central processing unit 11, and the operation code issued to the storage control unit 12 by the data transfer control unit 15 includes: The central processing unit 1 is provided with a request code for transferring a storage block including an address designated by the data transfer control unit 15 from the cache memory 14 to the main storage unit 13.
The storage block transfer unit 11A of No. 1 includes a command word and data when the data transfer control unit 15 issues the operation code to the storage control unit 12 after receiving the activation instruction from the central processing unit 11. The storage block may be transferred from the cache memory 14 to the main storage unit 13 (claim 3).

On the other hand, the storage control unit 12 is provided with a switching transfer means 12A. This switching transfer means 12A
Is for switching the transfer destination of the data from the external storage unit 16 from the main storage unit 13 to the cache memory 14 and transferring a part or all of the data to the cache memory 14 (claim 4). Then, the switching transfer means 12A
Means that the central processing unit 11 uses the data transferred from the external storage unit 16 to the main storage unit 13 immediately after the transfer is completed, according to the type of the data transfer instruction instructed by the command word from the central processing unit 11. If it can be determined based on this, the transfer storage destination of the data is switched from the main storage unit 13 to the cache memory 14 and a part or all of the data is transferred to the cache memory 14 (claim 5).

At this time, the data transfer control unit 15 holds the attribute information that the central processing unit 11 uses the data transferred from the external storage unit 16 to the main storage unit 13 immediately after the transfer as attribute information. Means and a notifying means for notifying the switching transfer means 12A of the storage control section 12 of the attribute information held in the attribute information holding means, and the switching transfer means 12A of the storage control section 12 has the attribute from the notification means. A switching transfer operation may be performed according to information (claim 6).

Further, when data is transferred from the external storage unit 16 to the main storage unit 13 to the data transfer control unit 15, the transfer storage destination of the data for each predetermined data unit is the switching transfer means 12A of the storage control unit 12. The switching transfer means 12A of the storage controller 12 may be configured to perform the switching transfer operation according to the attribute information from the notification means (claim 7).

[0051]

In the above-described information processing apparatus of the present invention (claim 1), the own central processing unit 11 requests the data transfer control unit 15 to transfer data between the main storage unit 13 and the external storage unit 16. After that, when requesting a synchronous transfer instruction that does not perform the next instruction processing until the data transfer is completed, the storage block transfer means 11A causes the storage block including the command word and the transfer target data to be the cache memory 1.
4 to the main storage unit 13.

As a result, when a request for fetching a command word and data to be transferred from the data transfer control unit 15 to the storage control unit 12 is issued to the storage control unit 12, the command word and the main storage unit 13 are immediately transferred. The data to be transferred can be supplied from the main storage unit 13 to the data transfer control unit 15. When the central processing unit 11 requests the data transfer control unit 15 to activate a synchronous transfer instruction, the data transfer control unit 15
Is in a state in which the data transfer instructed by the command word cannot be immediately started when the activation request is received from the central processing unit 11, before the processing of the data transfer control unit 15 is started, by the storage block transfer means 11A, By transferring the storage block including the command word and the transfer target data from the cache memory 14 to the main storage unit 13 (claim 2), the processing by the data transfer control unit 15 can be started, and the command word and the main storage unit 13 can be started. The command word and data can be immediately supplied to the data transfer control unit 15 when the above fetch request for the transfer target data is issued to the storage control unit 12.

Further, the operation code issued by the data transfer control unit 15 to the storage control unit 12 is a request for transferring a storage block including the address designated by the data transfer control unit 15 from the cache memory 14 to the main storage unit 13. By providing the code, the data transfer control unit 1
When the operation code is issued from 5,
The storage block transfer means 11A stores a storage block including a command word and data in the cache memory 14
By transferring the data to the main memory 13 in advance (claim 3), the command word and the data can be immediately read out by the data transfer controller 15.

On the other hand, in the above-described information processing apparatus of the present invention (claim 4), the switching transfer means 12A of the storage control unit 12 causes the main storage of the transfer storage destination of the data from the external storage unit 16 as necessary. It is possible to switch from the unit 13 to the cache memory 14 and transfer a part or all of the data to the cache memory 14. At this time, the central processing unit 11 determines the external storage unit 16 based on the type of the data transfer instruction specified by the command word from the central processing unit 11.
If it can be determined in advance that the data transferred from the main storage unit 13 to the main storage unit 13 will be used immediately after the transfer is completed, the switching transfer unit 1
By 2A, by transferring a part or all of the required data to the cache memory 14 instead of the main storage unit 13 (Claim 5), the central processing unit 11 immediately processes the data after the data transfer is completed. You can

The attribute information holding means of the data transfer control unit 15 holds that the central processing unit 11 uses the data transferred from the external storage unit 16 to the main storage unit 13 immediately after the transfer as attribute information. Then, the attribute transfer information is notified to the switch transfer means 12A by the notification means (claim 6), whereby the switch transfer means 12A of the storage controller 12 is sent.
Can perform a switching transfer operation according to the attribute information from the notification means.

When data is transferred from the external storage unit 16 to the main storage unit 13, the notification means of the data transfer control unit 15 transfers the data for each predetermined data unit (ie, which layer of the storage mechanism is stored). Storage control unit 1 by notifying the changeover transfer means 12A (claim 7).
The second switching transfer unit 12A can switch and transfer each data to the cache memory 14 or the main storage unit 13 according to the attribute information given for each predetermined data unit.

[0057]

Embodiments of the present invention will be described below with reference to the drawings. (A) Description of Configuration of Information Processing Apparatus of this Embodiment FIG. 2 is a block diagram showing the configuration of an information processing apparatus as one embodiment of the present invention. In FIG. 2, 1 is a central processing unit (hereinafter , CPU), 2 is a storage control unit (hereinafter referred to as MCU), 3 is a main storage unit (hereinafter referred to as MSU), and MSU3 is a plurality of CPUs 1 through MCU2.
It is shared with.

Here, the MCU 2 is composed of each CPU 1 and MSU.
It controls the transfer of data to and from. Also,
Each CPU 1 is provided with a cache memory (hereinafter, referred to as LBS) that holds the data transferred from the MSU 3 via the MCU 2 in a swap method.

Further, 5 is a data transfer control unit (hereinafter referred to as M
This MOVER is basically configured in the same manner as the conventional one shown in FIG. 12, and each CPU 1 is triggered by the activation instruction from each CPU 1.
Reference numeral 1 refers to a command word 4A created in the LBS 4 or MSU 3 to control data transfer between the MSU 3 and an external storage unit (hereinafter referred to as ESU) 6 via the MCU 2.

In this embodiment, each CPU 1 is provided with a storage block transfer function unit (storage block transfer means) 1A. This storage block transfer function unit 1A
Shows that its own CPU1 sends MSU3 and ES to MOVER5.
When requesting a synchronous transfer command with U6, the storage block including the command word 4A and the transfer target data is transferred to L
The data is transferred from BS4 to MSU3.

The memory block transfer function unit 1A is C
When PU1 requests the mover 5 to start a synchronous transfer instruction, the process of MOVER 5 is started when the mover 5 cannot immediately start the data transfer indicated by the command word when receiving the start request from the CPU 1. Before that, a storage block including the command word and the data to be transferred may be transferred from the LBS 4 to the MSU 3 (described later with reference to FIG. 4).

Also, the mover 5 analyzes the storage address of the command word and data created by the CPU 1 and transfers the storage block containing the address specified by the mover 5 to the operation code issued by the mover 5 to the MCU 2 from the LBS 4 to the MSU 3. The storage block transfer function unit 1A of the CPU 1 stores the command code and data when the MOVER 5 issues the operation code to the MCU 2 after receiving the activation instruction from the CPU 1. May be transferred from the LSB 4 to the MSU 3 (described later with reference to FIG. 5).

On the other hand, the MCU 2 is provided with a selector (switch transfer means) 7. This selector 7 has been configured so that either one of the LBS 4 and the MSU 3 has been moved to the MOVER 5 in the past.
This is provided for switching connection so as to be communicable with the ESU 6 via the ESU 6, but in the present embodiment, the transfer destination of the data from the ESU 6 is switched from the MSU 3 to the LBS 4 and a part or all of the data is transferred to the LBS 4. It also functions as a switching transfer means.

If the selector 7 can determine that the CPU 1 will use the data transferred from the ESU 6 to the MSU 3 immediately after the transfer is completed, based on the type of the data transfer command instructed by the command word from the CPU 1, It has a function of switching the data transfer destination from the MSU 3 to the LBS 4 and transferring a part or all of the data to the LBS 4.

At this time, as will be described later with reference to FIG.
The OVER5 [MSU access control mechanism 52 (see FIG. 12)] holds an attribute information holding unit 5A that holds, as attribute information, that the CPU 1 uses the data transferred from the ESU 6 to the MSU 3 immediately after the transfer, and this attribute information holding The notification function unit (notifying means) 5B for notifying the selector 7 of the MCU 2 of the attribute information held in the unit 5A,
The selector 7 of U2 may perform the switching transfer operation according to the attribute information from the notification function unit 5B.

Also, as will be described later with reference to FIG.
ER5 [MSU access control mechanism 52 (see FIG. 12)]
In addition, when data is transferred from the ESU 6 to the MSU 3, the transfer storage destination of the data is set to the MCU 2 for each predetermined data unit.
The selector 7 of the MCU 2 can also be configured to perform a switching transfer operation according to the attribute information from the notification function unit 5C.

Also in this embodiment, as in the case shown in FIG. 10, 8A is the tag portion of the LBS4 on the CPU 1 (see FIG. 15 for details), and this tag portion 8A is the LBS4.
The tag information, which is entry information for identifying the data registered in, is stored in the LBS 4, and the LBS 4 holds the tag information and the data as one entry. Further, a tag section 8B is also provided on the MCU 2 (see FIGS. 2 and 15), and the LBS 4 of each CPU 1 is attached to this tag section 8B.
A copy of the tag information held by the tag unit 8A is held.

(B) Description of Operation Example at the Time of Synchronous Transfer Request Next, the operation at the time of the synchronous transfer request of this embodiment will be described with reference to FIGS. CPU1 is command word 4A
Is created on LBS4 and the head MS of command word 4A
U Move absolute address, access attribute information, etc.
Conventional procedure (see A1 to A3 in FIG. 13) until sending to 5
Command word 4A as in MSU3 or LBS
4 (see A11 in FIG. 3), write only on LBS4 (see A12 in FIG. 3), and CPU1 moves to MOVER.
5, the head MSU absolute address of the command word 4A, access attribute information, etc. are sent to issue a transfer start request (see A13 in FIGS. 2 and 3).

However, in this embodiment, after the CPU 1 sends the access request to the MOVER 5, the CPU 1
It does not immediately stop (interlock) as in the past. The CPU 1 determines whether the block including the head MSU absolute address of the command word 4A exists in the LBS 4 by checking the tag portion 8A of the LBS 4, and when the command word 4A is included in the LBS 4,
After instructing the LBS4 to transfer the command word 4A to the MSU3 (see A14 in FIG. 3), the memory block transfer function unit 1A transfers the memory block including the command word 4A from the LBS4 to the MSU3 via the MCU2 ( (See A15 in FIGS. 2 and 3), the tag portion 8 in the LBS 4
An internal instruction for invalidating the entry in which the command word 4A of A is held is added.

That is, the CPU 1 sends the access request to the MO
After sending to the VER5 (see A13 in FIGS. 2 and 3), the storage block transfer function unit 1 is executed by executing the internal instruction.
A transfers command word 4A from LBS4 to MSU3. Further, the command word 4A is MSU3, E
Absolute address of MSU3 and ESU for transfer between SU6
6 is associated with the real address (see FIG. 11).
Mover 5 has a designated MS
Data is transferred between the U absolute address and the ESU real address.

Therefore, access is made from MSU3 to ESU6.
When it is a data transfer to LBS4, as in the case of the command word, the CPU1 uses the data of the specified MSU absolute address before sending the data to ESU6 by using the above internal instruction, and when the data is in LBS4. M by own control
It is possible to transfer to SU3. In this way, all command words and data are sent from the LBS4 to the MS.
After the U3N transfer, the CPU 1 enters the interlock state and remains in the stopped state until MOVER 5 issues an interrupt indicating the end of transfer (see B18 in FIGS. 2 and 9).

On the other hand, the MOVER 5, which has received the access request from the CPU 1, discriminates whether the access is a synchronous transfer or an asynchronous transfer based on the attribute information of the request (A in FIG. 3).
16), if the requested access is executable, the MCU 2 is requested to read the command word 4A (see A17 in FIG. 3). A copy of the tag portion 8A of the LBS 4 in each CPU 1 is included in the MCU 2 in the MCU 2.
Since it is held in B, the MCU 2 receives the read request for the command word 4A from MOVER 5, and the tag unit 8
Referring to B, a command word read request is issued to MSU 3 (see A18 in FIG. 3).

In this embodiment, as shown in FIG.
In parallel with the processing of ER5, CPU1 LBS4 to MSU
Since the process of transferring the command word 4A to the MSU 3 is performed, the command word 4A is stored in the MSU 3 at the time when the MCU 2 issues the command word read request to the MSU 3 as described above. Therefore, MSU3
When the command word read request from the MCU 2 is received, the command word 4A is transferred to the MCU 2 (A in FIG. 3).
19), and the MCU 2 has its command word 4
Transfer A to MOVER5 (see A20 in FIG. 3).

Thereafter, as in the conventional procedure described with reference to FIG. 13, in MOVER 5, the contents of MCW are MSU 3
When the data transfer from ESU6 to ESU6 is specified, MCU
It is determined whether the data transferred from 2 is MSW, MCW or the transfer target data between MSU3 and ESU6 (see A21 in FIG. 3), and the command word for synchronous transfer is analyzed, The instruction latch currently being executed is selected, the ESU 6 is activated, and data transfer between the MSU 3 and the ESU 6 is started (see A22 in FIG. 3).

As described above, according to this embodiment, the CPU 1
Since the execution of the internal instruction by MPU5 is performed in parallel with the operation of MOVER5 immediately after the command word 4A is supplied to MOVER5, the CPU1 sends this data to MCU2 rather than issuing a data transfer request to MCU2. The time to start transferring to MSU3 is fast enough. Therefore, in MOVER5, most of all necessary data is MS.
Since it exists on U3, the data transfer processing can be performed at high speed, as is apparent from the comparison between the conventional example of FIG. 13 and this embodiment of FIG.

(C) Description of Operation Example During Standby for Synchronous Transfer In the operation example shown in FIG. 3, when a synchronous transfer request is made, the storage block transfer function unit 1A transfers storage blocks from LBS 4 to M.
Although the case of transferring to SU3 has been described, for example, C
The storage block transfer function unit 1A transfers the storage block from the LBS 4 to the MS by using the state in which the PU 1 is in the state of waiting for the synchronous transfer.
You may make it transfer to U3. Hereinafter, such a case will be described with reference to FIG.

In the configuration in which the MOVER 5 is shared by a plurality of CPUs 1, when the MOVER 5 receives from the CPU 1 the start address of the command word 4A and the transfer request, the MOVE 5 has already received the transfer request from another CPU 1, In the state where the transfer received in step 5 is being executed, if the data transfer request being executed that is received earlier by MOVE5 is a synchronous transfer, the execution is completed even if a new transfer request is received. The CPU 1 stops and waits until this happens, but in the present embodiment, the memory of the CPU 1 that is substantially stopped by waiting for the completion of the synchronous transfer is waited until the MCU 2 executes the re-request after the elapse of a certain time. Using the block transfer function unit 1A,
Command word and data from LBS4 to MSU3
It can be left out.

That is, in this embodiment, MOVER5 is CP.
When receiving a transfer activation request from U1 (see C10 in FIG. 16), ESU6 determines that the new transfer activation request cannot be immediately accepted during data transfer by MOVER5 (see C11 in FIG. 16). , Returns a code indicating that it was not accepted to MCU2 (see C12 in FIG. 16), and further, MCU2 moves to MOVER.
The code from 5 is notified to the CPU 1 (see C13 in FIG. 4).

The CPU 1 notified of this code is released from the interlock state and checks whether the command word 4A and the data are in the LBS4 or the MSU 3 (see C14 in FIG. 4). The transfer function unit 1A causes the MSU 3 to partially or wholly
(See C15 in FIG. 4), the CPU 1 is again in the interlock state.

When the transfer start request is not accepted by MOVER5, the MCU2 which has received the code to that effect waits for a while and moves to MOVER5 after a certain time.
Issue the transfer request again (see C16 in FIG. 4). If the mover 5 can accept the request at the time of this re-request, as in FIG. 3, the mover 5 determines whether the access is synchronous transfer or asynchronous transfer, and if the requested access is executable, the mover 5 sends the request to the MCU 2. The command word 4A is requested to be read (see C17 in FIG. 4).

When the MCU 2 receives the read request for the command word 4A from the MOVER 5, the MCU 2 refers to the tag portion 8B and issues a command word read request to the MSU 3 (see A18 in FIG. 3). At this time, in this embodiment,
MOVE5 is in the process of executing another transfer request
When the transfer request from 1 cannot be accepted,
Since the interlock state of the CPU 1 is released and the command word 4A and the data are transferred from the LBS 4 to the MSU 3 by the storage block transfer function unit 1A, the mover
5 is ready to accept the new command, the command word 4A and the data from the LBS instead of the MSU3
Can be obtained from

Therefore, when the MSU3 receives the command word read request from the MCU2, it transfers the command word 4A to the MCU2 (see C19 in FIG. 4) and further the MCU.
2 transfers the command word 4A to MOVER 5 (see C20 in FIG. 4). After that, in MOVER5, when the content of the MCW designates data transfer from MSU3 to ESU6, whether the data transferred from MCU2 is MSW or MCW, MSU3 and ESU6.
Is to be transferred data, and the command word for synchronous transfer is analyzed, the instruction latch currently being executed is selected, and ESU6 is activated to transfer data between MSU3 and ESU6. Start (see C21 in FIG. 4).

As described above, until the mover 5 becomes ready to accept the data transfer and issues the command word 4A or the data transfer request to the MCU 2,
The command word 4A or data is transferred to the LBS 4 by using the CPU 1 which is substantially stopped while waiting for the end of the synchronous transfer.
From MSU2 to MSU2
Since all the data exist on the MSU 3, the data transfer process can be performed at high speed, as is apparent from the comparison between the conventional example shown in FIG. 16 and the present embodiment shown in FIG.

(D) Description of Storage Block Transfer Operation Example Using Operation Code Now, considering again the same situation as in the example described with reference to FIG. 4, another CPU while MOVER 5 is executing a synchronous transfer.
When the data transfer request is received from 1, MOVER 5 cannot be accepted. However, when MOVER 5 cannot execute new data transfer, CPU 1 moves to MOVE.
Until the R5 can be accepted, the data transfer start is retried to the MOVER5 at regular intervals.

At this time, since the head absolute address of the command word 4A created by the CPU 1 is sent to the MOVER 5, the block containing the MSU absolute address designated by the MOVER 5 and the MCU 2 is transferred to the storage block transfer function unit. If there is an operation code to transfer from LBS4 to MSU3 by 1A, MOVER
5 can be transferred from the LBS 4 to the MSU 3 in advance by the device itself according to a new command.

In the following, according to this embodiment, a plurality of LBSs 4 will be
A case of transferring continuous data of absolute addresses to the ESU 6 with a transfer length that requires the block will be described with reference to the flowchart shown in FIG. First MSU
The data of the absolute address and the data of the MSU absolute address that is separated from the head MSU absolute address by the capacity of the LBS block are L to which the head MSU absolute address belongs.
This entry is different from the BS block.

Here, all the data to be transferred are LBS4.
When MOVER 5 outputs a transfer request for the head absolute address to MCU 2 and transfers data to ESU 6, the LBS block containing the head MSU absolute address is L
As long as the data is transferred from BS4 to MSU3, and thereafter, as long as it is transferred from the same LBS block as the first MSU absolute address to ESU6, data is continuously transferred from MSU3 to ESU6.

When data that does not belong to the same block as the first MSU absolute address is to be transferred to ESU6, MOVER5 sends a data transfer request to MCU2.
, The data exists in the LBS4, so that the LBS block to which the data of the transfer target MSU absolute address belongs is transferred from the LBS4 to the MSU3 as in the case of the first MSU absolute address.

At this time, MOVER5 knows the head MSU absolute address and the transfer length, and the capacity of the block of LBS4 is a value peculiar to the information processing device. Therefore, MOVER actually outputs a transfer request to MCU2. Previously, the first MSU absolute address and the MSU absolute address of data belonging to another LBS block can be determined.

Therefore, by outputting the operation code for transferring the LBS block including the designated MSU absolute address from LBS4 to MSU3 in advance of the data transfer request to MCU2 of MOVER5,
Before the mover 5 outputs a data transfer request to the MCU 2, the memory block transfer function unit 1A transfers the data to the M
It becomes possible to transfer to SU3.

Here, considering the configuration of MOVER 5 shown in FIG. 12, MOVER 5 is transmitted from MSU 3 to E.
At the time of data transfer to the SU6, the adder 59 calculates the MSU absolute address in which the next data to be transferred is stored, and supplies the result to the MSU access control mechanism 52 to request the data transfer to the MCU2. Is issued. In addition, the MSU of the transfer target data to the ESU6 in the MSU3
The storage location indicated by the address obtained by adding the capacity of the storage block of the LBS4 to the absolute address is surely different from the storage location indicated by the MSU absolute address before the addition.
It exists in the memory block of 4.

That is, in this embodiment, the remaining transfer length is LB.
If it is larger than the S block (Y in step S1 of FIG. 5)
In the case of ES determination), the MSU absolute address obtained by adding the capacity of the storage block of LBS4 to the MSU absolute address at the start of transfer is held in a register (not shown) (step S2 in FIG. 5), and By issuing an ejection command (operation code) from MOVER5 to MCU2 using the MSU absolute address, from LBS4 newly added in this embodiment to MSU3,
The LBS block including the address of the register is transferred from the LBS 4 to the MSU 3 by the storage block transfer function unit 1A (step S3 in FIG. 5). The remaining transfer length is LB
If the number of blocks is less than or equal to S blocks (NO in step S1 of FIG. 5), the process immediately proceeds to step S4 described below.

Then, while judging whether or not the remaining transfer length has become 0 (step S4 in FIG. 5), if it is not 0,
While the MSU transfer start address sent from the MCU 2 by the MCW is added by the data request length by the adder 59, the MCU 2 is requested to read the data from the MSU 3 via the MSU access control mechanism 52, and the MSU address is added. At some time, the remaining transfer length is subtracted corresponding to the added address (step S5 in FIG. 5).

Thereafter, it is judged whether or not the MSU address is equal to the MSU absolute address held in the register (step S6 in FIG. 5). If they are not equal, the process returns to step S4, while if they are equal, Returning to step S1, when the remaining transfer length is still larger than the LBS block, the timing of the address match is used as a trigger,
LBS4 to the MSU absolute address held in the register
Using the MSU absolute address added by the capacity of the memory block of, the LBS4 flush command is issued and the MSU absolute address of the added result is held in the register repeatedly (steps S2 and S3 in FIG. 5). .

The above processing is repeatedly executed until it is determined in step S4 that the remaining transfer length is zero. In this way, before the command word 4A and the data are transferred from the mover 5 to the MCU 2, the LBS storage block can be ejected and the command word 4A and the data can be supplied to the mover 5 at high speed.

(E) Description of Operation Example at the End of Synchronous Transfer By the way, conventionally, when the transfer instruction was the data transfer from ESU6 to MSU3, all the data sent to MCU2 was stored in MSU3. ESU6
Some of the transfer commands for
There is a part where the data transferred from PU1 to ESU6 by MPU3 is used by PU1.
It is preferable to store in LBS4 rather than store in U3.

For example, IBM's "ENTERPRISE SYSTEMS"
An instruction generally called "COMPARE AND SWAP" published in ARCHITECTURE / 370, PRINCIPLES OF OPERATION controls one or more CPUs 1, MSUs 3 shared by each CPU 1, and a storage device including this MSU 3. The case where the MCU 2 and the MCU 2 are connected to each other (cluster, see FIGS. 2 and 7) will be described below.

The data prepared for the execution of this instruction includes the address (D2B2) on MSU3 shared by a plurality of CPUs 1 and the expected value (R1) that may be stored at the address indicated by D2B2. , And data (R3) newly stored at the address indicated by D2B2. When the operand of this instruction is CS, its format is as shown in (1) of FIG.

Here, R1, R3 and B2 use general-purpose registers in the CPU 1. The address of D2B2 is
It is obtained by adding the value of D2 to the contents of the general-purpose register indicated by B2, and a specific address is assigned to each area of MSU3. When you execute the command, MSU3
Data is fetched from the address indicated by D2B2.

The CPU 1 sends the fetched data to R1.
Compared with the contents of the register, fetched data and R1
If the contents of the register are the same, the contents of the R3 register are stored in the address on MSU3 indicated by D2B2, and the condition code indicating that the update was successful is notified to the software. Similarly, when the fetched contents and the contents of the R1 register do not match, the fetched contents are stored in the R1 register, and the condition code indicating the unsuccessful update is notified to the software.

After referring to the data stored in the address indicated by D2B2, the data is compared with the contents of the R1 register.
Until the contents of the register 3 are stored in the address indicated by D2B2, reading or writing of the other CPU1 to the address indicated by D2B2 is prohibited. PRINCIPLE OF O
In PERATION, the address specified by the above command is 1
Although it is an MSU address shared by one or a plurality of CPUs 1, as shown in FIG. 7, even when the ESU 6 is shared by one or a plurality of clusters 10-1 and 10-2, the instruction of the address of this instruction is given. An extension instruction that performs the same operation with the ESU address as the ESU address can be considered. When the operand of this extension instruction is CDSED, its format is as shown in (2) of FIG. Here, R1 and R3 are data stored in the register of the CPU 1 as in the case of the MSU 3 described above, and D2B2 indicates the address of the ESU 6. Then, an actual usage example of the extension instruction is as follows.

When the cluster 10-1 wants to use a certain area of the ESU 6, the cluster 10-1 is at a certain point in time.
Stores a value (here, "1") in ESU6. Next, when another cluster 10-2 stores a different value (here, "2") at the same address, the data "1" is stored at the address to which the cluster 10-1 has written the data "1" later. If the program is judged to have been written (the data "2" is actually stored) and the program is executed, the result obtained from it will be different from the expected result.

Therefore, an instruction obtained by extending the "COMPARE AND SWAP" instruction between the clusters 10-1 and 10-2 and the ESU 6 is used, and an area having the ESU 6 is used to generate the cluster 1
Control is performed so that another cluster 10-2 does not rewrite the same area when 0-1 performs processing. D2B2
As the address designated by, a specific address is prepared for each area of the ESU 6. Here, it is assumed that "0" is normally stored in the address indicated by D2B2,
“0” is set in the R1 register, “1” is set in R3 of the cluster 10-1, and “2” is set in the R2 register of the cluster 10-2.

The above instruction is executed before the CPU 1 of the cluster 10-1 uses a certain area. Therefore, the currently stored data is fetched (“0” in this case) from the storage device according to the address indicated by the R3 register (see FIG. 6), and the value of R1 is compared with the fetched value. In the example, the value of R1 is “0” and the fetched value is “0”, so the value of R3 “1” is stored in D2B2 (lock flag) (see FIG. 6), and the code indicating the successful update is Software is notified.

If the update is successful, C of the cluster 10-1
PU1 has acquired the right to use a certain area of ESU6 (see FIG. 6), executes the processing of using the area of ESU6, and when the processing is completed, the address indicated by D2B2 is " 0 "is stored (see FIG. 6).
If the CPU 10 of another cluster 10-2 tries to use the same area while the cluster 10-1 is using a certain area of the ESU 6, the CPU 1 of the cluster 10-2 will also be
Before using the area of U6, the extension command of "COMPARE AND SWAP" is executed in the same manner as in the case of the cluster 10-1 described above.

Then, the currently stored data is fetched from the storage device according to the address indicated by D2B2 and stored in a predetermined position on MSU3. At this time, since the cluster 10-1 has rewritten its address to "1", "1" is fetched (see FIG. 6). Then, the value of R1 is compared with the data stored in MSU3. In this case, R1 is "0", MSU.
Since the fetched data stored in 3 is "1", they do not match, the update is unsuccessful, "1" is stored in R1, and the code indicating the unsuccessful update is notified to the software.

When the unsuccessful update is notified, if a value unique to each of the clusters 10-1 and 10-2 is written in D2B2, then the cluster using the device (ESU6) is known. It is possible to rewrite R1 to the original value (“0” in this example) and update “COMPARE AND SWA
Repeat the extended instruction of “P”. “COMPARE AND SWA
While the extended instruction of P "is being executed, D2 of another cluster 10-1
Since updating or reference of the address indicated by B2 is prohibited, it is possible to control the usage right of the storage area managed by the lock flag.

Here, when the CPU 1 of the cluster 10-1 or 10-2 uses the ESU 6, the extension instruction of "COMPARE AND SWAP" is issued according to the above-mentioned example, and the use right of the area desired to be used by the ESU 6 is issued. Then, access ESU6 (see FIG. 7). If there is a mismatch as a result of executing the instruction, it is necessary to store the data fetched and stored on the MSU 3 in the register in the CPU 1 according to the above example (see FIG. 7). This means that the data fetched and stored on the MSU3 is the LB of the CPU1.
Since the time to store the data in the register is shorter when the data is stored in S4, it means that the instruction can be executed faster.

In the case of this instruction, data is not transferred from the ESU 6 to the CPU 1 which issued the instruction except the notification of the transfer status after the access except this time.
PU1 can add an attribute that data is unconditionally stored in LBS4 via selector 7 while ESU6 is executing this instruction. Then, as shown in FIG. 7, an attribute information holding unit 5 capable of storing and holding this attribute information.
A is provided in MOVER5 and MO is used when notifying the start address of the command word or in the command word.
By notifying the VER 5, the attribute information is held in the attribute information holding unit 5A. In addition, a notification function unit 5B for notifying the selector 7 of the MCU 2 of the attribute information held in the attribute information holding unit 5A is provided in the MOVER 5 [MSU access control mechanism (see reference numeral 52 in FIG. 12)].

With this configuration, MOVER5
When it transfers data to MCU2,
If this attribute is notified to the MCU2 using the U access control mechanism (see reference numeral 52 in FIG. 12), the MCU2 judges whether the data is stored in the LBS4 or the MSU3, and the selector 7 switches and transfers the data. It is possible to Alternatively, MOVER 5 can use the MSU access control mechanism to send this attribute to MCU 2 when transferring the transfer data from ESU 6 to MSU 3.

As a result, instructions can be executed at high speed, the data transfer speed can be increased, the lock retention period can be shortened, and the system performance can be greatly improved. (F) Description of another operation example at the end of synchronous transfer Now, when the CPU 1 issues a transfer instruction to the ESU 6, the data is directly transferred from the ESU 6 to the LBS 4 so that the CPU 1 uses the transfer data from the ESU 6 immediately after the transfer is completed. As an example of storing, in FIG. 6 and FIG. 7, “COMPARE AN
Although the case has been described in which the update fails when an extension command of "D SWAP" is issued and a code indicating the update failure is notified, as described above with reference to FIG. 14, for example, a command word including transfer end information (error information, etc.) Also, ESU6
It is preferable to store it in LBS4 rather than store it in MSU3.

For example, when the CPU 1 requests the ESU 6 for data transfer, it creates a command word frame (see reference numeral 4A in FIG. 2) and sets the start address of the frame to MO.
The VER5 is notified and the MOVER5 obtains the start address from the MSU3 or the LBS4.
Then, at the end of the data transfer, the ESU 6 has the same fixed bit (MSW) of the frame of the command word as when the request for the data transfer information such as error information is received.
Store). At the time of data transfer from ESU6 to MSU3, the data transferred from MOVE5 to MCU2 are transfer target data and transfer end information.

At this time, all the data to be transferred are transferred to the LBS.
As described above, storing the data in ESU 4 may cause a necessary cache entry to be expelled from LBS 4 to MSU 3, and may adversely affect the data processing performance. LBS
I can't register for 4. Therefore, also in this embodiment, the transfer target data is stored in the MSU 3 via the selector 7.

However, the transfer end information has a smaller data size than the transfer target data, and the CPU 1 refers to the transfer end information immediately after the transfer end interrupt is applied to the CPU 1. At this time, whether it is better to store the data in the LBS4 or the MSU3,
Since it does not depend on the type of command for data transfer between ESU6 and MSU3, it is impossible for CPU1 to add an attribute indicating whether the data is sent to LBS4 or MSU3.

In this case, as shown in FIG.
5 to MCU2 signal, MOVER5 to MC
A signal indicating the attribute that data to be transferred to U2 is transferred to LBS4 instead of MSU3 is added, and MOVER5 is added.
The notification function unit 5C of the (MSU access control mechanism 52) adds the attribute signal to each data and notifies the selector 7 of the MCU 2 of it.

If it is desired to add the attribute that the transfer end information is transferred to the LBS4, when the end information is transferred to the MCU2, the remaining transfer length (described above with reference to FIG. 12) held in the MOVE5 as the transfer status signal is set. On the basis of,
It is possible to determine whether or not the signal to be transferred to the MCU 2 is transfer end information. This allows the MSU access control mechanism 52 to be used to notify the MCU 2 of the signal to transfer the data to the LBS 4.

With this configuration, as shown in FIG. 8, the MOVER 5 uses the new addition signal when transferring the data transfer information at the end of the data transfer to the MCU 2, and uses the end code of the command word from the MOVER 5. In response to the new addition signal (attribute), the MCU 2 receiving the request to store the data switches the selector 7 from the MSU 3 side to the LBS 4 side of the CPU 1 so that the data is transferred to the LSU instead of the MSU 3.
It becomes possible to store in BS4.

Next, referring to FIG. 9, the operation of this embodiment when transferring the transfer end command and the end information such as an error to the CPU 1 at the end of transfer (or when an error is detected) will be described. Note that this FIG. 9 corresponds to FIG.
This corresponds to the conventional one described in 4. MOVER
5 has set a flag indicating that all the data has been transferred to ESU6 after transferring the last data to ESU6.
Send to 6. ESU6 finishes processing all data,
Alternatively, when an error is detected, the transfer end command and end information such as an error are notified to the MOVER 5 (see B12 in FIG. 9). After all data is transferred, move 5
Writes error information and the like into a predetermined field in the MSW of the command word (see B13 in FIG. 9).

MOVER 5 requests the MCU 2 to store the MSW containing the error information and the like (B1 in FIG. 9).
4), when the data is sent from MOVER5 to MCU2, MCU2 switches the selector 7 according to the attribute given to MSW from MOVER5, as shown in FIG. Request a store (see B15 in FIG. 9).
At this time, all the data is stored in the MSU 3 as in the conventional case.

When the LBS 4 completes the MSW store, M
Notify CU2 of normal end (see B16 in FIG. 9),
Further, the MCU 2 sends the normal end notification to the MOVER 5
(See B17 of FIG. 9). In this way, the MOVER 5, which has finished storing the MSW in which the error information and the like have been written, in the LBS 3 and received the normal termination notification, issues an interrupt to the CPU 1 as the access request source to terminate the command transfer (B18 in FIG. 9). ), The interlock of the CPU 1 is released.

Thereafter, the CPU 1 requests the MSB having the transfer end information (error information or the like) to the LBS 4 in order to check the transfer end information stored in the MSW (see B19 in FIG. 9), Check the error information and status information of the MSW and end the synchronous transfer (B2 in FIG. 9).
0). As described above with reference to FIGS. 6 to 9, according to the present embodiment, the data to be transferred is MS
Stored in U3, for data elements that require high speed (such as update failure code and transfer end information),
According to the attribute set in MOVER5, the data is written directly to LBS4 instead of MSU3. Therefore, as is clear from comparison between the conventional example of FIG. 14 and this embodiment of FIG. 9, MSU3 and ESU6 After the interruption indicating that the data transfer is completed at the end of the data transfer between the CPU 1 and the data stored in the MSU 3 is referred to, the CPU 1 can refer to the data transfer end code at a higher speed than in the case of referring to the data. The performance of can be greatly improved.

[0122]

As described above in detail, according to the information processing apparatus (Claim 1) of the present invention, the central processing unit of the self processing unit is provided between the main storage unit and the external storage unit with respect to the data transfer control unit. When requesting the synchronous transfer instruction of, the storage block transfer means transfers the storage block including the command word and the transfer amount data from the cache memory to the main storage unit. Therefore, the command from the data transfer control unit to the storage control unit is issued. When a fetch request for a word and data to be transferred is made to the storage controller, the command word and the data to be transferred on the main memory can be immediately supplied from the main memory to the data transfer controller. The data transfer process can be performed at high speed.

Further, when the data transfer control unit cannot immediately start the data transfer instructed by the command word when the synchronous transfer start request is received from the central processing unit, before the data transfer control unit starts processing, By transferring the storage block including the command word and the transfer target data from the cache memory to the main storage unit by the storage block transfer means (claim 2), the processing by the data transfer control unit can be started and the command word and the main When the fetch request for the data to be transferred on the storage unit is issued to the storage control unit, the command word and the data can be immediately supplied to the data transfer control unit, and the data transfer processing can be performed at high speed. .

Further, the operation code issued by the data transfer control unit to the storage control unit is provided with a request code for transferring the storage block including the address designated by the data transfer control unit from the cache memory to the main storage unit. When the operation code is issued from the data transfer control unit, the storage block transfer unit transfers the storage block including the command word and the data from the cache memory to the main storage unit in advance (claim 3). The command word and the data can be immediately read by the data transfer control unit, and the data transfer process can be performed at high speed.

On the other hand, the information processing apparatus of the present invention (claim 4).
According to the above, the switching transfer means of the storage control unit can switch the transfer destination of the data from the external storage unit from the main storage unit to the cache memory and transfer a part or all of the data to the cache memory. The data element that requires high speed in the process can be directly written into the cache memory as needed, and the data transfer process can be performed at high speed.

At this time, based on the type of data transfer instruction given by the command word from the central processing unit, the data transferred from the external storage unit to the main storage unit by the central processing unit may be used immediately after the transfer. If it is possible to make a decision, the switching transfer means transfers a part or all of the required data to the cache memory instead of the main memory (Claim 5). The processing can be performed immediately, and the data transfer processing can be performed at high speed.

Further, the attribute information holding means of the data transfer control unit holds that the central processing unit uses the data transferred from the external storage unit to the main storage unit immediately after the transfer is completed as attribute information, and the attribute thereof. By notifying the information to the switching transfer means by the notifying means (claim 6), the switching transfer means of the storage control unit performs the switching transfer operation according to the attribute information from the notifying means, and after the data transfer is completed, the central processing is performed. The arithmetic processing unit can immediately process the data, and the data transfer processing can be performed at high speed.

Furthermore, when data is transferred from the external storage unit to the main storage unit, the notification means of the data transfer control unit notifies the switching transfer means of the transfer storage destination of the data for each predetermined data unit. (Claim 7) According to the attribute information given to each predetermined data unit by the switching transfer means of the storage control unit, each data is switched and transferred to the cache memory or the main storage unit, and the central processing is performed after the data transfer is completed. The department can process the data immediately,
The data transfer process can be performed at high speed.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram showing a configuration of an information processing apparatus as an embodiment of the present invention.

FIG. 3 is a diagram for explaining an operation when a synchronous transfer request is made in the present embodiment.

FIG. 4 is a diagram for explaining an operation during standby for synchronous transfer according to the present embodiment.

FIG. 5 is a flow chart for explaining a memory block transfer operation according to an operation code of this embodiment.

FIG. 6 is a diagram for explaining the operation of the present embodiment.

FIG. 7 is a block diagram for explaining the configuration and operation of the present embodiment.

FIG. 8 is a block diagram for explaining the configuration and operation of the present embodiment.

FIG. 9 is a diagram for explaining an operation at the end of the synchronous transfer according to the present embodiment.

FIG. 10 is a block diagram illustrating a configuration example of a general information processing device.

FIG. 11 is a diagram showing an example of a general command word.

FIG. 12 is a block diagram showing a configuration of a general data transfer control unit (MOVER).

FIG. 13 is a diagram for explaining an operation example when a conventional synchronous transfer request is made.

FIG. 14 is a diagram for explaining an example of operation at the end of conventional synchronous transfer.

FIG. 15 is a diagram showing an example of data storage of a tag part.

FIG. 16 is a diagram for explaining an operation example in the conventional standby for synchronous transfer.

[Explanation of symbols]

1 central processing unit (CPU) 1A storage block transfer function unit (storage block transfer means) 2 storage control unit (MCU) 3 main storage unit (MSU) 4 cache memory (local buffer storage unit, LB)
S) 4A command word 5 data transfer control unit (MOVER) 5A attribute information holding unit (attribute information holding unit) 5B, 5C notification function unit (notification unit) 6 external storage unit (ESU) 7 selector (switching transfer unit) 8A, 8B Tag unit 10-1, 10-2 Cluster 11 Central processing unit (CPU) 11A Storage block transfer means 12 Storage control unit (MCU) 12A Switching transfer means 13 Main storage unit (MSU) 14 Cache memory (LBS) 15 Data Transfer control unit (MOVER) 16 External storage unit (ESU) 50A to 50D Data bus 51 Latch unit 52 MSU access control mechanism 53 Data / command determination unit 54 Synchronous / asynchronous transfer determination unit 55 Synchronous transfer latch unit 56 Asynchronous transfer latch Part 57, 58 Selector 59 Adder

Continued Front Page (72) Inventor Aiichiro Inoue 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Teru Watanabe 1015, Uedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Kasumi Koike 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Motoyoshi Hirose, 1015, Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited (72) Inventor Shinta Yutaro, Kanagawa Prefecture 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Fujitsu Limited

Claims (7)

[Claims] 1. A plurality of central processing units (11) and a main storage unit (1) shared by the plurality of central processing units (11).
3), each central processing unit (11) and the main storage unit (1)
Storage controller (1) for controlling data transfer to and from
2), each of the central processing units (11) described above has the storage control unit (1).
A cache memory (1) that holds the data transferred from the main storage unit (13) via the swap method by the swap method.
4), and each of the central processing units (11) in the cache memory (14) or the main storage unit (13) is triggered by the activation instruction from each of the central processing units (11). The storage controller (12) by referring to the command word created in
A data transfer control unit (15) for controlling data transfer between the main storage unit (13) and the external storage unit (16) via
In the information processing device comprising: a central processing unit (11), the central processing unit (11) includes a data transfer control unit (1).
5) to the main storage unit (13) and the external storage unit (1)
Storage block transfer means (11A) for transferring a storage block including the command word and transfer target data from the cache memory (14) to the main storage unit (13) when requesting a synchronous transfer instruction to and from (6). ) Is provided, the information processing apparatus characterized by the above. 2. When the central processing unit (11) requests the data transfer control unit (15) to activate a synchronous transfer instruction, the data transfer control unit (15) causes the central processing unit to operate. When the data transfer instructed by the command word cannot be immediately started when the activation request is received from (11), the storage block transfer means (11A) of the central processing unit (11) transfers the data transfer. The storage block including the command word and the transfer target data is transferred from the cache memory (14) to the main storage unit (13) before the processing of the control unit (15) is started. 1. The information processing device according to 1. 3. The data transfer control unit (15) analyzes a storage address of a command word and data created by the central processing unit (11), and the data transfer control unit (15) stores the storage control unit. The operation code issued to (12) includes a request code for transferring a storage block including an address designated by the data transfer control unit (15) from the cache memory (14) to the main storage unit (13). , The data transfer control unit (15) is connected to the central processing unit (1
1) after receiving the activation instruction from the storage control unit (1
When the operation code is issued to 2), the storage block transfer means (11A) of the central processing unit (11) stores a storage block including a command word and data from the cache memory (14). The information processing apparatus according to claim 1, wherein the information processing apparatus transfers the information to a main storage unit (13). 4. A plurality of central processing units (11) and a main storage unit (1) shared by the plurality of central processing units (11).
3), each central processing unit (11) and the main storage unit (1)
Storage controller (1) for controlling data transfer to and from
2), each of the central processing units (11) described above
It has a cache memory (14) for holding the data transferred from the main storage unit (13) via the storage control unit (12) by a swap method, and also has a cache memory (14) from each of the central processing units (11). The storage control unit (12) refers to a command word created in the cache memory (14) or the main storage unit (13) by each of the central processing units (11) upon activation instruction.
A data transfer control unit (15) for controlling data transfer between the main storage unit (13) and the external storage unit (16) via
In the information processing apparatus comprising the above, the transfer storage destination of the data from the external storage unit (16) is switched from the main storage unit (13) to the cache memory (14), and a part or all of the data is cached. A switching transfer means (12A) for transferring to the memory (14) is provided in the storage control unit (12),
Information processing equipment. 5. The switching transfer means (12A) uses the data transferred by the central processing unit (11) from the external storage unit (16) to the main storage unit (13) immediately after the transfer is completed. If it can be determined from the central processing unit (11) based on the type of the data transfer instruction designated by the command word, the transfer storage destination of the data is transferred from the main storage unit (13) to the cache memory. (1
The information processing apparatus according to claim 4, wherein a part or all of the data is transferred to the cache memory (14) by switching to 4). 6. The data transfer control unit (15) uses the data transferred from the external storage unit (16) to the main storage unit (13) by the central processing unit (11) immediately after the transfer is completed. The attribute information holding means for holding the information as attribute information, and the notifying means for notifying the switching transfer means (12A) of the storage control unit (12) of the attribute information held by the attribute information holding means. The switching transfer means (12A) of the storage control unit (12) is
The information processing apparatus according to claim 5, wherein the switching transfer operation is performed according to the attribute information from the notification means. 7. The data transfer control unit (15), when data is transferred from the external storage unit (16) to the main storage unit (13), a transfer storage destination of the data for each predetermined data unit. Is provided to the switching transfer means (12A) of the storage control unit (12), the switching transfer means (12A) of the storage control unit (12),
5. The information processing apparatus according to claim 4, wherein the switching transfer operation is performed according to the attribute information from the notification means.