JPH0722939A - Logic circuit - Google Patents

Abstract

PURPOSE:To always make the logical threshold value of an input logic circuit constant regardless of the fluctuation of a power supply voltage. CONSTITUTION:A constant voltage is supplied to the source terminal of a transistor 151 constituting an inverter. The constant voltage is generated based on a reference voltage VREF by a transistor 1533 and a current source 154. Also, a transistor 155 and an inverter 156 are connected with an output terminal 158, and a voltage VREF-VBE level supplied to the output terminal 158 is increased to a power supply voltage VCC level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit, and more particularly to a logic circuit which always outputs a signal of a stable logic level even if the power supply voltage level changes.

[0002]

[Prior Art 1] FIG. 19 shows a general SRAM.
It is a block diagram which shows schematic structure of (Static Randam Access Memory). Referring to FIG. 19, this SRAM is
A memory cell array 1, a row address buffer 2, a row decoder 3, a column address buffer 4, a column decoder 5, a bit line load 6, a write driver 7,
An R / W control circuit 8, a sense amplifier 9, and a data input / output buffer 10 are provided.

Memory cell array 1 includes a plurality of word lines (not shown) and bit lines (not shown) arranged so as to intersect with each other, and memories arranged at respective intersections of these word lines and bit lines. And a cell (not shown).

Next, the operation of this SRAM will be briefly described. The row address buffer 2 and the row decoder 3 select one word line of the memory cell array 1, and the column address buffer 4 and the column decoder 5 select one bit line of the memory cell array 1. As a result, one memory cell arranged at the intersection of the selected word line and bit line is selected. Then, the data is written in the selected memory cell or the data stored in the memory cell is read.

In writing data, first, both write enable signal / WE and chip select signal / CS input to R / W control circuit 8 are set to L level. Next, the input data DQ to be written is input / output pin 1
1 and is stored in the selected memory cell via the data input / output buffer 10 and the R / W control circuit 8.

On the other hand, in the reading of data, the data stored in the selected memory cell is detected and amplified by the sense amplifier 9, and further taken out from the input / output pin 11 via the data input / output buffer 10. To be done.

FIG. 20 is a specific circuit diagram showing a part of the row address buffer 2 or the column address buffer 4 shown in FIG.

Referring to FIG. 20, this address buffer 2 or 4 is provided with an input logic circuit 12 at the first stage thereof.
The input logic circuit 12 includes a complementary (CMOS) inverter including an enhancement type P channel MOS transistor 121 and an N channel MOS transistor 122, and a P channel MOS transistor 123 for activating the inverter.

The CMOS inverter and the P-channel MOS transistor 123 are connected in series between the power supply 100 and the ground 102.

The input logic circuit 12 is a TTL interface which converts a TTL level signal Vi received from the outside into a CMOS level and supplies the CMOS level signal Vi to the inside.

Generally, in the case of the TTL level, the H level corresponds to 2.2V and the L level corresponds to 0.8V. On the other hand, in the case of CMOS level, H level corresponds to 5V and L level
The level corresponds to 0V. Therefore, the amplitude of the TTL level is smaller than that of the CMOS level, and the H level is high.
The voltage corresponding to the level is low.

Therefore, the logic threshold value of the input logic circuit 12 is 1.5, which is an intermediate voltage between 2.2V and 0.8V.
It is set to V. Such a logical threshold value is obtained by setting the size of the N-channel MOS transistor 122 to P, for example.
It is realized by multiplying the channel MOS transistor 121 by 4 to 6 times.

The output signal V of the input logic circuit 12
o is provided to the inside through inverters 131, 132 and 133.

[Prior Art 2] FIG. 22 is a circuit diagram showing a general CMOS inverter. Referring to FIG. 22, the inverter 14 includes a P-channel MOS transistor 14
1 and N-channel MOS transistor 142. These transistors 141 and 142 are connected to the power source 1
00 and ground 102 are connected in series.

According to the inverter 14, the input signal V
When i is at L level (0 V), the transistor 141 is turned on and the transistor 142 is turned off, so that the output signal Vo becomes H level (V _CC ). On the other hand, the input signal V
When i is at H level, the transistor 141 is turned off and the transistor 142 is turned on, so that the output signal V
o becomes L level.

[0016]

[Prior Art 1] FIG. 21 is a graph showing the power supply voltage V _CC dependency of the output voltage Vo by the input logic circuit 12 shown in FIG.
o, and the horizontal axis represents the input voltage Vi.

As is apparent from this graph, when the power supply voltage V _CC is 5.0V, the logic threshold value of the input logic circuit 12 is 1.50V. Therefore, when the input voltage Vi is lower than 1.50V, the output voltage Vo becomes 5.0V, and when the input voltage Vi is higher than 1.50V, the output voltage Vo becomes 0V.

However, the power supply voltage V _CC is always 5.0.
It may vary between 4.5 and 5.5V instead of V.

When the power supply voltage V _CC is 4.5V, the logic threshold value of the input logic circuit 12 is 1.45V. Therefore, when the input voltage Vi is lower than 1.45V, the output voltage Vo becomes 4.5V, and when the input voltage Vi is higher than 1.45V, the output voltage Vo becomes 0V.

When the power supply voltage V _CC is 5.5V, the logic threshold value of the input logic circuit 12 is 1.55V. Therefore, when the input voltage Vi is lower than 1.55V, the output voltage Vo becomes 5.5V, and the input voltage Vi is 1.55V.
When higher than V, the output voltage Vo becomes 0V.

As described above, the logic threshold value of the input logic circuit 12 depends on the power supply voltage V _{CC because} it is a P channel MOS.
This is because the gate-source voltage V _{GS of the} transistor 121 similarly changes with the change of the power supply voltage V _CC .

Particularly when the power supply voltage V _CC is 4.5 V,
There is a problem that the rise time of the output signal Vo becomes long and the operation speed becomes slow. Further, the SRAM using such an input logic circuit 12 has a problem that the access time is delayed.

[Prior Art 2] FIG. 23 shows the CM shown in FIG.
6 is a timing chart showing the operation of the OS inverter 14.

Referring to FIG. 23, when input signal Vi falls from H level to L level, output signal Vo rises from L level to H level. However, the input signal Vi
If the noise N enters the power supply voltage V _CC when the signal is at the L level, there is a problem that the noise N also enters the output signal Vo. This is because when the input signal Vi is at L level, the P-channel MOS transistor 141 is on and the power supply voltage V _CC is output as it is through the transistor 141. Therefore, there is a problem that a circuit in the next stage that receives the output signal Vo is likely to malfunction.

The present invention has been made to solve the above problems, and its object is to reduce the power supply voltage dependency of a logic circuit.

Another object of the present invention is to improve the operation speed of a logic circuit. Still another object of the present invention is to reduce the influence of power supply voltage noise on the logic circuit.

[0027]

The first invention is the first invention.
And, in response to the logic level of the signal received from the outside through the input terminal, based on the two different voltages supplied from the second power supply, the signal at the predetermined logic level is output through the output terminal. Which is a logic circuit which is internally provided
It includes a conductive channel type field effect transistor, a second conductive channel type field effect transistor, a constant voltage means, and a voltage compensating means.

The first conductive channel type field effect transistor has a gate terminal connected to an input terminal, one conductive terminal,
And the other conduction terminal connected to the output terminal. Second
The conductive channel type field effect transistor has a gate terminal connected to the input terminal, one conduction terminal connected to the second power supply, and the other conduction terminal connected to the output terminal.

The constant voltage means supplies a constant voltage to one conduction terminal of the first conductive channel type field effect transistor without depending on the fluctuation of the voltage supplied from the first power source. The voltage compensating means shifts the voltage level to the voltage level supplied by the first power supply only when a constant voltage is generated at the other conduction terminal of the first conductive channel field effect transistor.

Also, in the above logic circuit, the constant voltage means includes a bipolar transistor and a current source means, and the voltage generated at the emitter terminal of the bipolar transistor is used as a constant voltage for the first conductive channel type electric field. Supply to one conduction terminal of the effect transistor.

The bipolar transistor has a base terminal for receiving a constant reference voltage, a collector terminal connected to the first power supply, and an emitter terminal connected to one conduction terminal of the first conductive channel field effect transistor. The current source means supplies an emitter current to the bipolar transistor.

On the other hand, the second invention is based on the first and second aspects.
Is a logic circuit that receives one or more input signals and generates a predetermined output signal based on two different voltages supplied from the power source, the logic operation means and the first conductive channel type A field effect transistor and a constant voltage means are provided.

The logical operation means includes a first power supply terminal and a second power supply terminal connected to the second power supply, and based on the voltage supplied from the first and second power supply terminals,
Logically operates one or more input signals and outputs the result as an output signal. The first conductive channel field effect transistor has a gate terminal, one conduction terminal connected to the first power supply terminal of the logic operation means, and the other conduction terminal connected to the first power supply. The constant voltage means is the first
Without depending on the fluctuation of the voltage supplied from
A constant voltage is supplied to the gate terminal of the first conductive channel field effect transistor.

Further, in the logic circuit, the constant voltage means includes a resistance means and a capacitance means. The resistance means is
It is connected between the first power supply and the gate terminal of the first conductive channel field effect transistor. The capacity means is the second
Of the power source and the gate terminal of the first conductive channel field effect transistor.

A logic circuit which receives one or more input signals and generates a predetermined output signal based on two different kinds of voltages supplied from the first and second power supplies, It is provided with a logical operation means, a first conductive channel type field effect transistor, a first constant voltage means, a second conductive channel type field effect transistor and a second constant voltage means.

The logical operation means includes a first power supply terminal and a second power supply terminal, and outputs one or more input signals based on the voltages supplied from the first and second power supply terminals. A logical operation is performed and the result is output as an output signal.

The first conductive channel field effect transistor has a gate terminal, one conduction terminal connected to the first power supply terminal of the logical operation means, and the other conduction terminal connected to the first power supply. The first constant voltage means supplies a constant voltage to the gate terminal of the first conductive channel field effect transistor without depending on the fluctuation of the voltage supplied from the first power supply.

The second conductive channel field effect transistor has a gate terminal, one conduction terminal connected to the second power supply terminal of the logical operation means, and the other conduction terminal connected to the second power supply. The second constant voltage means supplies a constant voltage to the gate terminal of the second conductive channel type field effect transistor without depending on the fluctuation of the voltage supplied from the second power source.

In the above logic circuit, the first constant voltage means includes first resistance means and first capacitance means. The first resistance means is connected between the first power supply and the gate terminal of the first conductive channel field effect transistor. The first capacitance means is connected between the second power supply and the gate terminal of the first conductive channel type field effect transistor.

The second constant voltage means includes second resistance means and second capacitance means. The second resistance means is the second
Is connected between the power source and the gate terminal of the second conductive channel type field effect transistor. The second capacitance means is connected between the first power supply and the gate terminal of the second conductive channel field effect transistor.

[0041]

According to the logic circuit of the first aspect of the present invention, the constant voltage means allows one conduction terminal of the first conductive channel type field effect transistor to be independent of the fluctuation of the voltage supplied from the first power source. Is supplied with a constant voltage. Further, when the constant voltage means includes a bipolar transistor and a constant current source means, a voltage shifted by a voltage between the base and the emitter from the reference voltage applied to the gate terminal of the bipolar transistor is the first conductive voltage. It is supplied to one conduction terminal of the channel field effect transistor.

As a result, the voltage between the gate terminal and the one conduction terminal of the first conductive channel type field effect transistor is independent of the voltage supplied from the first power source.
Be constant. Therefore, the logic threshold value of this logic circuit becomes constant regardless of the voltage supplied from the first power supply. Therefore, the rise and fall times of the output signal are constant regardless of the voltage supplied from the first power supply, and the operation of this logic circuit becomes faster.

A constant voltage different from the voltage supplied from the first power source may be generated at the other conduction terminal of the first conductive channel type field effect transistor.
At this time, since the voltage compensating means shifts to the voltage level supplied from the first power source, the output signal always at the normal logic level is output.

Further, according to the logic circuit of the second invention, the gate terminal of the first conductive channel type field effect transistor can be provided without depending on the fluctuation of the voltage supplied from the first power source by the constant voltage means. A constant voltage is supplied.
When the constant voltage means includes the resistance means and the capacitance means, the capacitance means is charged by the voltage supplied from the first power source via the resistance means. As a result, the voltage supplied from the first power supply is indirectly supplied to the gate terminal of the first conductive channel field effect transistor. Therefore, the first
Even if noise is introduced into the power source, the capacitance means absorbs the noise, and a constant voltage is always supplied to the gate terminal of the first conductive channel field effect transistor.

As a result, a voltage shifted by the threshold voltage of the first conductive channel type field effect transistor from the above constant voltage is supplied to the first power supply terminal of the logical operation means. As a result, noise is not included in the output signal of the logical operation means, and the next-stage circuit to which this output signal is applied is less likely to malfunction.

Further, the second conductive channel type field effect transistor is connected between the second power supply terminal and the second power supply of the logical operation means, and its gate terminal is composed of, for example, resistance means and capacitance means. When a constant voltage is supplied to the gate terminal by the constant voltage means, the noise is absorbed not only when the first power source has noise but also when the second power source has noise.
There is no noise in the output signal.

[0047]

Embodiments of the logic circuit according to the present invention will now be described in detail with reference to the drawings.

[Embodiment 1] FIG. 1 is a circuit diagram showing an input logic circuit according to a first embodiment of the present invention.

Referring to FIG. 1, this input logic circuit 15
Is a P-channel MOS transistor 151 and an N-channel MOS transistor 152, an NPN bipolar transistor 153, a current source 154, and a P-channel MO transistor.
The S transistor 155 and the inverter 156 are provided.

P channel MOS transistor 151 and N channel MOS transistor 152 form a CMOS inverter. These transistors 151 and 1
The gate terminals of 52 are both connected to the input terminal 157 of the input logic circuit 15. The drain terminals of the transistors 151 and 152 are both connected to the output terminal 158 of the input logic circuit 15. further,
The source terminal of the transistor 152 is connected to the ground 102 (second power supply).

The base terminal of the bipolar transistor 153 has a constant reference voltage V _REF independent of the power supply voltage V _CC.
Receive. The collector terminal of the bipolar transistor 153 is connected to the power supply 100 (first power supply), the emitter terminal is connected to the ground 102 via the current source 154, and the source terminal of the transistor 151.

Since a predetermined emitter current flows through the bipolar transistor 153 by the current source 154,
A voltage lower than the reference voltage V _REF by the base-emitter voltage V _BE is supplied to the emitter terminal. Therefore, the bipolar transistor 153 and the current source 1
Reference numeral 54 constitutes a constant voltage means for supplying a constant voltage V _REF -V _BE to the source terminal of the transistor 151 without depending on the fluctuation of the voltage V _CC supplied from the power source 100.

Further, the P-channel MOS transistor 15
5 is connected between the power supply 100 and the output terminal 158,
The gate terminal is output terminal 1 via the inverter 156.
58. Therefore, this transistor 15
5 and the inverter 156 constitute a voltage compensating means for raising the voltage level generated at the output terminal 158 from V _REF -V _BE to V _CC .

FIG. 2 is a circuit diagram showing some specific configurations of the current source 154 shown in FIG.

For example, referring to FIG. 2A, the current source 154 is an NPN bipolar transistor 154a.
And a resistor 154b. This transistor 154
The gate terminal of a is supplied with a constant voltage that does not depend on the power supply voltage V _CC .

Further, referring to FIG. 2B, this current source 1
54 includes an N-channel MOS transistor 154c. A constant voltage independent of the power supply voltage V _CC is supplied to the gate terminal of the transistor 154c.

Further, referring to FIG. 2C, this current source 1
54 includes an N-channel MOS transistor 154d. The power supply voltage V _CC is supplied to the gate terminal of the transistor 154d.

Further, referring to FIG. 2D, this current source 1
54 includes a resistor 154e. According to the current source 154 shown in FIGS. 2A and 2B, a constant emitter current is supplied to the bipolar transistor 153. In addition, the current source 154 shown in FIGS.
According to the above, a predetermined current is supplied to the bipolar transistor 153. As described above, the current source 154 desirably supplies a constant current, but is not particularly limited to a constant current source.

Next, the operation of the input logic circuit 15 will be described. The input logic circuit 15 functions as a TTL interface which converts an externally applied TTL level input signal Vi into a CMOS level and supplies it internally. Therefore, generally, power supply voltage V _CC is set to 5V and ground voltage is set to 0V.

As the input signal Vi, the H level (2.2 to
(3.0 V) is applied to the input terminal 157, the P-channel MOS transistor 151 turns off and the N-channel MOS transistor 152 turns on. This allows
The output terminal 158 becomes the ground level. Therefore,
An H level (0V) is output as the output signal Vo.

At this time, the output signal Vo is output to the inverter 15
Since it is given to the gate terminal of the transistor 155 through 6, the transistor 155 is turned off.

On the other hand, as the input signal Vi, the L level (0 to
0.8 V), the P-channel MOS transistor 151 turns on and the N-channel MOS transistor 152 turns off. As a result, the voltage level of the source terminal of the transistor 151 is supplied to the output terminal 158.

Since a predetermined current (preferably a constant current) flows through the transistor 153 by the current source 154, the emitter terminal of the transistor 153 has a base-emitter voltage higher than the constant reference voltage V _REF applied to the base terminal. A voltage lower by the voltage V _BE is generated. For example, when 4 V is applied as the reference voltage V _REF , the base-emitter voltage V _BE is always 0.8 V, so that 3.2 V is generated at the emitter terminal.

Therefore, the output terminal 158 is supplied with this voltage V _REF -V _BE (for example, 3.2 V). Further, since this voltage V _REF -V _BE is given to the gate terminal of the transistor 155 through the inverter 156, this transistor 155 is turned on. As a result, the voltage of the output terminal 158 is raised to the power supply voltage V _CC . As a result, the H level (5V) is finally output as the output signal Vo.

As described above, since the input logic circuit 15 is configured to supply the source terminal of the transistor 151 with a constant voltage that does not depend on the power supply voltage V _CC , its logic threshold value depends on the power supply voltage V _CC . Instead, it becomes constant. Therefore, since the input logic circuit 15 always operates stably even if the power supply voltage V _CC fluctuates, high speed operation is possible. Therefore, when this input logic circuit 15 is used for the input stage of the address buffer 2 or 4 of the SRAM, the dependency of the access time on the power supply voltage is reduced and high-speed operation becomes possible.

Further, the voltage V _REF lower than the power supply voltage V _CC
Since -V _BE is supplied to the source terminal of the transistor 151, the output terminal 158 first receives the voltage V _REF -V _BE.
Is supplied. However, since the voltage compensating means including transistor 155 and inverter 156 raises the voltage level to the power supply voltage V _CC level, 5 V is supplied as the H level and there is no problem as the CMOS level.

Further, the input logic circuit 15 is provided with a bipolar transistor 153, and a voltage lower than the base-emitter voltage V _BE by a reference voltage V _REF given to the base terminal of the bipolar transistor 153 is applied to the source terminal of the transistor 151. Therefore, the current flowing from the reference voltage generating circuit that generates the reference voltage V _REF to the input logic circuit 15 is up to about 1 / h _FE compared to the case where a constant voltage is directly applied to the source terminal of the transistor 151. Will be reduced. Here, h _FE is the current amplification factor (about 100) of the bipolar transistor 153. Therefore, unlike the case where the constant voltage is directly applied to the source terminal of the transistor 151, the applied constant voltage does not change transiently.

The input logic circuit 15 is not limited to the first input stage of the address buffer in the SRAM, but also the TTL.
If the circuit has an interface, DRAM, R
It can be used for anything such as OM, gate array, and microcomputer.

FIG. 3 is a circuit diagram of the transistor 153 shown in FIG.
Reference voltage V supplied to the base terminal _REFCriteria to generate
It is a circuit diagram which shows an example of a voltage generation circuit.

Referring to FIG. 3, the reference voltage generating circuit includes a bandgap reference circuit 16 and a current mirror circuit 17.

The bandgap reference circuit 16 is
The bipolar transistors Q ₁ to Q ₅ and the resistors R ₁ to R ₄ are provided, and a constant voltage V _CS (1.2 to 1.
3V) is generated.

Here, the currents flowing through the resistors R ₁ to R ₄ are I ₁ to I ₄ , respectively, and the base-emitter voltages of the transistors Q ₁ to Q ₅ are V, respectively.
_BE1 to V _BE5 . Further, since the current amplification factors of the transistors Q ₁ to Q ₅ are sufficiently large, their base currents are ignored.

This bandgap reference circuit 16
The voltage V _CS generated by is the sum of the base-emitter voltage V _BE5 of the transistor Q ₅ and the voltage applied to the resistor R ₄ , and is represented by the following equation.

V _CS = V _BE5 + R ₄ I ₄ (1) On the other hand, the potential difference (V _CC ) between the power supply voltage V _CC and the ground voltage
It includes a voltage across the resistor R _1, the transistor Q ₂ based - the emitter voltage V _BE2, the voltage across the resistor R _2, the transistor Q ₁ base - emitter voltage V _BE1
Since it is the sum of and, it is expressed by the following equation.

V _CC = R ₁ I ₁ + V _BE2 + R ₂ I ₂ + V _BE1 (2) Further, the potential difference (V _CC ) between the power supply voltage V _CC and the ground voltage.
Includes a voltage across the resistor R _1, the base of the transistor Q ₄ - emitter voltage V _BE4, the voltage across the resistor R _4, the base of the transistor Q ₅ - emitter voltage V _BE5
Since it is the sum of and, it is expressed by the following equation.

V _CC = R ₁ I ₁ + V _BE4 + R ₄ I ₄ + V _BE5 (3) From the equations (2) and (3), the voltage applied to the resistor R ₄ is represented by the following equation.

R ₄ I ₄ = V _BE1 + V _BE2 + R ₂ I ₂ −V _BE4 −V _BE5 (4) When the formula (4) is substituted into the formula (1), the constant voltage V _CS is represented by the following formula. .

V _CS = V _BE1 + V _BE2- V _BE4 + R ₂ I ₂ (5) Furthermore, the base-emitter voltage V of the transistor Q _5
BE5, the base of the transistor Q ₃ - emitter voltage V
And _BE3, because the sum of the voltage across the resistor R _3, is expressed by the following equation.

V _BE5 = V _BE3 + R ₃ I ₃ (6) The base currents of the transistors Q ₁ and Q ₃ are the current I ₂
And I ₃ are sufficiently small and can be ignored that the current I
_The following equation holds between ₂ and I ₃ .

I ₂ ≈I ₃ (7) From the equations (6) and (7), the voltage applied to the resistor R ₂ is represented by the following equation.

R ₂ I ₂ ≈R ₂ I ₃ = (V _BE5 −V _BE3 ) R ₂ / R ₃ (8) When the formula (8) is substituted into the formula (5), the constant voltage V _CS is given by the following formula. expressed.

V _CS = V _BE1 + V _BE2 −V _BE4 + (V _BE5 −V _BE3 ) R ₂ / R ₃ (9) Each current I ₁ to I ₄ also fluctuates according to the fluctuation of the power supply voltage V _CC. Since the variation of the base-emitter voltage V _BE due to the currents I ₁ to I ₄ is very small, the equation (9)
Therefore, the voltage V _CS is always constant regardless of the fluctuation of the power supply voltage V _CC .

On the other hand, the current mirror circuit 17 includes P channel MOS transistors P ₁ and P ₂ , an N channel MOS transistor N _1, and a bipolar transistor Q.
₆ and a resistor R ₅ , which amplifies the voltage V _CS supplied from the bandgap reference circuit 16 and generates a constant reference voltage V _REF .

Since the base terminal of the transistor Q ₆ is always supplied with a constant voltage V _CS regardless of the fluctuation of the power supply voltage V _CC, a constant current I ₅ flows through each of the transistors P ₁ and Q ₆ . Also, transistors P ₁ and P ₂
Is a current mirror, the transistor P
_A constant current I ₆ also flows through each of ₂ and N ₁ . Therefore, from the current mirror circuit 17, the power supply voltage V
_A constant reference voltage V _REF (for example, 4V) is always supplied regardless of the fluctuation of _CC .

In this reference voltage generation circuit, the voltage V generated by the bandgap reference circuit 16 is used.
_{Since CS} is relatively small, the current mirror circuit 17
The reference voltage V _REF is obtained by amplification by, but if a sufficiently high voltage can be obtained as the constant voltage V _CS ,
The voltage V _CS may be directly supplied to the base terminal of the bipolar transistor 153 forming the input logic circuit 15.

[Second Embodiment] FIG. 4 is a circuit diagram showing an input logic circuit according to a second embodiment of the present invention.

Referring to FIG. 4, this input logic circuit 18
Is a P-channel MOS transistor 181, an N-channel MOS transistor 182, a PNP bipolar transistor 183, a current source 184, and an N-channel MO transistor.
An S transistor 185 and an inverter 186 are provided. Transistors 181 and 182 form a CMOS inverter. Transistor 183 and current source 18
Reference numeral 4 constitutes constant voltage means for supplying a constant voltage to the source terminal of the transistor 182 without depending on the fluctuation of the voltage supplied from the ground 102 (first power source).
Further, the transistor 185 and the inverter 186.
Constitutes a voltage compensating means for lowering the voltage level generated at the output terminal 188 to the voltage level of the ground 102.

The input logic circuit 18 is constructed by reversing the power supply and the ground in the input logic circuit 15 according to the first embodiment, and a stable output signal Vo is always output regardless of the fluctuation of the ground voltage. It Therefore, the input logic circuit 18 operates at high speed.

[Third Embodiment] FIG. 5 is a circuit diagram showing a logic circuit according to a third embodiment of the present invention.

Referring to FIG. 5, this input logic circuit 20
Is an enhancement type P-channel MOS transistor 201 and an N-channel MOS transistor 202,
Depletion type N-channel MOS transistor 203
A resistor 204 and a capacitor 205. The transistors 201 and 202 form a CMOS inverter that is a logical operation means, logically invert the input signal Vi, and output the result as an output signal Vo.

Further, the transistor 203 is a depletion type having a threshold voltage V _thN of approximately 0 V, its drain terminal is connected to the power source 100 (first power source), and its source terminal is the transistor 20 which constitutes an inverter.
1 source terminal (first power supply terminal). Further, a resistor 204 having a very large value (for example, -10 ¹² Ω) is connected between the gate terminal and the power supply 100, and a capacitance 205 is provided between the gate terminal and the ground 102 (second power supply). Connected. The resistors 204 and 205 form constant voltage means for supplying a constant voltage to the gate terminal of the transistor 203 without depending on the fluctuation of the power supply voltage V _CC .

The gate terminal (second power supply terminal) of the transistor 202 forming the inverter is ground 10.
Connected to 2.

Next, the logic circuit 20 according to the third embodiment.
The operation of will be described. First, in the steady state, since the capacitor 205 is sufficiently charged, the transistor 20
The power supply voltage V _CC is supplied to the gate terminal of No. 3. Since this transistor 203 is a source follower,
Low voltage V _CC -V _thN by the threshold voltage V _thN is produced than the gate voltage V _CC to its source terminal. Since the threshold voltage V _thN is almost 0V, the power source voltage V _CC is almost supplied to the source terminal of the transistor 203.

In this state, the input signal Vi is H
When a level is applied, the transistor 201 is turned off and the transistor 202 is turned on. As a result, the output signal Vo becomes L level.

On the other hand, when the L level is given as the input signal Vi, the transistor 201 is turned on and the transistor 202 is turned off. As a result, the transistor 2
The voltage V _CC generated at the source terminal of 03 is supplied to the drain terminal of the transistor 201 via the source terminal.

At this time, even if the power supply 100 receives spike noise, since the resistor 204 and the capacitor 205 are connected to the gate terminal of the transistor 203,
Noise is absorbed by these. Therefore, noise does not enter the voltage V _CC supplied to the gate terminal of the transistor 203. Since this voltage V _CC is output through the transistors 203 and 201, noise does not enter the output signal Vo. Therefore, the circuit at the next stage to which the output signal Vo of the logic circuit 20 is applied does not malfunction.

The logic circuit 20 is not limited to the inverter circuit in the SRAM, but can be used in all CMOs such as DRAM, ROM, gate array, and microcomputer.
It can be applied to S logic circuits.

[Fourth Embodiment] FIG. 6 is a circuit diagram showing a logic circuit according to a fourth embodiment of the present invention.

Referring to FIG. 6, the logic circuit 22 includes an enhancement type P channel MOS transistor 221.
And an N channel MOS transistor 222, a depletion type N channel MOS transistor 223, a resistor 224, and a capacitor 225. This logic circuit 22
However, the difference from the logic circuit 20 according to the third embodiment is that the threshold voltage V _thN of the depletion type transistor 203 is not 0V but a very small value.

According to this logic circuit 22, the output signal Vo
H level becomes V _CC -V _thN , but other operations are similar to those of the logic circuit 20 according to the third embodiment.

In this way, the power supply side of the inverter is connected.
Transistor threshold voltage V _thNIs 0V
Is desirable, but if the value is very small, there is no particular problem.
Yes.

[Fifth Embodiment] FIG. 7 is a circuit diagram showing a logic circuit according to a fifth embodiment of the present invention.

Referring to FIG. 7, the logic circuit 24 includes an enhancement type P channel MOS transistor 241.
And a P-channel MOS transistor 242, an enhancement-type N-channel MOS transistor 243,
A resistor 244 and a capacitor 245 are provided.

The difference between the logic circuit 24 and the logic circuits 20 and 22 according to the third and fourth embodiments is that
The transistor 243 is an enhancement type and has a very small threshold voltage V _thN .

In the logic circuit 24, the output signal Vo
_Has an H level of V _CC -V _thN , but there is no problem if the threshold voltage V _thN is very small as in the above.

[Sixth Embodiment] FIG. 8 is a circuit diagram showing a logic circuit according to a sixth embodiment of the present invention.

Referring to FIG. 8, the logic circuit 26 includes an enhancement type P channel MOS transistor 261.
And N channel MOS transistor 262, depletion type N channel MOS transistor 263, P
A channel MOS transistor 264 and a capacitor 265 are provided.

This logic circuit 26 differs from the logic circuit 20 according to the third embodiment in that a transistor 264 is connected instead of the resistor 204. Since the ground voltage is applied to the gate terminal of the transistor 264, the transistor 264 is always on. Therefore, capacitor 265 is connected to power supply 100 via the conduction resistance of transistor 264. Generally, the conduction resistance of a transistor is the resistance 204
Since the value is smaller than the value of (10 ¹² ), the capacitor 265 is charged immediately after the power is turned on, and the depletion type transistor 263 is immediately turned on. Other operations are similar to those of the logic circuit 20 according to the third embodiment.

As is apparent from this embodiment, the conduction resistance of the transistor may be used as the resistance connected between the gate terminal of the transistor and the power supply.

[Embodiment 7] FIG. 9 is a circuit diagram showing a logic circuit according to a seventh embodiment of the present invention.

Referring to FIG. 9, the logic circuit 28 includes an enhancement type P channel MOS transistor 281.
And N channel MOS transistor 282, depletion type N channel MOS transistor 283, P
A channel MOS transistor 284 and a capacitor 285 are provided.

This logic circuit 28 is different from the logic circuit 22 according to the fourth embodiment in that a transistor 284 is connected instead of the resistor 224.

As described above, even when the conduction resistance of the transistor 284 is used as a resistor, the transistor 283 connected to the power supply side of the inverter may have a small threshold voltage V _thN .

[Embodiment 8] FIG. 10 is a circuit diagram showing a logic circuit 30 according to an eighth embodiment of the present invention.

Referring to FIG. 10, this logic circuit 30 has
Enhancement type P-channel MOS transistor 30
1 and N channel MOS transistor 302, and enhancement type N channel MOS transistor 303
, P-channel MOS transistor 304, and capacitor 30
5 and 5.

This logic circuit 30 differs from the logic circuit 24 according to the fifth embodiment in that a transistor 304 is connected instead of the resistor 244.

As described above, even when the conduction resistance of the transistor 304 is used as a resistor, an enhancement type transistor _having a small threshold voltage V _thN is used as the transistor 303 connected to the power supply side of the inverter. Good.

[Ninth Embodiment] FIG. 11 is a circuit diagram showing a logic circuit according to a ninth embodiment of the present invention.

Referring to FIG. 11, this logic circuit 32 is
Enhancement type P-channel MOS transistor 32
1 and 322 and enhancement type N channel MO
S transistors 323 and 324, depletion type N channel MOS transistor 325, and resistor 326.
And a capacitor 327.

The transistors 321 to 324 are the first
And a two-input NAND circuit that outputs the logical product of the second input signals Vi ₁ and Vi ₂ as the output signal Vo.

The difference between the logic circuit 32 and the logic circuit 20 according to the third embodiment is that it is replaced by an N instead of an inverter.
The AND circuit is connected.

Therefore, the H level of the output signal Vo is
In the case where the power source 100 contains the noise, it is always to the power supply voltage V _CC level. Other operations are similar to those of the logic circuit 20 according to the third embodiment.

[Embodiment 10] FIG. 12 shows the first embodiment of the present invention.
It is a circuit diagram which shows the logic circuit by 0 Example.

With reference to FIG. 12, this logic circuit 34 is
Enhancement type P-channel MOS transistor 34
1 and 342 and enhancement type N channel MO
S transistors 343 and 344, depletion type N channel MOS transistor 345, and resistor 346.
And a capacitor 347.

In the logic circuit 34, the transistors 341 to 344 have the first and second input signals Vi.
A 2-input NOR circuit that outputs a logical sum of ₁ and Vi ₂ as an output signal Vo is configured.

Therefore, the H level of the output signal Vo is
In the case where the power source 100 contains the noise, it is always to the power supply voltage V _CC level. Other operations are similar to those of the logic circuit 20 according to the third embodiment.

Although the two-input logical operation circuit is used in the ninth and tenth embodiments, a logical operation circuit having three or more inputs may be used.

[Embodiment 11] FIG. 13 shows the first embodiment of the present invention.
It is a circuit diagram which shows the logic circuit by 1 Example.

Referring to FIG. 13, this logic circuit 36 is
Enhancement type P-channel MOS transistor 36
1 and P channel MOS transistor 362, depletion type P channel MOS transistor 363,
A capacitor 364 and a resistor 365 are provided.

Transistors 361 and 362 form an inverter which is a logical operation means. Also, capacity 364
And the resistor 365 constitutes a constant voltage means for supplying a constant voltage to the gate terminal of the transistor 363 without depending on the fluctuation of the voltage supplied from the ground 102 (first power source). Further, the transistor 363 is a depletion type and has a threshold voltage V _thP of approximately 0V.

The difference between the logic circuit 36 and the logic circuit 20 according to the third embodiment is that the transistor 363 and the capacitor 364 are provided not on the power supply side of the inverter but on the ground side.
And the resistor 365 is connected.

Next, the operation of the logic circuit 36 will be described. First, in the steady state, the ground voltage is supplied to the gate terminal of the transistor 363. Since this transistor 363 is a source follower,
The source terminal has a threshold voltage V rather than a gate voltage.
_A voltage higher than _thP is supplied. This transistor 36
Since the threshold voltage V _{thP of} 3 is almost 0V, the source voltage becomes almost 0V.

In this state, the input signal Vi is L
When a level is applied, the transistor 361 is turned on and the transistor 362 is turned off. As a result, the output signal Vo becomes H level.

On the other hand, when the H level is applied as the input signal Vi, the transistor 361 turns off and the transistor 362 turns on. As a result, the transistor 3
0V is supplied to the drain terminal of 62, and the output signal Vo
Becomes L level.

At this time, even if spiked noise enters the ground 102, the noise is absorbed by the capacitor 364 and the resistor 365, so that 0V is always output through the transistor 362. Therefore, the circuit at the next stage to which the output signal Vo is applied does not malfunction.

As is apparent from this embodiment, the transistors, capacitors and resistors may be connected to the ground side of the logic operation means, and in this case, the logic operation means is always accurate even when noise enters the ground. Generate an output signal.

[Embodiment 12] FIG. 14 shows the first embodiment of the present invention.
It is a circuit diagram which shows the logic circuit by 2 Example.

Referring to FIG. 14, this logic circuit 38 is
Enhancement type P-channel MOS transistor 38
1 and 382 and enhancement type N channel MO
S transistors 383 and 384, depletion type P channel MOS transistor 385, and capacitor 386.
And a resistor 387.

The logic circuit 38 is different from the logic circuit 36 according to the eleventh embodiment in that a 2-input NAND circuit is connected instead of the inverter. Also,
This logic circuit 38 is the logic circuit 32 according to the ninth embodiment.
Since the power supply and the ground are reversed, the NAND circuit generates an accurate output signal Vo even when the ground 102 has noise.

[Embodiment 13] FIG. 15 shows the first embodiment of the present invention.
It is a circuit diagram which shows the logic circuit by 3 Example.

Referring to FIG. 15, this logic circuit 40 is
Enhancement type P-channel MOS transistor 40
1 and 402 and enhancement type N channel MO
S transistors 403 and 404, a depletion type P channel MOS transistor 405, and a capacitor 406.
And a resistor 407.

This logic circuit 40 is the eleventh and first
The difference from the logic circuits 36 and 38 according to the second embodiment is that a 2-input NO is used instead of the inverter and the NAND circuit.
This is the point where the R circuit is connected.

Further, this logic circuit 40 is the logic circuit 34 according to the tenth embodiment in which the power supply and the ground are reversed, and the NOR circuit outputs an accurate output signal even when noise is introduced into the ground 102. Generate Vo.

In the eleventh to thirteenth embodiments, the conduction resistance of the transistor may be used instead of the resistances 365, 387 and 407. Further, although the two-input logical operation circuit is used in the twelfth and thirteenth embodiments, a logical operation circuit having three or more inputs may be used.

[Embodiment 14] FIG. 16 shows the first embodiment of the present invention.
It is a circuit diagram which shows the logic circuit by 4th Example.

Referring to FIG. 16, this logic circuit 42 is
Enhancement type P-channel MOS transistor 42
1 and N channel MOS transistor 422, depletion type N channel MOS transistor 423 and P channel MOS transistor 426, and resistor 424.
And 428 and capacitors 425 and 427.

This logic circuit 42 is a combination of the logic circuit 20 according to the third embodiment and the logic circuit 36 according to the eleventh embodiment, and has a power supply 100 and a ground 102.
Even if both of them contain noise, the inverter formed by the transistors 421 and 422 produces an accurate output signal Vo. That is, the H level of the output signal Vo becomes V _CC -V _thN which is lower than the power supply voltage V _CC by the threshold voltage V _{thN of the} transistor 423, and the L level of the output signal Vo is lower than the ground voltage by the transistor 4.
It becomes V _thP higher by the threshold voltage V _{thP of} 26. Since the threshold voltages V _thN and V _thP of the depletion type transistors 423 and 426 are approximately 0 V, the H level of the output signal Vo becomes approximately V _CC and the L level becomes approximately 0 V.

[Embodiment 15] FIG. 17 shows the first embodiment of the present invention.
It is a circuit diagram which shows the logic circuit by 5 Example.

Referring to FIG. 17, this logic circuit 44 is
Enhancement type P-channel MOS transistor 44
1 and 442 and enhancement type N channel MO
S transistors 443 and 444, depletion type N channel MOS transistor 445 and P channel MOS transistor 448, and resistors 446 and 45.
0 and capacitors 447 and 449.

The logic circuit 44 is different from the logic circuit 42 according to the fourteenth embodiment in that instead of the inverter, it is composed of transistors 441 to 444.
The AND circuit is connected. The logic circuit 44 includes the logic circuit 32 according to the ninth embodiment and the first logic circuit 32.
In combination with the logic circuit 38 according to the second embodiment, the NAND circuit produces an accurate output signal Vo even when both the power supply 100 and the ground 102 contain noise.

[Embodiment 16] FIG. 18 shows the first embodiment of the present invention.
It is a circuit diagram which shows the logic circuit by 6 Example.

Referring to FIG. 18, this logic circuit 46 is
Enhancement type P-channel MOS transistor 46
1 and 462 and enhancement type N channel MO
S transistors 463 and 464, depletion type N channel MOS transistor 465 and P channel MOS transistor 468, and resistors 466 and 47.
0 and capacitors 467 and 469.

This logic circuit 46 is the 14th and 1st
The difference from the logic circuits 42 and 44 according to the fifth embodiment is that a NOR circuit including transistors 461 to 464 is connected instead of the inverter and the NAND circuit.

Further, the logic circuit 46 is a combination of the logic circuit 34 according to the tenth embodiment and the logic circuit 40 according to the thirteenth embodiment, and when both the power supply 100 and the ground 102 contain noise. Also in, the NOR circuit produces an accurate output signal Vo.

The resistors 424, 428, 446, 450, 466 in the fourteenth to sixteenth embodiments are used.
Instead of 470, a conduction resistance of a transistor may be used. Further, although the two-input logical operation circuit is used in the fifteenth and sixteenth embodiments, a logical operation circuit having three or more inputs may be used.

[0156]

According to the first aspect of the present invention, a constant voltage is supplied to one conduction terminal of the first conductive channel type field effect transistor. Therefore, when the voltage supplied from the first power supply fluctuates. Also, the logic threshold value of this logic circuit is always constant. Therefore, higher speed operation becomes possible.

Moreover, when the above-mentioned constant voltage is generated at the other conduction terminal of the first conductive channel type field effect transistor, the voltage level thereof is shifted to the voltage level supplied from the first power source. It is possible to output a signal that is always at a normal logic level.

According to the second aspect of the present invention, the constant voltage lower than the reference voltage supplied to the base terminal of the bipolar transistor by the base-emitter voltage is one of the first conductive channel type field effect transistors. Since it is supplied to the conduction terminal, the supplied constant voltage does not fluctuate significantly.

According to the third aspect of the invention, a constant voltage is applied to the gate terminal of the first conductive channel field effect transistor connected between the first power supply terminal of the logical operation means and the first power supply. Is supplied, the logical operation means generates an accurate output signal even when the first power supply contains noise. Therefore, the circuit at the next stage to which this output signal is applied does not malfunction.

According to the fourth aspect of the invention, since the constant voltage means is composed of the resistance means and the capacitance means, the noise contained in the first power supply can be absorbed by a simple structure. .

According to the fifth aspect of the present invention, the first conductive channel field effect transistor and the second conductive channel field effect are provided on both the first power supply side and the second power supply side of the logic operation means. Since each transistor is connected and a constant voltage is supplied to its gate terminal,
Even when both the first power supply and the second power supply contain noise, the logical operation means always generates an accurate output signal.

Further, according to the invention of claim 6,
Since the first and second constant voltage means are composed of the first and second resistance means and the first and second capacitance means, the first and second constant voltage means can be used for both the first and second power supplies with an extremely simple configuration. The contained noise can be absorbed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an input logic circuit according to a first embodiment of the present invention.

2 is a circuit diagram showing some specific configurations of the current source shown in FIG.

FIG. 3 is a circuit diagram showing an example of a reference voltage generation circuit for generating the reference voltage shown in FIG.

FIG. 4 is a circuit diagram showing an input logic circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a logic circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a logic circuit according to a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a logic circuit according to a fifth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a logic circuit according to a sixth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a logic circuit according to a seventh embodiment of the present invention.

FIG. 10 is a circuit diagram showing a logic circuit according to an eighth embodiment of the present invention.

FIG. 11 is a circuit diagram showing a logic circuit according to a ninth embodiment of the present invention.

FIG. 12 is a circuit diagram showing a logic circuit according to a tenth embodiment of the present invention.

FIG. 13 is a circuit diagram showing a logic circuit according to an eleventh embodiment of the present invention.

FIG. 14 is a circuit diagram showing a logic circuit according to a twelfth embodiment of the present invention.

FIG. 15 is a circuit diagram showing a logic circuit according to a thirteenth embodiment of the present invention.

FIG. 16 is a circuit diagram showing a logic circuit according to a fourteenth embodiment of the present invention.

FIG. 17 is a circuit diagram showing a logic circuit according to a fifteenth embodiment of the present invention.

FIG. 18 is a circuit diagram showing a logic circuit according to a sixteenth embodiment of the present invention.

FIG. 19 is a block diagram showing an overall configuration of a general SRAM.

20 is a circuit diagram showing an input logic circuit of an address buffer in the SRAM shown in FIG.

21 is a graph showing an operation of the input logic circuit shown in FIG.

FIG. 22 is a circuit diagram showing a conventional CMOS inverter.

23 is a timing chart showing an operation of the inverter shown in FIG.

[Explanation of symbols]

151,181,201,221,241,261,2
81, 301, 321, 322, 341, 342, 36
1,381,382,401,402,421,44
1,442,461,462 Enhancement type P-channel MOS transistor 152,182,202,222,242,243,2
62, 282, 302, 303, 323, 324, 34
3,344,362,383,384,403,40
4,422,443,444,463,464 Enhancement type N channel MOS transistor 153,183 Bipolar transistor 154,184 Current source 203,223,263,283,325,345,4
23,445,465 Depletion type N channel MO
S-transistors 363, 385, 405, 426, 448, 468 Depletion type P-channel MOS transistors 204, 224, 244, 326, 346, 365, 3
87,407,424,428,446,450,46
6,470 Resistance 205,225,245,265,285,305,3
27,347,364,386,406,425,42
7,447,449,467,469 Capacity

Claims (6)

[Claims] 1. A predetermined logic level is set in response to a logic level of a signal externally received via an input terminal, based on two different voltages supplied from a first power source and a second power source. A logic circuit for giving a signal to the inside through an output terminal, wherein a gate terminal connected to the input terminal, one conduction terminal,
And a first conductive channel field effect transistor having the other conduction terminal connected to the output terminal, a gate terminal connected to the input terminal, one conduction terminal connected to the second power supply, and the output terminal A second conductive channel type field effect transistor having the other conductive terminal connected to the one conductive terminal, and one conductive terminal of the first conductive channel type field effect transistor independent of fluctuations in the voltage supplied from the first power source. Constant voltage means for supplying a constant voltage to, and only when the constant voltage is generated at the other conduction terminal of the first conductive channel field effect transistor,
A voltage compensating means for shifting the voltage level to the voltage level supplied from the first power supply. 2. The constant voltage means is connected to a base terminal for receiving a constant reference voltage, a collector terminal connected to the first power supply, and one conduction terminal of the first conductive channel field effect transistor. A first conductive channel type electric field including a bipolar transistor having an emitter terminal, and current source means for supplying an emitter current to the bipolar transistor, wherein the voltage generated at the emitter terminal of the bipolar transistor is the constant voltage. The logic circuit according to claim 1, wherein the logic circuit is supplied to one conduction terminal of the effect transistor. 3. A logic circuit which receives one or more input signals and generates a predetermined output signal based on two different kinds of voltages supplied from a first power source and a second power source, A first power supply terminal and a second power supply terminal connected to the second power supply, and based on the voltage supplied from the first and second power supply terminals Logical operation means for logically operating an input signal and outputting the result as the output signal; a gate terminal, one conduction terminal connected to the first power supply terminal of the logical operation means, and the first power supply A first conductive channel type field effect transistor having the other conductive terminal, and a constant voltage applied to the gate terminal of the first conductive channel type field effect transistor without depending on the fluctuation of the voltage supplied from the first power source. To A logic circuit having constant voltage supply means. 4. The constant voltage means includes a resistance means connected between the first power source and a gate terminal of the first conductive channel type field effect transistor, the second power source and the first conductive channel. Logic circuit according to claim 3, comprising capacitive means connected between the gate terminals of the field effect transistor. 5. A logic circuit which receives one or more input signals and generates a predetermined output signal based on two different kinds of voltages supplied from a first power source and a second power source, A logical operation is performed on the one or more input signals based on the voltage supplied from the first and second power supply terminals, including a first power supply terminal and a second power supply terminal, and the result is the result. And a gate terminal, one conduction terminal connected to the first power supply terminal of the logic operation means, and the other conduction terminal connected to the first power supply. A conductive channel type field effect transistor, and a first constant voltage means for supplying a constant voltage to the gate terminal of the first conductive channel type field effect transistor without depending on the fluctuation of the voltage supplied from the first power source. When A second conductive channel type field effect transistor having a gate terminal, one conduction terminal connected to the second power supply terminal of the logical operation means, and the other conduction terminal connected to the second power supply; A second constant voltage means for supplying a constant voltage to the gate terminal of the second conductive channel type field effect transistor without depending on the fluctuation of the voltage supplied from the power source. 6. The first constant voltage means includes first resistance means connected between the first power supply and a gate terminal of the first conductive channel field effect transistor, and the second power supply. And a first capacitance means connected between the gate terminals of the first conductive channel type field effect transistors, wherein the second constant voltage means includes the second power source and the second conductive channel type electric field. A second resistance means connected between the gate terminals of the effect transistors, and a second capacitance means connected between the first power supply and the gate terminals of the second conductive channel type field effect transistors. The logic circuit according to claim 5.