JPH07170098A - Mounting structure of electronic parts and mounting method - Google Patents

Mounting structure of electronic parts and mounting method

Info

Publication number
JPH07170098A
JPH07170098A JP4034134A JP3413492A JPH07170098A JP H07170098 A JPH07170098 A JP H07170098A JP 4034134 A JP4034134 A JP 4034134A JP 3413492 A JP3413492 A JP 3413492A JP H07170098 A JPH07170098 A JP H07170098A
Authority
JP
Japan
Prior art keywords
chip
substrate
carrier
electronic component
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4034134A
Other languages
Japanese (ja)
Inventor
Richard L Wheeler
リチャード・エル・ホイーラー
Voddarahalli K Nagesh
ボッダラハリ・ケイ・ナゲシュ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JPH07170098A publication Critical patent/JPH07170098A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/467—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing gases, e.g. air
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/45124—Aluminium (Al) as principal constituent
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    • H01L2224/4805—Shape
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Supply And Installment Of Electrical Components (AREA)

Abstract

PURPOSE: To minimize the packaging area of an electronic component and at the same time, increase the operation speed of the electronic component by connecting a plurality of signal pads, formed along the peripheral edge of an active main surface close to a substrate-mounting end face to a contact pattern that is provided along the substrate-mounting end face. CONSTITUTION: An active layer 40 of IC chips 30, 32, and 34 is vertical with respect to a chip carrier 38. Therefore, a chip density on a carrier 38 drastically increases, thus miniaturizing an electronic assembly easily. Also, the length of a signal path can be minimized by manufacturing chips 30, 32, 34 and 36, by providing a signal pad pattern along the periphery of the active surface 40 of each chip adjacent to a boundary between the chip and the carrier 38. By arranging the signal pad along the periphery of the active surface, the pad can be soldered to the contact region of the carrier 38 at the position of a solder connection 42, thus minimizing the packaging area of the electronic component and at the same time increasing the operating speed of the electronic component.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、一般に電子構成要素に
関し、特に集積回路チップの相互接続に関する。FIELD OF THE INVENTION This invention relates generally to electronic components, and more particularly to interconnecting integrated circuit chips.

【０００２】[0002]

【従来技術および発明が解決しようとする課題】一般的
に、電子構成要素の製造の、および電子構成要素を印刷
回路板に設置する構成の目標は、印刷回路板の表面から
の装置の高さを極力少くすることである。これにより電
子組立品の印刷回路板を密接して横並びの関係に実装す
ることができる。このように、大きい面積の電子構成要
素の表面を印刷回路板の表面に平行に取付けることが標
準になっている。フラットパック部品および表面実装部
品は印刷回路板の最大高さを極力小さくするのに役立
つ。BACKGROUND OF THE INVENTION In general, the goal of the manufacture of electronic components, and the configuration of mounting the electronic components on a printed circuit board, is the height of the device above the surface of the printed circuit board. Is to be as small as possible. This allows the printed circuit boards of the electronic assembly to be mounted in close, side-by-side relationship. Thus, it has become standard to mount the surface of large area electronic components parallel to the surface of the printed circuit board. Flat pack components and surface mount components help minimize the maximum height of the printed circuit board.

【０００３】印刷回路板の高密度を達成するという目的
に伴う一つの障害として回路板間の電気的連絡がある。
一つの板から他の板へ信号を伝えるには比較的長い信号
経路が必要である。このことは回路の低インダクタン
ス、高速動作にとって有害である。One obstacle to achieving the high density of printed circuit boards is electrical communication between the boards.
A relatively long signal path is required to transfer signals from one board to another. This is detrimental to the low inductance and high speed operation of the circuit.

【０００４】その上、電子構成要素の低プロフィル構成
は小形化に逆らうことがある。時々、印刷回路板は間隔
を密に配置する必要がないことがある。事実、多数の電
子組立品は１枚の印刷回路板しか必要としない。このよ
うな用途では、電子構成要素を印刷回路板に平行に取付
けると特定の回路板に取付けることができる構成要素の
数が制限される。Moreover, the low profile construction of electronic components can oppose miniaturization. At times, the printed circuit boards may not need to be closely spaced. In fact, many electronic assemblies require only one printed circuit board. In such applications, mounting electronic components in parallel with a printed circuit board limits the number of components that can be mounted on a particular circuit board.

【０００５】所定量の回路板表面域に構成要素を更に高
密度に設置する装置および方法が知られている。クック
（Ｃｏｏｋ）に与えられた米国特許第４，７３０，２３
８号は、表面実装集積回路パッケージ用両面実装モジュ
ールを教示している。このパッケージはモジュールの反
対面を従来どおりの仕方で接続している。次いでモジュ
ールを、モジュールおよびパッケージが板から垂直に突
出するように印刷回路板にはんだ付けする。マーフィ
（Ｍｕｒｐｈｙ）に与えられた米国特許第３，８９９，
７１９号は、二重インラインパッケージ、およびパツケ
ージを水平の印刷回路板から垂直に取付けることができ
るようにする曲ったリードを備えた端子を教示してい
る。クックおよびマーフィの発明は所定量の印刷回路板
表面域の使用に関しては改善になっているが、パツケー
ジおよび中間印刷回路板の必要とする信号線の数は最適
より少い。クックおよびマーフィが教示する信号線の垂
直の長さでは信号線が長くなる。Devices and methods are known for placing components more densely on a given amount of circuit board surface area. US Pat. No. 4,730,23 issued to Cook.
No. 8 teaches a double sided mounting module for surface mounting integrated circuit packages. This package connects the opposite sides of the module in the conventional manner. The module is then soldered to the printed circuit board so that the module and package project vertically from the board. US Patent No. 3,899, to Murphy,
No. 719 teaches a dual in-line package, and terminals with bent leads that allow the package to be mounted vertically from a horizontal printed circuit board. Although the Cook and Murphy invention is an improvement on the use of a given amount of printed circuit board surface area, the number of signal lines required by the package and intermediate printed circuit board is less than optimal. The vertical length of the signal lines taught by Cook and Murphy lengthens the signal lines.

【０００６】従来の印刷回路板または他の基板に、所要
回路板表面域が減少すと共に回路全体の速さおよび性能
が増大する仕方で、直接取付けることができる電子構成
部品を提供するのが本発明の目的である。It is an object of the present invention to provide electronic components that can be directly attached to conventional printed circuit boards or other substrates in a manner that reduces the required circuit board surface area and increases overall circuit speed and performance. It is the purpose of the invention.

【０００７】[0007]

【課題を解決するための手段】上記の目的は、構成要素
の大面積の活性側を基板取付け縁に隣接する印刷回路板
にはんだ付けして、小面積の基板取付け縁に沿って取付
けるようになっている電子構成要素、望ましくは集積回
路チップ、により満たされる。集積回路チップはパッシ
ベーション材料の縁塗膜を備えることができるが、信号
線の長さを増さなければならなくなるチップパッケージ
内には収めないことが望ましい。SUMMARY OF THE INVENTION The above objective is to solder a large area active side of a component to a printed circuit board adjacent a board mounting edge for mounting along a small area board mounting edge. Being filled with electronic components, preferably integrated circuit chips. The integrated circuit chip may be provided with an edge coat of passivation material, but is preferably not contained within the chip package, which requires increased signal line length.

【０００８】複数の集積回路チップが、チップの対向主
面を平面状表面に垂直にして、印刷回路板または他の基
板の平面場表面に実装される。主面間の寸法は基板取付
け縁と反対の縁との間の寸法より実質的に大きい。主面
の一つは基板取付け縁に隣接するる信号パッドのパター
ンを備えた活性面である。信号パッドは印刷回路板上の
接触パッドのパターンに対応するパターン状に設置され
ている。従来どおりのはんだバンプ手法を用いて、チッ
プの信号パッドを印刷回路板の接触パッド機械的におよ
び電気的に接続する。得られる組立品は高チップ密度に
適応するものである。A plurality of integrated circuit chips are mounted on the planar field surface of a printed circuit board or other substrate with the opposing major surfaces of the chips perpendicular to the planar surface. The dimension between the major surfaces is substantially larger than the dimension between the substrate mounting edge and the opposite edge. One of the major surfaces is an active surface with a pattern of signal pads adjacent the board mounting edge. The signal pads are arranged in a pattern corresponding to the pattern of the contact pads on the printed circuit board. The conventional solder bump technique is used to mechanically and electrically connect the signal pads of the chip to the contact pads of the printed circuit board. The resulting assembly is compatible with high chip densities.

【０００９】本発明の長所は、相互接続の三次元特性を
活用することができるということである。多数のチップ
に対して信号パツドの総接続面積はチップの活性側の全
面積に比較して小さい。たとえば、静的および動的記憶
装置チップ上のこの相互接続面積は１センチメートル未
満である。本発明は、チップの一主面上のすべての接続
を中間パーケッジを使用せずに垂直実装することができ
る範囲に設置することを考えている。パッシベーション
層は各チップを絶縁して印刷回路板に沿う短絡を防止し
ている。冷却空気流を利用して熱エネルギをチップから
遠くへ導くことができる。代りに熱だめまたは液体冷却
を利用することができる。An advantage of the present invention is that it can take advantage of the three-dimensional nature of interconnects. For many chips, the total signal pad connection area is small compared to the total active area of the chip. For example, this interconnect area on static and dynamic storage chips is less than 1 centimeter. The present invention contemplates placing all connections on one major surface of the chip to the extent that they can be vertically mounted without the use of intermediate packaging. The passivation layer insulates each chip and prevents shorts along the printed circuit board. A cooling air stream can be used to direct thermal energy away from the chip. Alternatively, heat sink or liquid cooling can be utilized.

【００１０】本発明の他の長所は、相互接続が短かくな
って動作速度が増大していることである。その上、最終
パッケージを廉価に作ることができる。というのは、パ
ッケージングで、および、おそらく、印刷回路板の大き
さで、材料が節約されるからである。Another advantage of the present invention is the shorter interconnections and increased operating speed. What's more, the final package can be made cheaply. This is because packaging saves material, and perhaps the size of the printed circuit board.

【００１１】[0011]

【実施例】図１および図２を参照すると、集積回路チッ
プ１０、１２、１４をチップキャリア１６に接続する従
来技術の三つの方法が示されている。チップキャリア１
６は、印刷回路板またはマルチチップモジュールまたは
類似のものとすることができる。第１のチップ接続法
は、集積回路チップ１０で行われている。チップ１０の
各信号パッドにはキャリア１６にはんだ付けまたは溶接
された外端を備えたワイヤ１８が設けられている。金の
ワイヤの場合には熱圧縮法、超音波法、または熱音波法
により、またはアルミニウムワイヤの場合には超音波法
によりワイヤ接合を行うことができる。ワイヤをウェッ
ジ・ボール接合されているものとして図示してある。す
なわち、ワイヤのチップ端ではウェッジ接合を利用して
いるが、キャリアレベルではボール接合２０を利用して
いる。しばしば、ウェッジ接合とボール接合は逆に使用
される。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIGS. 1 and 2, three prior art methods for connecting integrated circuit chips 10, 12, 14 to a chip carrier 16 are shown. Chip carrier 1
6 can be a printed circuit board or a multi-chip module or the like. The first chip connection method is performed on the integrated circuit chip 10. Each signal pad of chip 10 is provided with a wire 18 having an outer end soldered or welded to carrier 16. Wire bonding can be performed by the heat compression method, ultrasonic method, or thermosonic method in the case of a gold wire, or by the ultrasonic method in the case of an aluminum wire. The wires are shown as wedge ball bonded. That is, while the wedge end is used at the tip end of the wire, the ball joint 20 is used at the carrier level. Often, wedge and ball joints are used in reverse.

【００１２】集積回路チップ１２ではテープ自動化接合
法を示してある。テープ自動化接合フレームはチップ１
２の信号パッドに接続された銅の引線２２から成る内部
リードを備えている。銅の引線は３５ミリフィルムと同
様の絶縁材料で支持されている。テープ自動化接合フレ
ームは、フィルムに銅を塗布し、その後で銅塗膜に伝統
的な写真平版法を施し、エッチングして引線２２を画定
することにより形成される。引線２２の外部リードは代
表的には、キャリア１６の接点にはんだ付けまたは溶接
される。代りに、テープ自動化接合フレームを「着脱自
在」にすることができる。着脱自在テープ自動化接合は
銅の引線２２とおよびキャリア１６の接点２６と一直線
を成す伝導引線（図示せず）を備えている圧縮キャップ
２４を備えることができる。したがって、圧縮キャップ
に加えられる圧力がフレームの銅の引線とキャリア接点
２６との間を圧縮キャップの伝導引線を経由して電気的
に連絡することになる。着脱自在テープ自動化接合によ
れば不良テープ自動化接合チップ１２を容易に取換える
ことができる。For the integrated circuit chip 12, an automated tape joining method is shown. Tape 1 for automated tape joining frame
It has an internal lead consisting of a copper wire 22 connected to two signal pads. The copper traces are supported by an insulating material similar to 35 mm film. The automated tape joining frame is formed by applying copper to the film, followed by traditional photolithography of the copper coating and etching to define the lines 22. The outer leads of the leads 22 are typically soldered or welded to the contacts of the carrier 16. Alternatively, the automated tape joining frame can be made "detachable". The removable tape automated bond may include a compression cap 24 having a copper trace 22 and a conductive trace (not shown) aligned with the contacts 26 of the carrier 16. Therefore, the pressure applied to the compression cap will establish electrical communication between the copper traces on the frame and the carrier contacts 26 via the conductive traces on the compression cap. The removable tape automated bonding allows the defective tape automated bonding tip 12 to be easily replaced.

【００１３】集積回路チップ１４は、はんだバンプ法に
よりキャリア１６に固定される。この方法は、チップの
信号パッドが下向きにキャリア１６を向いているので、
時々フリップ・チップ実装法と言われることがある。は
んだバンプ２８は各信号パッド上に形成されている。チ
ップを面を下にしてキャリアに設置し、温度を上げては
んだをリフローさせ、信号パッドをキャリアの接点に直
接接合する。The integrated circuit chip 14 is fixed to the carrier 16 by the solder bump method. In this method, since the signal pads of the chip face the carrier 16 downward,
It is sometimes referred to as the flip chip mounting method. The solder bumps 28 are formed on each signal pad. The chip is placed face down on the carrier and the temperature is raised to reflow the solder and bond the signal pads directly to the carrier contacts.

【００１４】ワイヤ接合チップ１０のピッチ「ｄ」は一
般にテープ自動化接合チップ１２のピッチ「ｅ」に等し
い。両者の場合において、チップ１０および１２はかな
り間隔を置いてワイヤ１８およびリード２２をキャリア
１６にはんだ付けできるようにしなければならない。チ
ップ１４のはんだバンプ法によれば、チップの信号パッ
ドが直接キャリアに接続されるので、ピッチ「ｆ」を小
さくすることができる。ただし、チップ１０、１２、お
よび１４の大きな面積の表面は上述のすべての方法にお
いてキャリアに平行である。The pitch "d" of the wire bonding tip 10 is generally equal to the pitch "e" of the automated tape bonding tip 12. In both cases, the chips 10 and 12 must be well spaced so that the wires 18 and leads 22 can be soldered to the carrier 16. According to the solder bump method of the chip 14, since the signal pads of the chip are directly connected to the carrier, the pitch “f” can be reduced. However, the large area surfaces of chips 10, 12, and 14 are parallel to the carrier in all of the above methods.

【００１５】図３および図４は、集積回路チップ３０、
３２、３４、および３６の間の必要なピッチ「ｇ」をか
なり小さくする相互接続法を示している。上述の方法で
は、チップの活性面、すなわち、信号パッドのある側、
はチップキャリアから遠ざかる方にまたはチップキャリ
アに向う方に向いていた。本発明では、ＩＣチップ３０
〜３６の活性面４０はチップキャリア３８に垂直であ
る。したがって、キャリア３８の上のチップ密度は大幅
に増大している。これにより電子組立品の微小化が容易
になる。3 and 4 show an integrated circuit chip 30,
An interconnection scheme is shown which significantly reduces the required pitch "g" between 32, 34 and 36. In the method described above, the active surface of the chip, ie the side with the signal pads
Was oriented away from the chip carrier or towards the chip carrier. In the present invention, the IC chip 30
The active surfaces 40 of ~ 36 are perpendicular to the chip carrier 38. Therefore, the chip density on the carrier 38 has increased significantly. This facilitates miniaturization of electronic assemblies.

【００１６】恐らく更に重要なのは、図３および図４の
三次元相互接続法を回路の速さおよび性能を高めるのに
使用することができることである。ワイヤ接合、テープ
自動化接合、およびフリップ・チップ法では、チップ間
の間隔のため比較的長い信号距離が必要である。このた
めキャパシタンスおよびインダクタンスが増加し、性能
および速さが低下する。図３および図４の高密度法は、
性能および動作速度を高める。信号径路の長さはチップ
３０〜３６を、チップとキャリア３８との境界に隣接す
る各チップの活性面４０の周辺に沿う信号パッドのパタ
ーンを設けるという仕方で、製作することにより極小に
なる。信号パッドを活性面の周辺に沿って設置すること
により、パッドをキャリア３８の接触域にはんだ接続４
２の位置ではんだ付けすることができる。Perhaps more importantly, the three-dimensional interconnection method of FIGS. 3 and 4 can be used to increase circuit speed and performance. Wire bonding, tape automated bonding, and flip-chip methods require relatively long signal distances due to chip-to-chip spacing. This increases capacitance and inductance, which reduces performance and speed. The high density method of FIGS. 3 and 4
Increase performance and operating speed. The length of the signal path is minimized by making the chips 30-36 in a manner that provides a pattern of signal pads along the perimeter of the active surface 40 of each chip adjacent the chip / carrier 38 boundary. By placing the signal pads along the perimeter of the active surface, the pads are soldered to the contact areas of the carrier 38.
It can be soldered in position 2.

【００１７】それ故本発明では信号パッドを各チップ３
０〜３６の活性面の下端に形成する必要がある。典型的
には、パッドを単一行に沿って形成し、でも間隔の障害
は生じない。たとえば、標準のランダムアクセス記憶装
置チップ（ＲＡＭ）では、相互接続の総面積は、活性面
４０の総面積、たとえば、１センチメートル未満と比較
して小さい。Therefore, in the present invention, the signal pad is provided for each chip 3
It is necessary to form it at the lower end of the active surface of 0 to 36. Typically, the pads are formed along a single row, but there is no gap in the spacing. For example, in a standard random access storage chip (RAM), the total interconnect area is small compared to the total active surface 40 area, eg, less than one centimeter.

【００１８】チップ製作工程には信号パッドにはんだバ
ンプを形成することが含まれる。はんだバンプを製作す
る一連の工程は既知である。約２５ミクロンの高さに金
を電気めっきすればチップキャリア３８の接点に形成さ
れたはんだバンプへの有効な電気接続が充分に確保され
る。しかし、はんだバンプを形成する金属の選択やその
方法は本発明にとっては重要ではない。それで電気接続
を行うにははんだリフローを採用することができる。電
気接続は代りに、個々の信号パッドをキャリア３８の接
触域に溶接によりまたは導電性接着剤接合により設ける
ことができる。チップの信号パッドおよびキャリア接点
のパターンに対応するメタリゼーションパターンを備え
ているブロックの使用も考えられている。The chip fabrication process includes forming solder bumps on the signal pads. A series of processes for making solder bumps are known. Electroplating gold to a height of about 25 microns ensures sufficient effective electrical connection to the solder bumps formed on the contacts of chip carrier 38. However, the choice of metal and method of forming the solder bumps is not critical to the invention. So solder reflow can be employed to make the electrical connection. The electrical connections could instead be provided by individual signal pads to the contact areas of the carrier 38 by welding or by a conductive adhesive bond. The use of blocks with metallization patterns corresponding to those of the chip's signal pads and carrier contacts is also contemplated.

【００１９】望ましくは、集積回路チップ３０〜３６に
パッシベーション層を縁被覆する。この層はチップを流
体エポキシにまたはポリイミド材に浸漬することにより
施すことができる。縁塗膜は被処理半導体ウェーハの伝
統的なパッシベーション被覆とは別のものである。縁塗
膜はウェーハを個々のチップに薄切りしてから施され
る。縁塗膜は、酸化の危険を減らし、更に重要なこと
は、チップをキャリアに接触させたときキャリア３８の
信号径路が短絡を生じないようにする絶縁を行うことで
ある。Desirably, the integrated circuit chips 30-36 are edge coated with a passivation layer. This layer can be applied by dipping the chip in a fluid epoxy or in a polyimide material. The edge coating is separate from the traditional passivation coating of processed semiconductor wafers. The edge coating is applied after slicing the wafer into individual chips. The edge coating reduces the risk of oxidation and, more importantly, provides insulation that prevents the signal path of carrier 38 from shorting when the chip is contacted with the carrier.

【００２０】従来技術の方法のように、チップ３０〜３
６はキャリアと接触したままになっているが、接触の面
積は従来技術の方法よりかなり少い。その結果キャリア
３８との接触によりチップから外に伝えられる熱エネル
ギは少い。或る用途ではキャリアを通しての伝導冷却で
充分である。他の用途ではファン４４を使用して気体、
好ましくは空気、の冷却流をチップ３０〜３６の表面に
沿って導くことができる。熱発生の大きいチップの冷却
は、フレオンのような液体冷却剤の流れを代りに使用す
ることができる。As in the prior art method, chips 30-3.
6 remains in contact with the carrier, but the area of contact is much smaller than prior art methods. As a result, less heat energy is transferred from the chip to the outside by contact with the carrier 38. Conductive cooling through the carrier is sufficient for some applications. In other applications, use fan 44 for gas,
A cooling flow, preferably air, can be directed along the surface of chips 30-36. Cooling of the heat-generating chips can instead use a stream of liquid coolant such as freon.

【００２１】今度は図５を参照すると、下向きに垂れ下
るフィンガ４８を有する指のように組み合わせた熱だめ
４６をファンの代りにまたはファンと関連して使用して
チップ３０〜３６の温度を制御することができる。フィ
ンガ４８は一つのチップの活性面と、および隣接チップ
の裏面と接触していることが望ましい。熱だめは液体冷
却剤の通路として内部流路（図示せず）を備えることが
できる。代りに、液体冷却剤を熱だめの外部を横断して
流すことがきる。Referring now to FIG. 5, a finger-like combined heat sink 46 having downwardly depending fingers 48 is used in place of or in conjunction with the fan to control the temperature of chips 30-36. can do. The fingers 48 are preferably in contact with the active surface of one chip and the back surface of an adjacent chip. The heat sink may include internal flow passages (not shown) as passages for the liquid coolant. Alternatively, liquid coolant can be flowed across the exterior of the heat sink.

【００２２】[0022]

【発明の効果】以上の如く本発明によれば、電子部品の
実装面積を極小化できると共に、接結信号線を短くとる
ことができ、電子部品の動作速度を増大できる。As described above, according to the present invention, the mounting area of an electronic component can be minimized, the connecting signal line can be shortened, and the operating speed of the electronic component can be increased.

【図面の簡単な説明】[Brief description of drawings]

【図１】従来技術における集積回路チップを基板に取り
付ける三種類の方法を示した側面図である。FIG. 1 is a side view showing three methods of attaching an integrated circuit chip to a substrate in the related art.

【図２】図１の平面図である。FIG. 2 is a plan view of FIG.

【図３】本発明による集積回路チップの実装状態を示す
側面図である。FIG. 3 is a side view showing a mounting state of an integrated circuit chip according to the present invention.

【図４】図３の平面図である。FIG. 4 is a plan view of FIG.

【図５】図３の実装状態から熱エネルギーを導く別の実
施例である。FIG. 5 is another embodiment for introducing heat energy from the mounted state of FIG.

【符号の説明】[Explanation of symbols]

３０、３２、３４、３６：集積回路チップ ３８：チップキャリア ４０：活性面 ４２：はんだ接続 30, 32, 34, 36: Integrated circuit chip 38: Chip carrier 40: Active surface 42: Solder connection

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】活性主面および該活性主面に直角でかつ該
活性主面よりも面積の小さい基板取付け端面を有する集
積回路チップと、 上記基板取付け端面に近接した上記活性主面の周縁に沿
って形成した複数の信号パッドと、 からなり、基板上の上記基板取付け端面に沿って設けた
接点パターンに上記複数の信号パッドを接続するように
した、 ことを特徴とする電子部品。1. An integrated circuit chip having an active main surface and a substrate mounting end surface that is perpendicular to the active main surface and has an area smaller than that of the active main surface; An electronic component, comprising: a plurality of signal pads formed along the plurality of signal pads; and connecting the plurality of signal pads to a contact pattern provided along the substrate mounting end surface on the substrate. 【請求項２】複数の接点パータンをその表面上に備えた
基板と上記基板表面上に実装される複数の電子部品とか
らなり、 上記各電子部品は、対向する二つの主面および該各対向
する主面よりも面積の小さい対向する二つの端面を有
し、上記主面の一つは、上記一方の端面に近接して信号
パッドのパターンを有する活性面とされ、上記一方の端
面を上記基板表面上に固定し、上記基板表面上の接点パ
ターンと上記信号パッドのパターンを直接接続するよう
にした、 ことを特徴とする電子部品の実装構造。2. A substrate comprising a plurality of contact patterns on its surface and a plurality of electronic components mounted on the substrate surface, wherein each electronic component has two main surfaces facing each other and the respective facing surfaces. Has two smaller end surfaces facing each other, and one of the main surfaces is an active surface having a pattern of signal pads in the vicinity of the one end surface. An electronic component mounting structure, characterized in that the electronic component mounting structure is fixed on a substrate surface, and the contact pattern on the substrate surface is directly connected to the signal pad pattern. 【請求項３】対向する二つの大きい主面と、該両主面の
対応する一端の間に配置された小さい実装面とを備え、
上記両主面の対応する一端の間隔を、上記主面における
該端と直交する方向の寸法よりも小さくしてなる複数の
集積回路チップを組み立てるステップと、 上記複数の集積回路チップ上の上記主面の一端側に複数
の信号パッドを形成するステップと、 複数の接点パターンを有する基板を備えるステップと、 上記基板上の複数の接点パターンと上記集積回路チップ
上の信号パターンとを接続することによって各集積回路
チップを基板上に実装するステップと、 からなることを特徴とする電子部品の実装方法。3. Comprising two large major surfaces facing each other and a small mounting surface disposed between corresponding one ends of the major surfaces,
A step of assembling a plurality of integrated circuit chips in which a distance between corresponding one ends of the two main surfaces is smaller than a dimension of the main surface in a direction orthogonal to the ends; By forming a plurality of signal pads on one end side of the surface, providing a substrate having a plurality of contact patterns, and connecting the plurality of contact patterns on the substrate to the signal pattern on the integrated circuit chip. A method for mounting an electronic component, comprising: mounting each integrated circuit chip on a substrate.
JP4034134A 1991-01-24 1992-01-24 Mounting structure of electronic parts and mounting method Pending JPH07170098A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
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US07/645,913 US5113314A (en) 1991-01-24 1991-01-24 High-speed, high-density chip mounting

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KR920015972A (en) 1992-08-27
US5113314A (en) 1992-05-12

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