JPH0476731A - Pipeline type microprocessor assembler processing system - Google Patents

Abstract

PURPOSE:To form an object program having high execution efficiency by analyzing the address of an assembler instruction for accessing a memory and executing scheduling based upon the analyzed result. CONSTITUTION:This assembler processing system is constituted of an assembler instruction string 1, a reference block detection part 2, a reference block 3, a data depending relation analyzing part 4, data depending relation information 5, a memory access analyzing part 6, a scheduling part 7, an assembler instruction string 8, an object output part 9, and an object module 10. The address of the assembler instruction for accessing the memory is analyzed and the analyzed result is used for scheduling. Consequently, the pipeline type microprocessor assembler processing system improving the execution efficiency of an object module can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a processing method of an assembler for a pipelined microprocessor, and particularly to a scheduling method of assembler instructions.

[Conventional technology]

In a pipelined microprocessor, if the hardware does not have an interlock mechanism, the assembler must perform scheduling so that the pipeline operates normally. Even when an interlock mechanism is provided, scheduling must be performed in order to minimize interlocks and increase execution efficiency of object programs.

The processing method of a conventional assembler of a microprocessor without an interlock mechanism will be explained with reference to FIG. Second
The figure shows a processing block diagram according to a conventional assembler processing method. An assembler instruction string 1 written by a user or output by a compiler is detected by a basic block detection unit 2, and is branched from outside without containing a branch instruction in the middle. It is divided into three basic blocks, each of which is a sequence of assembler instructions that never occurs. The data dependency analysis unit 4 analyzes data dependencies between assembler instructions of this basic block 3,
The result is output as data dependency information 5. The scheduling unit 7 schedules the assembler instruction sequence of the basic block 3 with reference to the data dependency relationship information 5, and outputs the assembler instruction sequence 8. The object output unit 9 reads the scheduled assembler instruction sequence 8 and outputs it as an object module 10.

Next, the processing of the data dependency analysis section 4 will be explained. 1st
The table shows an example of a basic block consisting of five assembler instructions.

Table 1 Here, it takes 2 clocks to execute the 1d instruction, add, st,
It is assumed that it takes one clock to execute the jr instruction. The data dependency analysis unit 4 analyzes whether there is a data dependency between assembler instructions, and outputs a set of assembler instructions that have a data dependency as data dependency relationship information 5. Here, when either of the following holds true for the two assembler instructions, or
A data dependency exists when there is a possibility that it holds true.

(1) The second assembler instruction uses data that the first assembler instruction wrote to a register or memory.

(2) The first assembler instruction writes the second assembler instruction to a register or memory that does not use data.

(3) After the first assembler instruction writes data from a register to memory, the second assembler instruction writes data to the same register or memory. Perform the following analysis on a set of instructions 6 (1) Since the contents stored in register r1 by the assembler instruction ■ are used by the assembler instruction ■, there is no data dependency between the two assembler instructions. be.

(2) Assembler instruction ■ reads data from memory, and assembler instruction ■ writes data to memory. There is no possibility that two instructions access memory at the same address, but in order to know this, the contents of register sp must not have changed between the two instructions, and
We must check that the displacement values of the two instructions are different. However, conventional assemblers that do not have the means to do this cannot deny the possibility that two instructions access memory at the same address, and assume that there is a data dependency between the two instructions.

(3) Assembler instruction ■ and assembler instruction ■ both read data from memory, so there is no data dependency relationship.

(4) Assembler instruction ■ and assembler instruction ■, assembler instruction ■ and one assembler instruction ■, assembler instruction ■ and assembler instruction ■, assembler instruction ■ and assembler instruction ■
Since none of the three conditions hold between
There are no data dependencies.

(5> Since the contents stored in the register r2 by the assembler instruction ■ are used by the assembler instruction ■, there is a data dependency between the two assembler instructions.

(6) Assembler instruction ■ writes data to memory, and assembler instruction ■ reads data from memory. There is no possibility that two instructions access memory at the same address, but to know this, we need to know that the contents of register sp have not changed in the instructions between the two instructions, and the displacement value of the two instructions. It is necessary to investigate that the two are different. However, conventional assemblers that do not have the means to do this cannot deny the possibility that two instructions access memory at the same address, and assume that there is a data dependency between the two instructions.

(7) Since the contents stored in the register r3 by the assembler instruction ■ are used by the assembler instruction ■, there is a data dependency between the two assembler instructions.

The data dependency analysis unit 4 outputs the results of the above analysis as data dependency information 5, as shown in Table 2 below. The data dependency relationship information 5 is a set of numbers of two assembler instructions having a data dependency relationship, arranged with the smallest number on the left.

The Table 2 scheduling unit 7 performs scheduling with reference to the data dependency relationship information 5, and outputs the scheduled assembler instruction sequence 8. In the board block shown in Table 1, instructions cannot be rearranged, so a nop instruction, which is an instruction with no effect, is inserted at a necessary location, and the corresponding assembler instruction sequence 8 becomes as shown in Table 3. Seven clocks are required to execute this assembler instruction sequence.

[Margin below]

Table 3 In this assembler processing method, the order of two assembler instructions that have no possibility of accessing memory at the same address cannot be changed, so the rearrangement of instructions is limited, and the execution of the resulting object module 10 It becomes less efficient.

[Problem to be solved by the invention]

As mentioned above, in the conventional assembler processing method, there is no means to analyze memory access addresses, so the reordering of assembler instructions is limited, and as a result, the execution efficiency of the object module 10 that is finally obtained deteriorates. There is a problem with this.

An object of the present invention is to solve such problems by providing a means for analyzing addresses of assembler instructions that access memory, so that the results of the analysis can be used for scheduling, and the execution efficiency of object modules can be improved. The object of the present invention is to provide an assembler processing method for a pipelined microprocessor that improves the following.

[Means to solve the problem]

The structure of the assembler processing method of the pipelined microprocessor of the present invention is such that the assembler processing method used in the pipelined microprocessor analyzes the possibility that multiple assembler instructions accessing the memory access the same address. access analysis means; data dependency analysis means for outputting data dependency relationship information between the assembler instructions using the analysis result of the memory access analysis means; and rearrangement of the assembler instructions using the data dependency relationship information. and a scheduling means for performing scheduling.

In the present invention, the memory access analysis means can check whether the contents of a register have not been changed by an instruction between two instructions and whether the displacement values of these two instructions are different.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a flow diagram illustrating a processing method according to an embodiment of the present invention. An assembler instruction string 1 written by a user or output by a compiler is divided by a basic block detection unit 2 into basic blocks 3, which are assembler instruction strings that do not include branch instructions in the middle and do not branch from outside. be done.

The data dependency analysis unit 4 analyzes the data dependency between assembler instructions of the basic program 3 and outputs the result as data dependency information 5. At this time, for a set of assembler instructions that access memory, the data dependency analysis unit 4 queries the memory access analysis unit 6 as to whether there is a possibility that two instructions access the same address, and The analysis unit 6 determines whether there is a possibility that two instructions access the same address, and the data dependency relationship analysis unit 4 uses this result to output data dependency information.

The scheduling unit 7 schedules the assembler instruction sequence of the basic block 3 with reference to the data dependency relationship information 5, and outputs the assembler instruction sequence 8. The object output unit 9 reads the scheduled assembler instruction sequence 8 and outputs the object module 10.

Next, the processing of the data dependency analysis section 4 and the memory access analysis section 6 will be explained with reference to the above-mentioned Table 1. In Table 1, it takes 2 clocks to execute the 1d instruction, add, st, j
Assume that it takes one clock to execute the r instruction. The data dependency analysis unit 4 analyzes whether there is a data dependency between assembler instructions, and outputs a set of assembler instructions that have a data dependency as data dependency information 5. The data dependency analysis unit 4 and memory access analysis unit 6 perform the following analysis on each set of assembler instructions.

First, the next set of assembler instructions is analyzed in exactly the same way as in the conventional example.

■ and ■, ■ and ■, ■ and ■, ■ and ■, ■ and ■, ■ and ■, ■
and ■, ■ and ■, and other pairs (■ and ■, ■ and ■), the following analysis is performed.

(1) Both assembler instruction ■ and assembler instruction ■ access memory. In this case, the data dependency analysis unit 4 inquires of the memory access analysis unit 6 whether there is a possibility that two instructions access the same address.

The memory access analysis unit 6 determines that the two instructions access memory at the same address because the contents of register sp are not changed by the instruction between the two instructions and the displacement values of the two instructions are different. I judge that there is no possibility of doing so. Based on this result, the data dependency analysis unit 4 determines that there is no data dependency between the two assembler instructions.

(2) Both assembler instruction ■ and assembler instruction ■ access memory. In this case, the data dependency analysis unit 4 inquires of the memory access analysis unit 6 whether there is a possibility that two instructions access the same address.

The memory access analysis unit 6 determines that the two instructions access memory at the same address because the contents of register sp are not changed by the instruction between the two instructions and the displacement values of the two instructions are different. I judge that there is no possibility of doing so. Based on this result, the data dependency analysis unit 4 determines that there is no data dependency between the two assembler instructions.

The data dependency relationship analysis unit 4 outputs the results of the above analysis as data dependency relationship information 5 as shown in Table 4.

Table 4 Table 5 The scheduling unit 7 performs scheduling with reference to the data dependency relationship information 5, and outputs the scheduled assembler instruction sequence 8.

For the basic block shown in Table 1, assembler instruction ■ is moved before assembler instruction ■, and the corresponding assembler instruction sequence 8 becomes as shown in Table 5. The number of locks required to execute this assembler instruction sequence is five, which is two clocks shorter than the assembler instruction sequence shown in the conventional example.

[Margin below]

[Effects of the Invention] As explained above, the assembler processing method of the present invention can analyze the address of an assembler instruction that accesses memory and perform scheduling using the result, which makes execution easier. This has the effect that an efficient object program can be generated.

[Brief explanation of drawings]

FIG. 1 is a processing flow diagram of an assembler processing method showing an embodiment of the present invention, and FIG. 2 is a processing flow diagram of an example of a conventional assembler processing method. 1... Assembler instruction sequence, 2... Basic block detection section, 3... Basic block, 4... Data dependency analysis section, 5... Data dependency information, 6... Memory access analysis Department, 7... Scheduling Department, 8...
Assembler instruction sequence, 9...Object output section, 1o
...object module.

Claims (1)

[Claims] 1. In an assembler processing method used in a pipelined microprocessor, a memory access analysis means for analyzing the possibility that multiple assembler instructions accessing memory access the same address; a data dependency analysis unit that outputs data dependency relationship information between the assembler instructions using the analysis result of the analysis unit; and a scheduling unit that performs scheduling for rearranging the assembler instructions using the data dependency relationship information. An assembler processing method for a pipelined microprocessor characterized by comprising: 2. The memory access analysis means determines that the register contents are not changed by the instruction between the two instructions, and that the contents of the register are not changed by the instruction between the two instructions.
2. The assembler processing method for a pipelined microprocessor according to claim 1, wherein the assembler processing method for a pipelined microprocessor is used to check whether the displacement values of two instructions are different.