JP5999022B2 - Multilayer substrate and manufacturing method thereof - Google Patents

Multilayer substrate and manufacturing method thereof Download PDF

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JP5999022B2
JP5999022B2 JP2013099586A JP2013099586A JP5999022B2 JP 5999022 B2 JP5999022 B2 JP 5999022B2 JP 2013099586 A JP2013099586 A JP 2013099586A JP 2013099586 A JP2013099586 A JP 2013099586A JP 5999022 B2 JP5999022 B2 JP 5999022B2
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electronic component
resin film
resin films
resin
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JP2014220428A (en
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原田　敏一
敏一 原田
横地　智宏
智宏 横地
長谷川　賢一郎
賢一郎 長谷川
康徳 笠間
康徳 笠間
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Denso Corp
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

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Description

本発明は、複数の樹脂フィルムを積層した積層体を加圧しつつ加熱して形成される多層基板およびその製造方法に関するものである。   The present invention relates to a multilayer substrate formed by heating a laminate in which a plurality of resin films are laminated while applying pressure, and a method for manufacturing the same.

このような多層基板が特許文献１に開示されている。この多層基板は、積層された複数の樹脂フィルムのうち一部の樹脂フィルムが有する貫通孔にチップ部品が挿入されている。チップ部品は電極を有しており、電極の主面、すなわち、電極の下面がその真下に位置するビアと接続されている。ビアは、多層基板内の導体パターンとともに基板内の配線を構成している。また、ビアは、導電ペーストを焼結させることで形成される。   Such a multilayer substrate is disclosed in Patent Document 1. In this multilayer substrate, chip components are inserted into through holes of some of the laminated resin films. The chip component has an electrode, and the main surface of the electrode, that is, the lower surface of the electrode is connected to a via located immediately below. The via constitutes a wiring in the substrate together with the conductor pattern in the multilayer substrate. The via is formed by sintering a conductive paste.

なお、特許文献１に開示された多層基板は、チップ部品の電極の下面とビアとが接続されていたが、従来の多層基板には、チップ部品の電極の上面とビアとが接続されたものや、チップ部品の電極の上面および下面の両面とビアとが接続されたものもある。   In the multilayer substrate disclosed in Patent Document 1, the lower surface of the electrode of the chip component and the via are connected. However, the conventional multilayer substrate has the upper surface of the electrode of the chip component and the via connected to each other. In some cases, vias are connected to both the upper and lower surfaces of the electrode of the chip component.

特開２００８−１４７２５４号公報JP 2008-147254 A

しかし、上記した多層基板は、チップ部品の上面と下面の少なくとも一方の主面のみがビアと接続されており、チップ部品と基板内の配線との接続箇所が少ないので、接続信頼性が低いという問題がある。例えば、ビア用の導電ペーストの充填不足が起きると、チップ部品とビアとの間が接続不良となり、その結果、チップ部品と基板内の配線とが導通不良となる。   However, in the multilayer substrate described above, only the main surface of at least one of the upper surface and the lower surface of the chip component is connected to the via, and the connection reliability between the chip component and the wiring in the substrate is small, so the connection reliability is low. There's a problem. For example, when insufficient filling of the conductive paste for via occurs, connection failure occurs between the chip component and the via, and as a result, conduction failure occurs between the chip component and the wiring in the substrate.

なお、このような問題は、チップ部品の主面に対してビアを接続させる場合に限らず、チップ部品の主面に対してメッキ層や金属箔等の導体パターンを接続させる場合においても同様に生じる。また、このような問題は、貫通孔にチップ部品を挿入した多層基板に限らず、貫通孔に他の電子部品を挿入した多層基板においても同様に生じる。   Such a problem is not limited to the case where vias are connected to the main surface of the chip component, but also when a conductor pattern such as a plating layer or metal foil is connected to the main surface of the chip component. Arise. Such a problem occurs not only in a multilayer substrate in which chip components are inserted into the through holes, but also in a multilayer substrate in which other electronic components are inserted into the through holes.

本発明は上記点に鑑みて、電子部品と基板内の配線との接続信頼性を向上させることを目的とする。   In view of the above points, an object of the present invention is to improve the connection reliability between an electronic component and a wiring in a substrate.

上記目的を達成するため、請求項１、４、５に記載の発明では、
積層された複数の樹脂フィルム（１０）と、
複数の樹脂フィルムのうち一部の樹脂フィルムが有する貫通孔（１１）に挿入され、貫通孔の軸方向端部に位置する主面（２０ａ）と、貫通孔を構成する壁面に対向する側面（２０ｃ）とを有する電子部品（２０）と、
複数の樹脂フィルムのうち貫通孔を有していない樹脂フィルムであって一部の樹脂フィルムに隣接する樹脂フィルムに設けられ、電子部品の主面と接続された導電性の接続部材（４０ｆ）とを備え、
電子部品は、チップ部品であり、
一部の樹脂フィルムの表面上には、貫通孔の隣の位置に、電子部品の側面と接触するとともに、接続部材と導通する導体パターン（３０ｄ、３０ｅ）が設けられていることを特徴としている。 In order to achieve the above object, the inventions according to claims 1 , 4 , and 5
A plurality of laminated resin films (10);
A main surface (20a ) that is inserted into a through-hole (11) of a part of the plurality of resin films and is positioned at an end portion in the axial direction of the through-hole, and a side surface that faces a wall surface that forms the through-hole ( 20c ) an electronic component (20 ) ,
A conductive connecting member (40f ) provided on a resin film adjacent to a part of the resin film and having no through-hole among the plurality of resin films, and connected to the main surface of the electronic component; With
The electronic component is a chip component,
On the surface of the portion of the resin film, to the position next to the through-hole contacts with the side surface of the electronic component, as characterized by the conductor pattern (3 0d, 30e) which conduct the connecting member is provided Yes.

本発明では、電子部品の主面と接続部材とを接続するとともに、電子部品の側面と導体パターンとを接続している。このため、本発明によれば、電子部品の主面のみを基板内の配線と接続する場合と比較して、電子部品と基板内の配線との接続箇所が増加しているので、電子部品と基板内の配線との接続信頼性が向上する。   In the present invention, the main surface of the electronic component and the connection member are connected, and the side surface of the electronic component and the conductor pattern are connected. For this reason, according to the present invention, compared with the case where only the main surface of the electronic component is connected to the wiring in the substrate, the number of connection points between the electronic component and the wiring in the substrate is increased. Connection reliability with wiring in the substrate is improved.

なお、この欄および特許請求の範囲で記載した各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示す一例である。   In addition, the code | symbol in the bracket | parenthesis of each means described in this column and the claim is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.

第１実施形態における多層基板の断面図である。It is sectional drawing of the multilayer substrate in 1st Embodiment. 図１の多層基板を構成する複数の樹脂フィルムが積層される様子を示す斜視図である。It is a perspective view which shows a mode that the some resin film which comprises the multilayer substrate of FIG. 1 is laminated | stacked. 第１実施形態における多層基板の製造工程のうち、樹脂フィルムの準備工程を示す断面図である。It is sectional drawing which shows the preparatory process of the resin film among the manufacturing processes of the multilayer substrate in 1st Embodiment. 図３Ａに続く樹脂フィルムの準備工程を示す断面図である。It is sectional drawing which shows the preparatory process of the resin film following FIG. 3A. 図３Ｂに続く樹脂フィルムの準備工程を示す断面図である。It is sectional drawing which shows the preparatory process of the resin film following FIG. 3B. 第１実施形態における多層基板の製造工程のうち、樹脂フィルムの積層工程を示す断面図である。It is sectional drawing which shows the lamination process of a resin film among the manufacturing processes of the multilayer substrate in 1st Embodiment. 第１実施形態における多層基板の製造工程のうち、チップ部品の挿入工程を示す断面図である。It is sectional drawing which shows the insertion process of a chip component among the manufacturing processes of the multilayer substrate in 1st Embodiment. 図４Ｂに続くチップ部品の挿入工程を示す断面図である。FIG. 4B is a cross-sectional view showing the chip component insertion process following FIG. 4B. 第１実施形態における多層基板の製造工程のうち、積層体の加圧加熱工程を示す断面図である。It is sectional drawing which shows the pressurization heating process of a laminated body among the manufacturing processes of the multilayer substrate in 1st Embodiment. 第２実施形態における多層基板の断面図である。It is sectional drawing of the multilayer substrate in 2nd Embodiment. 第２実施形態における多層基板の製造工程のうち、樹脂フィルムの準備工程を示す断面図である。It is sectional drawing which shows the preparatory process of the resin film among the manufacturing processes of the multilayer substrate in 2nd Embodiment. 図６Ａに続く樹脂フィルムの準備工程を示す断面図である。It is sectional drawing which shows the preparatory process of the resin film following FIG. 6A. 第３実施形態における多層基板の断面図である。It is sectional drawing of the multilayer substrate in 3rd Embodiment. 第３実施形態における多層基板の製造工程のうち、積層体の加圧加熱工程を示す断面図である。It is sectional drawing which shows the pressurization heating process of a laminated body among the manufacturing processes of the multilayer substrate in 3rd Embodiment. 第３実施形態における多層基板の製造工程のうち、ピンの挿入工程を示す断面図である。It is sectional drawing which shows the insertion process of a pin among the manufacturing processes of the multilayer substrate in 3rd Embodiment. 他の実施形態におけるピンを示す外観図である。It is an external view which shows the pin in other embodiment.

以下、本発明の実施形態について図に基づいて説明する。なお、以下の各実施形態相互において、互いに同一もしくは均等である部分には、同一符号を付して説明を行う。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

（第１実施形態）
図１、２に示すように、多層基板１は、電子部品が内蔵された部品内蔵基板であって、複数の樹脂フィルム１０が積層された積層体を加熱プレスして成形されたものである。 (First embodiment)
As shown in FIGS. 1 and 2, the multilayer substrate 1 is a component-embedded substrate in which electronic components are built, and is formed by hot pressing a laminated body in which a plurality of resin films 10 are laminated.

複数の樹脂フィルム１０は、熱可塑性樹脂で構成されており、相互に接着されている。図１、２に示す例では、６枚の樹脂フィルム１０が積層されている。６枚の樹脂フィルム１０のそれぞれを上から順に第１〜第６樹脂フィルム１０ａ〜１０ｆと呼ぶ。第１〜第６樹脂フィルム１０ａ〜１０ｆのうち、第３〜第５樹脂フィルム１０ｃ、１０ｄ、１０ｅは、貫通孔１１を有しており、第１、第２および第６樹脂フィルム１０ａ、１０ｂ、１０ｆは貫通孔１１を有していない。第６樹脂フィルム１０ｆは、貫通孔１１を有する第５樹脂フィルム１１ｅに隣接している。したがって、第３〜第５樹脂フィルム１０ｃ〜１０ｅが、特許請求の範囲に記載の一部の樹脂フィルムに相当し、第６樹脂フィルム１０ｆが特許請求の範囲に記載の貫通孔１１を有していない樹脂フィルムであって一部の樹脂フィルムに隣接する樹脂フィルムに相当する。   The plurality of resin films 10 are made of a thermoplastic resin and are bonded to each other. In the example shown in FIGS. 1 and 2, six resin films 10 are laminated. Each of the six resin films 10 is referred to as first to sixth resin films 10a to 10f in order from the top. Among the first to sixth resin films 10a to 10f, the third to fifth resin films 10c, 10d, and 10e have through holes 11, and the first, second, and sixth resin films 10a, 10b, 10 f does not have the through hole 11. The sixth resin film 10 f is adjacent to the fifth resin film 11 e having the through holes 11. Accordingly, the third to fifth resin films 10c to 10e correspond to a part of the resin films described in the claims, and the sixth resin film 10f has the through holes 11 described in the claims. This corresponds to a resin film adjacent to some resin films.

第３〜第５樹脂フィルム１０ｃ〜１０ｅが有する貫通孔１１に、チップ部品２０が挿入されている。チップ部品２０は、半導体チップ、チップコンデンサ、チップ抵抗等のチップ型の電子部品である。チップ部品２０は、主面としての下面２０ａおよび上面２０ｂと、側面２０ｃとを有している。主面２０ａ、２０ｂは、貫通孔１１の軸方向端部に位置している。側面２０ｃは、貫通孔１１の内部に位置しており、貫通孔１１を構成する壁面に対向している。   The chip component 20 is inserted into the through hole 11 included in the third to fifth resin films 10c to 10e. The chip component 20 is a chip-type electronic component such as a semiconductor chip, a chip capacitor, or a chip resistor. The chip component 20 has a lower surface 20a and an upper surface 20b as main surfaces, and a side surface 20c. The main surfaces 20a and 20b are located at the end portions of the through holes 11 in the axial direction. The side surface 20 c is located inside the through hole 11 and faces the wall surface constituting the through hole 11.

チップ部品２０は、両側の側方端部にそれぞれ第１、第２電極２１、２２が設けられている。第１、第２電極２１、２２は金属材料等の導電性材料で構成されている。第１、第２電極２１、２２の表面は、チップ部品２０の主面２０ａ、２０ｂと側面２０ｃの両方に面しており、チップ部品２０の主面２０ａ、２０ｂと側面２０ｃのどちらからも電気的な接続が可能となっている。   The chip component 20 is provided with first and second electrodes 21 and 22 at lateral end portions on both sides. The first and second electrodes 21 and 22 are made of a conductive material such as a metal material. The surfaces of the first and second electrodes 21 and 22 face both the main surfaces 20a and 20b and the side surface 20c of the chip component 20, and electricity is supplied from both the main surfaces 20a and 20b and the side surface 20c of the chip component 20. Connection is possible.

第１、第２電極２１、２２の下面２１ａ、２２ａは、第６樹脂フィルム１０ｆに設けられた層間接続部材としてのビア４０ｆと接続されている。この接続とは物理的および電気的な接続を意味する。第１、第２電極２１、２２は、ビア４０ｆを介して、第６樹脂フィルム１０ｆの下面に設けられた導体パターン３０ｆと導通している。このビア４０ｆが特許請求の範囲に記載の電子部品の主面と接続された導電性の接続部材に相当する。   The lower surfaces 21a and 22a of the first and second electrodes 21 and 22 are connected to vias 40f as interlayer connection members provided on the sixth resin film 10f. This connection means physical and electrical connection. The first and second electrodes 21 and 22 are electrically connected to the conductor pattern 30f provided on the lower surface of the sixth resin film 10f through the via 40f. The via 40f corresponds to a conductive connecting member connected to the main surface of the electronic component described in the claims.

また、第１〜第５樹脂フィルム１０ａ〜１０ｅの上面には導体パターン３０が設けられている。第１〜第５樹脂フィルム１０ａ〜１０ｅおよび第６樹脂フィルム１０ｆに設けられた各導体パターン３０は、各樹脂フィルム中に設けられたビア４０を介して互いに導通している。したがって、第１〜第６樹脂フィルム１０ａ〜１０ｆに設けられた各導体パターン３０ａ〜３０ｆは、第１、第２電極２１、２２と電気的に接続されており、ビア４０とともに、第１、第２電極２１、２２に接続された配線を構成している。   Moreover, the conductor pattern 30 is provided on the upper surfaces of the first to fifth resin films 10a to 10e. The conductor patterns 30 provided in the first to fifth resin films 10a to 10e and the sixth resin film 10f are electrically connected to each other through vias 40 provided in the resin films. Accordingly, the conductor patterns 30a to 30f provided on the first to sixth resin films 10a to 10f are electrically connected to the first and second electrodes 21 and 22, and together with the via 40, the first and first A wiring connected to the two electrodes 21 and 22 is formed.

そして、第４、第５樹脂フィルム１０ｄ、１０ｅの上面に設けられた導体パターン３０ｄ、３０ｅは、ビア４０の位置から貫通孔１１の隣の位置まで配置されており、これらの導体パターン３０ｄ、３０ｅの側面３１が第１、第２電極２１、２２の側面２１ｃ、２２ｃと接触している。導体パターン３０の側面３１を第１、第２電極２１、２２に接触させることから、導体パターン３０は厚い方が好ましい。   The conductor patterns 30d and 30e provided on the upper surfaces of the fourth and fifth resin films 10d and 10e are arranged from the position of the via 40 to the position adjacent to the through hole 11, and these conductor patterns 30d and 30e. Side surface 31 of the first and second electrodes 21 and 22 are in contact with side surfaces 21c and 22c. Since the side surface 31 of the conductor pattern 30 is brought into contact with the first and second electrodes 21 and 22, the conductor pattern 30 is preferably thicker.

次に、本実施形態の多層基板１の製造方法を説明する。多層基板１は、樹脂フィルム１０の準備工程と、樹脂フィルム１０の積層工程と、チップ部品２０の挿入工程と、積層体の加圧加熱工程とを順に行うことで製造される。   Next, the manufacturing method of the multilayer substrate 1 of this embodiment is demonstrated. The multilayer substrate 1 is manufactured by sequentially performing a resin film 10 preparation step, a resin film 10 lamination step, a chip component 20 insertion step, and a laminate pressure and heating step.

樹脂フィルム１０の準備工程では、貫通孔１１を有する樹脂フィルム１０および貫通孔１１を有していない樹脂フィルム１０を含む複数の樹脂フィルム１０を準備する。貫通孔１１を有する樹脂フィルム１０が図１の第３〜第５樹脂フィルム１０ｃ〜１０ｅであり、貫通孔１１を有していない樹脂フィルム１０が図１の第１、第２、第６樹脂フィルム１０ａ、１０ｂ、１０ｆである。   In the preparation process of the resin film 10, a plurality of resin films 10 including the resin film 10 having the through holes 11 and the resin film 10 not having the through holes 11 are prepared. The resin films 10 having the through holes 11 are the third to fifth resin films 10c to 10e in FIG. 1, and the resin films 10 having no through holes 11 are the first, second, and sixth resin films in FIG. 10a, 10b, and 10f.

ここで、第４、第５樹脂フィルム１０ｄ、１０ｅの準備について具体的に説明する。まず、図３Ａに示すように、樹脂フィルム１０の一方の表面に銅箔等の導体箔を設けた後、フォトリソグラフィおよびエッチングにより導体箔をパターニングして、導体パターン３０を形成する。このとき、形成された導体パターン３０は、貫通孔１１の形成予定領域およびその隣の領域にも存在している。   Here, the preparation of the fourth and fifth resin films 10d and 10e will be specifically described. First, as shown in FIG. 3A, after providing a conductive foil such as a copper foil on one surface of the resin film 10, the conductive foil is patterned by photolithography and etching to form a conductive pattern 30. At this time, the formed conductor pattern 30 is also present in a region where the through-hole 11 is to be formed and a region adjacent thereto.

続いて、図３Ｂに示すように、樹脂フィルム１０に貫通孔１１を形成する。このとき、レーザ加工またはパンチ加工により、貫通孔１１の形成予定領域に存在する導体箔も除去する。これにより、貫通孔１１の隣に導体パターン３０が設けられる。   Subsequently, as shown in FIG. 3B, a through hole 11 is formed in the resin film 10. At this time, the conductor foil existing in the region where the through hole 11 is to be formed is also removed by laser processing or punching. Thereby, the conductor pattern 30 is provided next to the through hole 11.

続いて、図３Ｃに示すように、レーザ加工により、ビアホール１２を形成した後、ビアホール１２内にビア４０を形成するための導電ペースト１３を充填する。以上により、第４、第５樹脂フィルム１０ｄ、１０ｅの準備が完了する。   Subsequently, as shown in FIG. 3C, after the via hole 12 is formed by laser processing, the conductive paste 13 for forming the via 40 in the via hole 12 is filled. Thus, the preparation of the fourth and fifth resin films 10d and 10e is completed.

なお、第３樹脂フィルム１０ｃについては、上記した第４、第５樹脂フィルム１０ｄ、１０ｅの準備工程に対して、形成される導体パターン３０の形状および位置を変更することで準備することができる。第１、第２樹脂フィルム１０ａ、１０ｂについては、上記した第４、第５樹脂フィルム１０ｄ、１０ｅの準備工程に対して、貫通孔１１の形成を省略するとともに、形成される導体パターン３０の形状および位置を変更する等により準備することができる。第６樹脂フィルム１０ｆについては、上記した第４、第５樹脂フィルムの準備工程に対して、貫通孔１１の形成を省略するとともに、形成される導体パターン３０の形状および位置を変更し、さらに、チップ部品２０と電気的に接続されるビア４０ｆを追加する等により準備することができる。なお、第６樹脂フィルム１０ｆについては、第１、第２樹脂フィルム１０ａ、１０ｂの準備と同様に、樹脂フィルムの上面に導体箔が設けられ、下面にビア４０ホールが形成されるが、積層時にその上下面が逆となる。   In addition, about the 3rd resin film 10c, it can prepare by changing the shape and position of the conductor pattern 30 formed with respect to the preparation process of the above-mentioned 4th, 5th resin film 10d, 10e. About the 1st, 2nd resin film 10a, 10b, while omitting formation of the through-hole 11 with respect to the preparation process of the above-mentioned 4th, 5th resin film 10d, 10e, the shape of the conductor pattern 30 formed It can be prepared by changing the position and the like. About the 6th resin film 10f, while omitting formation of penetration hole 11 to the above-mentioned preparation process of the 4th and 5th resin films, changing the shape and position of conductive pattern 30 to be formed, It can be prepared by adding a via 40f electrically connected to the chip component 20 or the like. In addition, about the 6th resin film 10f, like preparation of the 1st, 2nd resin film 10a, 10b, conductor foil is provided in the upper surface of the resin film, and a via 40 hole is formed in the lower surface. The upper and lower surfaces are reversed.

樹脂フィルム１０の積層工程では、図４Ａに示すように、準備した第３〜第６樹脂フィルム１０ｃ〜１０ｆを積層して樹脂フィルム１０の積層体を形成する。これにより、第３〜第５樹脂フィルム１０ｃ〜１０ｅの貫通孔１１が連なって、積層体にチップ部品２０を挿入する凹部が形成される。   In the step of laminating the resin film 10, as shown in FIG. 4A, the prepared third to sixth resin films 10c to 10f are laminated to form a laminate of the resin film 10. Thereby, the through-hole 11 of the 3rd-5th resin film 10c-10e continues, and the recessed part which inserts the chip component 20 in a laminated body is formed.

チップ部品２０の挿入工程では、図４Ｂに示すように、樹脂フィルム１０の積層体の凹部にチップ部品２０を挿入する。その後、図４Ｃに示すように、樹脂フィルム１０の積層体の凹部に蓋をするように、第１、第２樹脂フィルム１０ａ、１０ｂを積層する。これにより、第１〜第６樹脂フィルム１０ａ〜１０ｆの積層体が形成される。   In the step of inserting the chip component 20, as shown in FIG. 4B, the chip component 20 is inserted into the concave portion of the laminate of the resin film 10. Then, as shown to FIG. 4C, 1st, 2nd resin film 10a, 10b is laminated | stacked so that the recessed part of the laminated body of the resin film 10 may be covered. Thereby, the laminated body of the 1st-6th resin film 10a-10f is formed.

続いて、加圧加熱工程では、図４Ｄに示すように、ヒータが埋設された一対の熱プレス板５０によって、第１〜第６樹脂フィルム１０ａ〜１０ｆの積層体を加圧しつつ加熱する。これにより、各樹脂フィルム１０が相互に接着されて一体化するとともに、樹脂が流動して隙間が埋められて、チップ部品２０と樹脂フィルム１０とが一体化する。このように、樹脂フィルム１０とチップ部品２０とを一括で一体化させる。なお、このときの加熱により、導電ペースト１３に含まれる粉末が焼結してビア４０が形成される。以上により、図１に示す多層基板１が製造される。   Then, in a pressurization heating process, as shown to FIG. 4D, it heats, pressing the laminated body of 1st-6th resin film 10a-10f with a pair of hot press board 50 by which the heater was embed | buried. Accordingly, the resin films 10 are bonded and integrated with each other, and the resin flows to fill the gaps, so that the chip component 20 and the resin film 10 are integrated. Thus, the resin film 10 and the chip component 20 are integrated together. In addition, by the heating at this time, the powder contained in the conductive paste 13 is sintered and the via 40 is formed. As described above, the multilayer substrate 1 shown in FIG. 1 is manufactured.

以上の説明の通り、本実施形態では、貫通孔１１を有する第４、第５樹脂フィルム１０ｄ、１０ｅの上面のうち貫通孔１１の隣の位置に、チップ部品２０の第１、第２電極２１、２２の側面２１ｃ、２２ｃと接触する導体パターン３０ｄ、３０ｅが設けられている。この導体パターン３０ｄ、３０ｅは、チップ部品２０の第１、第２電極２１、２２の下面２１ａ、２２ａに接合されたビア４０と導通している。このため、本実施形態の多層基板１は、チップ部品２０の第１、第２電極２１、２２をビア４０のみと電気的に接続した場合と比較して、第１、第２電極２１、２２の基板内の配線との接続箇所が増加しており、チップ部品２０と基板内の配線との接続信頼性が向上している。   As described above, in the present embodiment, the first and second electrodes 21 of the chip component 20 are disposed at positions adjacent to the through holes 11 on the upper surfaces of the fourth and fifth resin films 10 d and 10 e having the through holes 11. , 22 are provided with conductor patterns 30d, 30e that contact the side surfaces 21c, 22c. The conductor patterns 30d and 30e are electrically connected to the via 40 joined to the lower surfaces 21a and 22a of the first and second electrodes 21 and 22 of the chip component 20. For this reason, the multilayer substrate 1 of the present embodiment has the first and second electrodes 21 and 22 as compared with the case where the first and second electrodes 21 and 22 of the chip component 20 are electrically connected to only the via 40. The number of connection points with the wiring in the substrate is increased, and the connection reliability between the chip component 20 and the wiring in the substrate is improved.

（第２実施形態）
図５に示すように、本実施形態では、第４、第５樹脂フィルム１０ｄ、１０ｅに設けた導体パターン３０ｄ、３０ｅが、貫通孔１１の周縁部で貫通孔１１に入り込むように折り曲げられた折り曲げ部３２を有しており、この折り曲げ部３２よりも先端側部分３３の表面がチップ部品２０の側面２０ｃに接触している。 (Second Embodiment)
As shown in FIG. 5, in the present embodiment, the conductor patterns 30 d and 30 e provided on the fourth and fifth resin films 10 d and 10 e are bent so as to enter the through hole 11 at the peripheral edge of the through hole 11. A portion 32 is provided, and the surface of the tip side portion 33 with respect to the bent portion 32 is in contact with the side surface 20 c of the chip component 20.

このような構成は、第１実施形態で説明した第４、第５樹脂フィルム１０ｄ、１０ｅの準備工程において、次のように変更することで実現される。すなわち、図６Ａに示すように、導体パターン３０の端部３４が、貫通孔１１の形成予定領域の内部に位置するように、導体パターン３０を形成する。その後、図６Ｂに示すように、導体パターン３０を残しつつ、貫通孔１１を形成する。これにより、導体パターン３０の端部３４が貫通孔１１の周縁部から貫通孔１１の中心側へ突出した導体パターン３０が形成される。   Such a configuration is realized by making the following changes in the preparation steps of the fourth and fifth resin films 10d and 10e described in the first embodiment. That is, as shown in FIG. 6A, the conductor pattern 30 is formed so that the end 34 of the conductor pattern 30 is located inside the region where the through hole 11 is to be formed. Thereafter, as shown in FIG. 6B, the through hole 11 is formed while leaving the conductor pattern 30. Thereby, the conductor pattern 30 in which the end portion 34 of the conductor pattern 30 protrudes from the peripheral edge portion of the through hole 11 toward the center side of the through hole 11 is formed.

そして、チップ部品２０の挿入工程において、チップ部品２０を貫通孔１１に挿入した際に、チップ部品２０によって導体パターン３０が折り曲げ部３２で折り曲げられ、導体パターン３０がチップ部品２０の側面２０ｃと接触する。   When the chip component 20 is inserted into the through hole 11 in the insertion process of the chip component 20, the conductor pattern 30 is bent at the bent portion 32 by the chip component 20, and the conductor pattern 30 contacts the side surface 20 c of the chip component 20. To do.

本実施形態によれば、導体パターン３０の側面（端面）をチップ部品２０の側面２０ｃに接触させる場合と比較して、チップ部品２０の側面２０ｃと導体パターン３０の接触面積を増大させることができる。   According to the present embodiment, the contact area between the side surface 20c of the chip component 20 and the conductor pattern 30 can be increased as compared with the case where the side surface (end surface) of the conductor pattern 30 is brought into contact with the side surface 20c of the chip component 20. .

（第３実施形態）
図７に示すように、本実施形態の多層基板１００は、第１実施形態の多層基板１に対してチップ部品２０をピン６０に変更したものである。 (Third embodiment)
As shown in FIG. 7, the multilayer substrate 100 of the present embodiment is obtained by changing the chip component 20 to a pin 60 with respect to the multilayer substrate 1 of the first embodiment.

ピン６０は、針状の接続部材であり、多層基板１００の配線と外部とを電気的に接続する電子部品である。ピン６０は、主面６０ａと側面６０ｃとを有している。ピン６０の長手方向端部の先端面が主面６０ａであり、長手方向に沿う面が側面６０ｃである。したがって、ピン６０の主面６０ａは、貫通孔１１の軸方向端部に位置している。ピン６０の側面６０ｃは、貫通孔１１の内部に位置しており、貫通孔１１を構成する壁面に対向している。   The pin 60 is a needle-like connection member, and is an electronic component that electrically connects the wiring of the multilayer substrate 100 and the outside. The pin 60 has a main surface 60a and a side surface 60c. The front end surface of the end portion in the longitudinal direction of the pin 60 is the main surface 60a, and the surface along the longitudinal direction is the side surface 60c. Therefore, the main surface 60 a of the pin 60 is located at the axial end of the through hole 11. The side surface 60 c of the pin 60 is located inside the through hole 11 and faces the wall surface that forms the through hole 11.

図７に示す例では、複数の樹脂フィルム１０として、８枚の樹脂フィルム１０ａ〜１０ｈが積層されている。貫通孔１１を有していない樹脂フィルム１０ｆに主面接続用の導体パターン３０ｆが設けられている。この主面接続用の導体パターン３０ｆに、ピン６０の主面６０ａが接触している。この主面接続用の導体パターン３０ｆは、各樹脂フィルム１０の表面に設けられた導体パターン３０とビア４０を介して導通している。この主面接続用の導体パターン３０ｆが、特許請求の範囲に記載の電子部品の主面に接続された接続部材に相当する。   In the example shown in FIG. 7, as the plurality of resin films 10, eight resin films 10 a to 10 h are laminated. A conductor pattern 30f for main surface connection is provided on a resin film 10f that does not have the through-hole 11. The main surface 60a of the pin 60 is in contact with the main surface connecting conductor pattern 30f. The main surface connecting conductor pattern 30 f is electrically connected to the conductor pattern 30 provided on the surface of each resin film 10 via the via 40. The main surface connecting conductor pattern 30f corresponds to a connecting member connected to the main surface of the electronic component described in the claims.

また、本実施形態においても、第１実施形態と同様に、貫通孔１１を有するフィルム１０の表面のうち貫通孔１１の隣の位置に、導体パターン３０が設けられている。図７に示す例では、第１〜第５樹脂フィルム１０ａ〜１０ｅの上面のうち貫通孔１１の隣の位置に、導体パターン３０ａ〜３０ｅが設けられている。これらの導体パターン３０ａ〜３０ｅの側面３１が、ピン６０の側面６０ｃに接触している。ピン６０の側面６０ｃに接触している導体パターン３０ａ〜３０ｅは、ビア４０を介して、主面接続用の導体パターン３０ｆと導通している。   Also in the present embodiment, similarly to the first embodiment, the conductor pattern 30 is provided at a position adjacent to the through hole 11 on the surface of the film 10 having the through hole 11. In the example shown in FIG. 7, conductor patterns 30 a to 30 e are provided at positions adjacent to the through holes 11 in the upper surfaces of the first to fifth resin films 10 a to 10 e. The side surfaces 31 of these conductor patterns 30 a to 30 e are in contact with the side surface 60 c of the pin 60. The conductor patterns 30a to 30e that are in contact with the side surface 60c of the pin 60 are electrically connected to the conductor pattern 30f for main surface connection via the via 40.

次に、本実施形態の多層基板１００の製造方法を説明する。本実施形態の多層基板１００の製造方法は、積層体の加圧加熱工程の後にピン６０の挿入工程を行う点が第１実施形態と異なっており、その他は第１実施形態と同じである。   Next, a method for manufacturing the multilayer substrate 100 of this embodiment will be described. The manufacturing method of the multilayer substrate 100 of the present embodiment is different from the first embodiment in that the step of inserting the pin 60 is performed after the pressure heating process of the laminated body, and the other is the same as the first embodiment.

すなわち、樹脂フィルムの準備工程で、貫通孔１１を有する樹脂フィルム１０および貫通孔１１を有していない樹脂フィルム１０を含む複数の樹脂フィルム１０を準備する。このとき、貫通孔１１を有する樹脂フィルム１０として、貫通孔１１の隣の位置に導体パターン３０ａ〜３０ｅが設けられたものを準備する。一方、貫通孔１１を有していない樹脂フィルム１０として、主面接続用の導体パターン３０ｆが設けられたものを準備する。   That is, in the resin film preparation step, a plurality of resin films 10 including the resin film 10 having the through holes 11 and the resin film 10 not having the through holes 11 are prepared. At this time, the resin film 10 having the through holes 11 is prepared in which conductor patterns 30 a to 30 e are provided at positions adjacent to the through holes 11. On the other hand, as the resin film 10 that does not have the through hole 11, a resin film provided with a conductor pattern 30f for main surface connection is prepared.

続いて、図８に示すように、樹脂フィルム１０の積層工程を行った後、積層体の加圧加熱工程を行う。これにより、各樹脂フィルム１０が相互に接着されて一体化する。また、このときの加熱により、導電ペーストに含まれる粉末が焼結してビア４０が形成される。   Then, as shown in FIG. 8, after performing the lamination process of the resin film 10, the pressurization heating process of a laminated body is performed. Thereby, each resin film 10 is mutually adhere | attached and integrated. In addition, by the heating at this time, the powder contained in the conductive paste is sintered and the via 40 is formed.

続いて、図９に示すように、ピン６０の挿入工程において、ピン６０を貫通孔１１に挿入する。これにより、ピン６０の主面６０ａを主面接続用の導体パターン３０ｆと接触させるとともに、ピン６０の側面６０ｃを貫通孔１１の隣に設けられた導体パターン３０ａ〜３０ｅの側面３１と接触させる。以上により、図７に示す多層基板１００が製造される。   Subsequently, as shown in FIG. 9, in the step of inserting the pin 60, the pin 60 is inserted into the through hole 11. Thereby, the main surface 60a of the pin 60 is brought into contact with the conductor pattern 30f for main surface connection, and the side surface 60c of the pin 60 is brought into contact with the side surface 31 of the conductor patterns 30a to 30e provided next to the through hole 11. Thus, the multilayer substrate 100 shown in FIG. 7 is manufactured.

本実施形態においても、ピン６０の主面６０ａに加えて、ピン６０の側面６０ｃを導体パターン３０と接触させているので、ピン６０の主面６０ａのみを導体パターン３０と接触させる場合と比較して、ピン６０の接触面積が増加しており、ピン６０と基板内の配線との接続信頼性が向上している。   Also in this embodiment, since the side surface 60c of the pin 60 is in contact with the conductor pattern 30 in addition to the main surface 60a of the pin 60, it is compared with the case where only the main surface 60a of the pin 60 is in contact with the conductor pattern 30. Thus, the contact area of the pin 60 is increased, and the connection reliability between the pin 60 and the wiring in the substrate is improved.

（他の実施形態）
本発明は上記した実施形態に限定されるものではなく、下記のように、特許請求の範囲に記載した範囲内において適宜変更が可能である。 (Other embodiments)
The present invention is not limited to the above-described embodiment, and can be appropriately modified within the scope described in the claims as follows.

（１）第１実施形態では、第４、第５樹脂フィルム１０ｄ、１０ｅの準備の際に、貫通孔１１の形成予定領域およびその隣の領域に存在するように導体パターン３０を形成し、貫通孔１１の形成とともに導体パターン３０の一部を除去した。これに対して、貫通孔１１の形成前に、貫通孔１１の形成予定領域に存在せず、その隣の領域に存在するように導体パターン３０を形成しておいても良い。   (1) In the first embodiment, when the fourth and fifth resin films 10d and 10e are prepared, the conductor pattern 30 is formed so as to exist in the region where the through-hole 11 is to be formed and the region adjacent thereto, A part of the conductor pattern 30 was removed together with the formation of the holes 11. On the other hand, before forming the through hole 11, the conductor pattern 30 may be formed so that it does not exist in the region where the through hole 11 is to be formed but exists in the adjacent region.

（２）第１、第２実施形態では、チップ部品２０の第１、第２電極２１、２２の下面２１ａ、２２ａを、ビア４０と接続させたが、ビア４０の代わりに、メッキ層や金属箔からなる導体パターン３０等の他の接続部材と接続させても良い。   (2) In the first and second embodiments, the lower surfaces 21a and 22a of the first and second electrodes 21 and 22 of the chip component 20 are connected to the via 40. However, instead of the via 40, a plating layer or metal You may connect with other connection members, such as the conductor pattern 30 consisting of foil.

（３）第１、第２実施形態では、チップ部品２０の一方の主面である下面２０ａをビア４０と接続させたが、チップ部品２０の他方の主面である上面２０ｂをビア４０と接続させても良い。   (3) In the first and second embodiments, the lower surface 20 a that is one main surface of the chip component 20 is connected to the via 40, but the upper surface 20 b that is the other main surface of the chip component 20 is connected to the via 40. You may let them.

（４）第１、第２実施形態では、チップ部品２０の第１、第２電極２１、２２の側面２１ｃ、２２ｃと接触する導体パターン３０を、第４、第５樹脂フィルム１０ｄ、１０ｅの一方の表面である上面に設けたが、他方の表面である下面に設けても良い。   (4) In the first and second embodiments, the conductor pattern 30 that contacts the side surfaces 21c and 22c of the first and second electrodes 21 and 22 of the chip component 20 is replaced with one of the fourth and fifth resin films 10d and 10e. However, it may be provided on the lower surface which is the other surface.

（５）第３実施形態では、ピン６０が単独の部品であったが、図１０に示すように、ピン６０が挿入部品６１の足と呼ばれる挿入部を構成していても良い。   (5) In the third embodiment, the pin 60 is a single component. However, as shown in FIG. 10, the pin 60 may constitute an insertion portion called a leg of the insertion component 61.

（６）第３実施形態では、積層体の加圧加熱工程の後にピン６０の挿入工程を行ったが、ピン６０を多層基板に内蔵する場合、第１実施形態と同様に、ピン６０の挿入工程の後に積層体の加圧加熱工程を行うようにしても良い。   (6) In the third embodiment, the pin 60 insertion step is performed after the pressurizing and heating step of the laminated body. However, when the pin 60 is built in the multilayer substrate, the insertion of the pin 60 is performed as in the first embodiment. You may make it perform the pressurization heating process of a laminated body after a process.

（７）第３実施形態では、貫通孔１１を有する樹脂フィルム１０の表面上のうち貫通孔１１の隣の位置に設けられた導体パターン３０の側面３１をピン６０の側面６０ｃと接触させたが、第２実施形態のように、導体パターン３０の折り曲げ部よりも先端側部分の表面をピン６０の側面６０ｃに接触させても良い。   (7) In 3rd Embodiment, although the side surface 31 of the conductor pattern 30 provided in the position adjacent to the through-hole 11 on the surface of the resin film 10 which has the through-hole 11 was made to contact with the side surface 60c of the pin 60. As in the second embodiment, the surface of the tip side portion of the conductor pattern 30 relative to the bent portion may be brought into contact with the side surface 60c of the pin 60.

（８）上記各実施形態では、複数の樹脂フィルム１０が熱可塑性樹脂で構成されていたが、これに限られず、複数の樹脂フィルム１０が全て熱硬化性樹脂で構成されていても良い。また、複数の樹脂フィルム１０として、熱可塑性樹脂で構成されたものと熱硬化性樹脂で構成されたものとを併用しても良い。   (8) In each said embodiment, although the some resin film 10 was comprised with the thermoplastic resin, it is not restricted to this, All the some resin films 10 may be comprised with the thermosetting resin. Moreover, you may use together what was comprised with the thermoplastic resin and what was comprised with the thermosetting resin as the some resin film 10. FIG.

（９）上記各実施形態は、互いに無関係なものではなく、組み合わせが明らかに不可な場合を除き、適宜組み合わせが可能である。また、上記各実施形態において、実施形態を構成する要素は、特に必須であると明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必ずしも必須のものではないことは言うまでもない。   (9) The above-described embodiments are not irrelevant to each other, and can be appropriately combined unless the combination is clearly impossible. In each of the above-described embodiments, it is needless to say that elements constituting the embodiment are not necessarily essential unless explicitly stated as essential and clearly considered essential in principle. Yes.

１ 多層基板
１０ 樹脂フィルム
２０ チップ部品（電子部品）
２０ａ チップ部品の下面（電子部品の主面）
２０ｃ チップ部品の側面（電子部品の側面）
３０ 導体パターン
３０ｄ 電子部品の側面に接続された導体パターン
３０ｅ 電子部品の側面に接続された導体パターン
４０ ビア
４０ｆ 電子部品の主面に接続されたビア（接続部材）
６０ ピン（電子部品）
1 Multilayer substrate 10 Resin film 20 Chip component (electronic component)
20a Lower surface of chip component (main surface of electronic component)
20c Side surface of chip component (side surface of electronic component)
30 Conductor Pattern 30d Conductor Pattern Connected to Side of Electronic Component 30e Conductor Pattern Connected to Side of Electronic Component 40 Via 40f Via Connected to Main Surface of Electronic Component (Connecting Member)
60 pins (electronic parts)

Claims (5)

積層された複数の樹脂フィルム（１０）と、
前記複数の樹脂フィルムのうち一部の樹脂フィルムが有する貫通孔（１１）に挿入され、前記貫通孔の軸方向端部に位置する主面（２０ａ）と、前記貫通孔を構成する壁面に対向する側面（２０ｃ）とを有する電子部品（２０）と、
前記複数の樹脂フィルムのうち前記貫通孔を有していない樹脂フィルムであって前記一部の樹脂フィルムに隣接する樹脂フィルムに設けられ、前記電子部品の主面と接続された導電性の接続部材（４０ｆ）とを備え、
前記電子部品は、チップ部品であり、
前記一部の樹脂フィルムの表面上には、前記貫通孔の隣の位置に、前記電子部品の側面と接触するとともに、前記接続部材と導通する導体パターン（３０ｄ、３０ｅ）が設けられており、
前記導体パターンは、前記複数の樹脂フィルムの積層方向に複数並んでいることを特徴とする多層基板。 A plurality of laminated resin films (10);
The resin film is inserted into a through hole (11) of a part of the plurality of resin films, and faces a main surface (20a ) positioned at an axial end of the through hole and a wall surface forming the through hole. An electronic component (20 ) having a side surface (20c )
A conductive connection member provided on a resin film that does not have the through-hole among the plurality of resin films and is adjacent to the part of the resin films, and is connected to a main surface of the electronic component (40f )
The electronic component is a chip component,
Wherein the surface of the portion of the resin film, to the position next to the through hole contacts with the side surface of the electronic component, the connecting member and the conductive to the conductive pattern (3 0d, 30e) is provided ,
A multilayer substrate , wherein a plurality of the conductor patterns are arranged in a laminating direction of the plurality of resin films . 前記導体パターンは、その側面（３１）が前記電子部品の側面と接触していることを特徴とする請求項１に記載の多層基板。   The multilayer substrate according to claim 1, wherein the side surface (31) of the conductive pattern is in contact with the side surface of the electronic component. 前記導体パターンは、その先端側部分が前記貫通孔に入り込むように、前記貫通孔の周縁部で折り曲げられた折り曲げ部（３２）を有しており、前記折り曲げ部よりも先端側部分（３３）の表面が前記電子部品の側面と接触していることを特徴とする請求項１に記載の多層基板。   The conductor pattern has a bent portion (32) bent at the peripheral edge of the through hole so that the tip side portion enters the through hole, and the tip side portion (33) from the bent portion. The multilayer substrate according to claim 1, wherein the surface of the substrate is in contact with a side surface of the electronic component. 積層された複数の樹脂フィルム（１０）と、
前記複数の樹脂フィルムのうち一部の樹脂フィルムが有する貫通孔（１１）に挿入され、前記貫通孔の軸方向端部に位置する主面（２０ａ）と、前記貫通孔を構成する壁面に対向する側面（２０ｃ）とを有する電子部品（２０）と、
前記複数の樹脂フィルムのうち前記貫通孔を有していない樹脂フィルムであって前記一部の樹脂フィルムに隣接する樹脂フィルムに設けられ、前記電子部品の主面と接続された導電性の接続部材（４０ｆ）とを備え、
前記電子部品は、チップ部品であり、
前記一部の樹脂フィルムの表面上には、前記貫通孔の隣の位置に、前記電子部品の側面と接触するとともに、前記接続部材と導通する導体パターン（３０ｄ、３０ｅ）が設けられており、
前記導体パターンは、その先端側部分が前記貫通孔に入り込むように、前記貫通孔の周縁部で折り曲げられた折り曲げ部（３２）を有しており、前記折り曲げ部よりも先端側部分（３３）の表面が前記電子部品の側面と接触していることを特徴とする多層基板。 A plurality of laminated resin films (10);
The resin film is inserted into a through hole (11) of a part of the plurality of resin films, and faces a main surface (20a ) positioned at an axial end of the through hole and a wall surface forming the through hole. An electronic component (20 ) having a side surface (20c )
A conductive connection member provided on a resin film that does not have the through-hole among the plurality of resin films and is adjacent to the part of the resin films, and is connected to a main surface of the electronic component (40f )
The electronic component is a chip component,
Wherein the surface of the portion of the resin film, to the position next to the through hole contacts with the side surface of the electronic component, the connecting member and the conductive to the conductive pattern (3 0d, 30e) is provided ,
The conductor pattern has a bent portion (32) bent at the peripheral edge of the through hole so that the tip side portion enters the through hole, and the tip side portion (33) from the bent portion. The multilayer substrate is characterized in that the surface thereof is in contact with the side surface of the electronic component . 積層された複数の樹脂フィルム（１０）と、
前記複数の樹脂フィルムのうち一部の樹脂フィルムが有する貫通孔（１１）に挿入され、前記貫通孔の軸方向端部に位置する主面（２０ａ）と、前記貫通孔を構成する壁面に対向する側面（２０ｃ）とを有する電子部品（２０）と、
前記複数の樹脂フィルムのうち前記貫通孔を有していない樹脂フィルムであって前記一部の樹脂フィルムに隣接する樹脂フィルムに設けられ、前記電子部品の主面と接続された導電性の接続部材（４０ｆ）とを備え、
前記電子部品は、チップ部品であり、
前記一部の樹脂フィルムの表面上には、前記貫通孔の隣の位置に、前記電子部品の側面と接触するとともに、前記接続部材と導通する導体パターン（３０ｄ、３０ｅ）が設けられている多層基板の製造方法であって、
貫通孔（１１）を有する樹脂フィルムおよび前記貫通孔を有していない樹脂フィルムを含む複数の樹脂フィルム（１０）を準備する準備工程と、
前記複数の樹脂フィルムを積層する積層工程と、
前記積層工程後に、前記貫通孔に電子部品（２０）を挿入する挿入工程と、
前記挿入工程後に、積層した前記複数の樹脂フィルムを加圧しつつ加熱することにより、前記複数の樹脂フィルムを一体化させるとともに、前記複数の樹脂フィルムと前記電子部品とを一体化させる加圧加熱工程とを備え、
前記準備工程において、前記貫通孔を有する樹脂フィルムとして、前記貫通孔の隣の位置に導体パターン（３０ｄ、３０ｅ）が設けられたものを準備するとともに、前記貫通孔を有していない樹脂フィルムとして、前記電子部品の主面（２０ａ）と接続するための前記接続部材（４０ｆ）が設けられたものを準備し、
前記挿入工程において、前記電子部品を前記貫通孔に挿入することにより、前記電子部品の主面を前記接続部材と接触させるとともに、前記電子部品の側面（２０ｃ）を前記導体パターンと接触させることを特徴とする多層基板の製造方法。 A plurality of laminated resin films (10);
The resin film is inserted into a through hole (11) of a part of the plurality of resin films, and faces a main surface (20a) positioned at an axial end of the through hole and a wall surface forming the through hole. An electronic component (20) having a side surface (20c)
A conductive connection member provided on a resin film that does not have the through-hole among the plurality of resin films and is adjacent to the part of the resin films, and is connected to a main surface of the electronic component (40f)
The electronic component is a chip component,
A multilayer in which conductor patterns (30d, 30e) that are in contact with the side surfaces of the electronic component and are electrically connected to the connection member are provided on the surface of the part of the resin film at positions adjacent to the through holes. A method for manufacturing a substrate, comprising:
A preparation step of preparing a plurality of resin films (10) including a resin film having a through-hole (11) and a resin film not having the through-hole;
A laminating step of laminating the plurality of resin films;
An insertion step of inserting an electronic component (20 ) into the through hole after the laminating step;
After the inserting step, by pressing and heating the plurality of laminated resin films, the plurality of resin films are integrated, and the pressure heating step of integrating the plurality of resin films and the electronic component And
In the preparation step, wherein a resin film having a through hole, the through hole of the adjacent position to the conductor pattern (3 0d, 30e) with preparing what is provided, the resin film does not have the through hole As prepared the thing provided with the connection member (40f ) for connecting to the main surface (20a ) of the electronic component,
In the inserting step, by inserting the electronic component into the through hole, the main surface of the electronic component is brought into contact with the connecting member, and the side surface (20c ) of the electronic component is brought into contact with the conductor pattern. A method for manufacturing a multilayer substrate.
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