JP5175517B2 - Processor - Google Patents

Description

  The present invention relates to a processor, and more particularly to a processor having a reconfigurable integrated circuit.

A recent processor, for example, a video signal using a digital signal, or a processor mounted on an audio device needs to support a plurality of processes.
Looking at the case of compressing video, MPEG (Moving Picture Experts Group) 2, MPEG4, H.264, etc. are used as compression methods. 263, H.M. Many standards such as H.264 have been put into practical use.

Therefore, in consideration of user convenience and the like, recent video and audio equipment is one device, and it is required to realize a plurality of functions such as correspondence to the plurality of standards.
In order to respond to this requirement, whether multiple processes are implemented by installing multiple hardware that performs one process, or whether multiple processes are executed by software by installing one hardware. A method is conceivable.

The former method has an advantage that high performance can be realized, but has a disadvantage that the circuit scale becomes large when a large number of functions are to be realized. Further, when adding a new function, it is necessary to add hardware.
On the other hand, the latter method has an advantage that a plurality of functions can be flexibly realized and added by adding or changing software, but has a drawback that it is difficult to improve performance.

Therefore, reconfigurable to realize flexible and high-performance processing for specific processing by incorporating a circuit suitable for specific processing into a part of a homogeneous circuit configuration and dynamically changing the hardware configuration. Hardware has been proposed (see Patent Document 1).
International Publication No. 2002/095946 Pamphlet

However, such reconfigurable hardware requires a wiring part and a switch in addition to the part that implements the circuit function, and the circuit scale must be increased. Need time.
Accordingly, an object of the present invention is to provide a flexible and high-performance processor while suppressing the circuit scale.

  In order to solve the above-mentioned problem, a processor that executes a plurality of threads cyclically for each time allotted to the thread, the reconfigurable integrated circuit, and based on the circuit configuration information, Using reconfiguration means for reconfiguring a part, configuration information storage means for storing circuit configuration information corresponding to each of a plurality of threads, and an integrated circuit reconfigured sequentially based on circuit configuration information corresponding to a thread, Control means for executing the thread, and selection means for selecting a thread to be executed next while the control means is executing a thread.

Since the processor according to the present invention has the above-described configuration, the circuit can be reconfigured for each thread, so that the processor can be executed using a circuit suitable for the thread.
Further, the control means is further selected by the selection means by the reconfiguration means for a part other than the part of the integrated circuit used by the executing thread while executing the thread. Reconfiguration based on the circuit configuration information corresponding to the thread may be performed.

This makes it possible to perform reconfiguration for the next thread during execution of a thread, thereby eliminating the time required for reconfiguration and realizing a flexible and high-performance processor.
The processor may further include an arithmetic unit, and the control means may execute the thread using the arithmetic unit and the reconfigured integrated circuit.

  As a result, a thread can be executed using a normal arithmetic unit and a reconfigured integrated circuit. Depending on the processing, a normal arithmetic unit can be used, a reconfigured arithmetic unit can be used, or Since both can be used, flexible and high-performance processing can be performed while suppressing the circuit scale. For example, the reconfigured integrated circuit is used as a computing unit for specific processing.

In other words, since the integrated circuit is not reconfigured for all processes, the scale of reconfigurable circuits can be reduced, the scale of the entire processor can be reduced, and the circuits necessary for processing can be reconfigured. Since it can be configured, flexible and high-performance processing is possible.
A processor for executing a program comprising a plurality of instructions, a reconfigurable integrated circuit; reconfiguration means for reconfiguring a portion of the integrated circuit based on circuit configuration information; and a plurality of instructions Configuration information storage means for storing corresponding circuit configuration information, selection means for selecting two or more instructions capable of simultaneously reconfiguring the integrated circuit based on the circuit configuration information, and two or more selected by the selection means And executing means for executing the two or more instructions in parallel using an integrated circuit reconfigured based on circuit configuration information corresponding to the instructions.

  Since the processor according to the present invention has the above-described configuration, the integrated circuit can be reconfigured for each instruction, and the reconfiguration for a plurality of instructions can be performed simultaneously according to the scale of the circuit to be reconfigured. It becomes possible to perform flexible and high-performance processing while suppressing the above. In order to perform reconfiguration at the same time, not only the order of instructions is taken into account, but also the reconfiguration can be achieved by combining the circuit scale of an integrated circuit required for one instruction with the circuit scale of an integrated circuit required for another instruction. It is necessary not to exceed the circuit scale of possible logic circuits.

<Embodiment 1>
<Overview>
The processor according to the present invention includes reconfigurable hardware in addition to the arithmetic unit provided in a normal processor, and realizes high-performance processing while suppressing the circuit scale by sharing the processing. It is.

  That is, even if it is a plurality of processes, not all of the processes are different, but paying attention to common processes and instructions, frequently used processes and instructions, and common ones are ordinary arithmetic devices The processing specific to each processing is performed by an arithmetic unit configured by reconfigurable hardware, thereby maintaining high performance while suppressing the circuit scale of the entire processor.

The processor of the present embodiment is a multi-thread processor, and as a method for realizing multi-thread, a round robin method in which each task is executed in order for a certain time is assumed.
For each thread, a unique circuit is more suitable, or processing that requires a unique circuit is executed using a circuit reconfigured with reconfigurable hardware.

In other words, the processor does not need to have a circuit unique to each thread, and thus the overall circuit scale can be suppressed.
However, since reconfiguration takes time, it is important to reduce the time.
The multithread processor according to the embodiment of the present invention will be described below.
<Configuration>
Hereinafter, the configuration of the processor 1000 according to the present invention will be described with reference to FIG.

FIG. 1 is a diagram illustrating a configuration example of the processor 1000.
The processor 1000 includes a multi-thread processor 1100, a reconfigurable computing unit 1200, a configuration information storage unit 1300, and a reconfiguration control unit 1400.
The multi-thread processor 1100 is a normal processor, and is a so-called multi-thread processor that can execute a plurality of different processes in a time-sharing manner.

The multi-thread processor 1100 includes a fixed function computing unit 1120 that is a normal computing unit and a thread scheduling unit 1110. The thread scheduling unit 1110 has a thread scheduling function such as determining a thread to be executed next.
The thread schedule unit 1110 determines a thread to be executed next and prepares for saving and restoring of registers, and also performs processing unique to the present invention.

Specifically, during thread execution, a thread to be executed next is selected, and the thread is notified to the reconfiguration control unit 1400.
The multi-thread processor 1100 executes processing while exchanging arithmetic data with both the internal fixed function arithmetic unit 1120 and the external reconfigurable arithmetic unit 1200 as necessary.

  Next, the reconfigurable computing unit 1200 includes a logic block that can realize a combinational circuit and a sequential circuit, and a wiring portion between the logic blocks. The logic block is a circuit unit including a lookup table and a flip-flop, and a desired logic circuit is realized by changing a setting value of the lookup table. In addition, a transistor switch or the like is arranged in the wiring portion, and the wiring path can be freely set.

In the present embodiment, all the logic blocks have the same configuration, and the functions can be individually changed. By connecting them with a group of wires that can be rearranged, circuits having various functions are realized.
Further, it is assumed that the reconfigurable computing unit 1200 is divided into 10 areas having the same configuration. These areas can be reconfigured independently, and a reconfigurable wiring is drawn between the areas, so that one circuit can be realized in a plurality of areas.

The configuration information storage unit 1300 has a function of storing configuration information for reconfiguring the reconfigurable computing unit 1200 into a desired circuit. It is assumed that there are as many pieces of configuration information as the number of desired circuits.
This configuration information includes the set value of the lookup table of the logic block and the information of the control signal to each transistor switch for setting the wiring path.
In addition to the configuration information, the configuration information storage unit 1300 has a function of storing a thread information table 1410 described later. This table associates a thread with configuration information used in the thread.

  Whether the reconfiguration control unit 1400 receives a notification of the next thread from the thread scheduling unit 1110 during thread execution and can be executed only by the normal fixed function computing unit 1120 or does the reconfigurable computing unit 1200 be required? When the reconfigurable computing unit 1200 is reconfigured, the reconfigurable computing unit 1200 and the configuration information storage unit 1300 are instructed.

The reconfigurable computing unit 1200 is notified of reconfiguration and the area to be reconfigured, the configuration information is specified in the configuration information storage unit 1300, and the configuration information is reconfigurable computing unit 1200. Instruct to supply.
Further, when reconfiguration is not possible, it has a function of returning the fact to the thread schedule unit 1110. The case where reconfiguration is not possible is a case where the reconfigurable computing unit 1200 has no area that can be reconfigured.

<Operation>
Next, the operation of the processor according to the present invention will be described with reference to FIGS.
An example in which threads are executed in the order of execution will be described with reference to FIG. 2, and an example in which the execution order of threads will be changed will be described with reference to FIG.
Finally, the thread control process will be described with reference to the flowchart of FIG.

<When threads are executed in the order of execution>
FIG. 2A is a diagram illustrating a configuration example and content example of the thread information table 1410, and FIG. 2B is a time chart illustrating a thread execution example.
The time chart when the thread of the thread information table 1410 shown in FIG. 2A is executed is the time chart shown in FIG.

First, the thread information table 1410 shown in FIG.
The thread information table 1410 is stored in the configuration information storage unit 1300.
The thread information table 1410 includes a thread name 1411, configuration information 1412, and a use area number 1413.

The thread name 1411 is a thread identifier. In the following description, it is assumed that four threads represented by “TH0” to “TH3” are executed in order.
The configuration information 1412 indicates configuration information for reconfiguration when the thread represented by the thread name 1411 uses the reconfigurable computing unit 1200.
The use area number 1413 represents the number of areas required when the reconfigurable computing unit 1200 is used.

  For example, the thread having the thread name 1411 “TH0” uses the reconfigurable computing unit 1200 reconfigured with the configuration of the configuration information 1412 “configuration A” and reconfigurable computing unit 1200 with the configuration information 1412 “configuration A”. In order to reconfigure, the number of used areas of 1413 “6” areas is required. Also, the configuration information 1412 “-” corresponding to the thread name 1411 “TH1” indicates that the reconfigurable computing unit 1200 is not used, and naturally the number of used areas is 1413 “0”.

Next, an example of thread execution will be described with reference to FIG.
Here, the time chart 10 in which the thread uses the fixed function computing unit 1120, the time chart 20 representing the configuration information when the thread uses the reconfigurable computing unit 1200, and the thread A time chart 30 representing configuration information reconfiguring the reconfigurable computing unit 1200 during execution is shown. Further, the configuration information is shown above the time arrow, and the number of areas required by the configuration information is shown below. FIG. 2B shows a case where all threads use the fixed function computing unit 1120, but it is of course possible that there is a period of non-use.

First, the threads are executed in the order of the thread names “TH0”, “TH1”, “TH2”, and “TH3”. While each thread is executing, the reconfigurable computing unit 1200 used by the next thread is reconfigured. It shall be configured.
By preparing in advance in this way, it is not necessary to take the time required for reconfiguration, and substantially only the execution time of the thread.

For example, the thread 100 with the thread name “TH1” uses only the fixed function computing unit 1120 to execute the thread.
During this time, the reconfigurable computing unit 1200 is reconfigured with the configuration information 1412 “configuration C” used by the thread 110 with the thread name 1411 “TH2” to be executed next.
In this case, since the reconfigurable computing unit 1200 has 10 areas in total, the number of areas of the reconfigurable computing unit 1200 used is “3/10” required for “configuration C”. It becomes area 101.

Similarly, the thread 110 with the thread name “TH2” executes the thread using the fixed function computing unit 1120 and the “configuration C” of the reconfigurable computing unit.
During this time, the reconfigurable computing unit 1200 is reconfigured with the configuration information 1412 “configuration D” used by the thread with the thread name 1411 “TH3” to be executed next.
In this case, the number of areas of the reconfigurable computing unit 1200 used is the “3/10” area used by “Configuration C” and the “4/10” area required by “Configuration D”. The “7/10” area 111 is obtained.

In this way, necessary reconfiguration is performed in advance before executing the thread in order.
<To change the thread execution order>
Next, an example in which reconfiguration for the next thread can be performed during thread execution by changing the execution order of the threads will be described with reference to FIG.
FIG. 3A is a diagram illustrating a configuration example and content example of the thread information table 1420, and FIGS. 3B and 3C are time charts illustrating thread execution examples.

The time chart when the thread of the thread information table 1420 shown in FIG. 3A is executed is the time chart shown in FIGS. 3B and 3C.
First, the thread information table 1420 in FIG.
Since the thread information table 1420 in FIG. 3A is almost the same as the thread information table 1410 in FIG. 2A, only the differences will be described.

The difference is that the thread 1421 having the thread name 1411 “TH1” uses the reconfigurable computing unit 1200. The configuration information 1412 “configuration B” and the number of used areas 1413 “5”.
Next, a time chart showing an example of thread execution will be described with reference to FIG. The meaning of the time chart is the same as in FIG.

The thread 200 with the thread name “TH0” is executing a thread using the “function A” of the fixed function computing unit and the reconfigurable computing unit.
During this time, the reconfigurable computing unit 1200 is to be reconfigured with the configuration information 1412 “configuration B” used by the thread with the thread name 1411 “TH1” to be executed next.
In this case, the number of areas of the reconfigurable computing unit 1200 used is the “6/10” area used by “Configuration A” and the “5/10” area required by “Configuration B”. “11/10” area 201, and “configuration B” cannot be reconfigured while the thread with the thread name “TH0” is being executed.

Therefore, as shown in FIG. 3C, the thread 220 with the thread name “TH2” is executed before the thread 230 with the thread name “TH1”. That is, the threads are executed by changing the execution order.
Then, during execution of the thread with the thread name “TH0”, what is reconfigured is the “configuration C” used by the thread 220 with the thread name “TH2”, and “6/10” used by the “configuration A”. The “9/10” area 211 is obtained by adding the “3/10” area required by the “configuration C” area and the “configuration C”, and can be reconfigured in advance.

Similarly, while the thread 220 with the thread name “TH2” is executing a thread using the “function C” of the fixed function computing unit 1120 and the reconfigurable computing unit 1200, the thread 220 is scheduled to be executed next. The reconfigurable computing unit 1200 is reconfigured with the configuration information 1412 “configuration B” used by the thread with the thread name 1411 “TH1”.
In this case, the number of areas of the reconfigurable computing unit 1200 used is the “3/10” area used by “Configuration C” and the “5/10” area required by “Configuration B”. It becomes an “8/10” area 222.

Usually, in the round robin method, the length of a time slice allocated to a thread is considered according to the processing to be executed by each thread. That is, when it is necessary to guarantee the processing time, a thread having a long time slice is allocated.
Therefore, it is a precondition for assigning a process to a thread that the cycle does not collapse.

  However, since the time of one time slice is very small compared to the execution time of the entire process, the thread schedule is set so that the execution time of each thread is as planned within a predetermined time. The adjustment is performed by the unit 1110. For example, if every thread executes 10 times, the number of executions of each thread is counted, and before the first thread starts the 11th execution, the other threads are not enough 10 times Will run preferentially. For example, the eleventh execution of the first thread is started after all the threads have been executed ten times.

<Thread control processing>
Next, the thread control processing of this processor will be described with reference to FIG.
FIG. 4 is a flowchart showing thread control processing of the processor.
The thread schedule unit 1110 selects a thread to be executed next (step S100). If the control process is just started, it is the first thread.

If all the processes assigned to each thread have been completed (step S110: Y), the thread control process is terminated.
When executing the next thread which is the selected thread, the thread name 1411 is passed to the reconfiguration control unit 1400 to request reconfiguration.
Upon receiving the request, the reconfiguration control unit 1400 determines whether or not the received thread name 1411 uses the reconfigurable computing unit 1200 with reference to the thread information table 1410 stored in the configuration information storage unit 1300. To do. Specifically, when the configuration is specified in the configuration information 1412 corresponding to the received thread name 1411, it is determined that the reconfigurable computing unit 1200 is used.

When it is determined not to use (N in step S120), the reconfiguration control unit 1400 returns to that effect to the thread scheduling unit 1110, and the thread scheduling unit 1110 starts executing the next thread as soon as the currently executing thread is finished. (Step S150).
On the other hand, if it is determined that the area is to be used (step S120: Y), it is determined whether or not an area to be reconfigured is free (step S130). Specifically, it is determined whether or not the number of areas shown in the number of used areas 1413 corresponding to the received thread name 1411 are free.

The reconfiguration controller 1400 internally stores the number of the area that is currently used, and when the time slice of the thread that is being used has been completed, the area that was being used is assumed to be free. And erase from the stored area number.
If it is determined that the area is not free (step S130: N), the reconfiguration control unit 1400 notifies the thread scheduling unit 1110 of that fact. The thread schedule unit 1110 selects a different thread (step S100). The thread schedule unit 1110 stores the number of executions of each thread and preferentially selects it at an appropriate time to match the number of executions of all threads.

  On the other hand, when it is determined that the area is empty (step S130: Y), the reconfiguration control unit 1400 notifies the reconfigurable computing unit 1200 that reconfiguration is performed, and the configuration information storage unit 1300 receives the received information. The configuration information 1412 corresponding to the thread name 1411 is transmitted by designating the area. After transmission, the reconfiguration control unit 1400 updates the area number in use stored therein.

The reconfigurable computing unit 1200 performs reconfiguration with the configuration information sent from the configuration information storage unit 1300 (step S140), and notifies the reconfiguration control unit 1400 when it is completed.
The reconfiguration control unit 1400 that has received the notification that the reconfiguration has been completed returns it to the thread scheduling unit 1110, and the thread scheduling unit 1110 starts executing the next thread immediately after the currently executing thread is terminated ( Step S150).

The thread schedule unit 1110 that has started the thread selects the next thread (step S100).
<Embodiment 2>
<Overview>
In the first embodiment, a reconfigurable arithmetic unit that is reconfigured for each thread is used. In this embodiment, a reconfigurable arithmetic unit that is reconfigured is used for each instruction.

Hereinafter, the configuration of the second embodiment will be described.
<Configuration>
FIG. 5 is a diagram illustrating a configuration example of the processor 5000 according to the second embodiment.
The processor 5000 includes an instruction fetch unit 5100, an instruction decode unit 5200, an operation control unit 5300, an address table storage unit 5400, a reconfiguration information storage unit 5500, a reconfigurable operation unit 5600, and a fixed function operation unit 5700. A storage unit 5010 is provided.

The instruction storage unit 5010 has a function of storing instruction codes to be executed by the processor 5000.
The instruction fetch unit 5100 has a function of reading an instruction code from the instruction storage unit 5010 and passing it to the instruction decoding unit 5200.
The instruction decode unit 5200 has a function unique to the present invention in addition to a normal function of receiving and analyzing an instruction code from the instruction fetch unit 5100.

Specifically, in the case of an instruction using the reconfigurable computing unit 5600 as a result of decoding, the address where the configuration information is stored is obtained from the instruction type from the address table storage unit 5400 and stored in the reconfiguration information storage unit 5500. This is a function for passing the address and causing the reconfigurable computing unit 5600 to transmit the configuration information.
The address table storage unit 5400 has a function of storing an instruction type and an address of its configuration information in association with each other.

The arithmetic control unit 5300 has a function of controlling the arithmetic operation according to the result decoded by the instruction decoding unit 5200. Instructions are issued to the fixed function computing unit 5700 and the reconfigurable computing unit 5600 with timing.
The reconfiguration information storage unit 5500 has a function of storing configuration information corresponding to a plurality of instructions. The head address of each piece of configuration information stored here is stored in the address table storage unit 5400 in association with the instruction type. This configuration information is the same as the configuration information stored in the configuration information storage unit 1300 of the first embodiment.

The reconfiguration information storage unit 5500 also has a function of transmitting the configuration information of the designated address to the reconfigurable computing unit 5600 in response to an instruction from the instruction decoding unit 5200.
The reconfigurable computing unit 5600 is a reconfigurable computing unit, and is the same as the reconfigurable computing unit 1200 of the first embodiment. However, in this embodiment, it is assumed that it is divided into four areas.

The fixed function computing unit 5700 is composed of a plurality of fixed function computing units. In this embodiment, the fixed function computing unit 5700 is composed of three fixed function computing units (5701, 5702, 5703).
Hereinafter, the correspondence between the instructions and the configuration information will be briefly described and the operation will be described.
<Correspondence between instruction code and configuration information>
A description will be given of how to obtain configuration information for reconfiguration necessary for execution of an instruction from the instruction code used in the present invention, with reference to FIGS.

FIG. 6 is a diagram illustrating a configuration example of an instruction code used in the present invention, and FIG. 7 is a diagram illustrating a configuration example and content example of the instruction information table 5410.
First, the configuration example of the instruction code in FIG. 6 will be described.
The instruction code 5110 used in the present invention is composed of an operation code 5111 indicating the type of instruction and an operand 5112 indicating a value handled by this instruction.

In the present invention, the operation code 5111 is associated with the configuration information (see the arrow), and is associated when the processor determines that the reconfigurable computing unit 5600 is necessary for executing the instruction. The instruction is executed by the reconfigurable computing unit 5600 reconfigured according to the configuration information.
If the processor determines that the reconfigurable computing unit 5600 is not required for execution of the instruction, the fixed function computing unit 5700 is used for execution.

Next, the instruction information table 5410 in FIG. 7 will be described.
This command information table 5410 is stored in the address table storage unit 5400.
The instruction information table 5410 includes an operation code type 5411, an address 5412, and a used area number 5413.

The operation code type 5411 indicates an operation code of an instruction code, that is, an instruction. Here, it is assumed that only instructions using the reconfigurable computing unit 5600 are described.
Therefore, instructions not described here are executed by the fixed function computing unit 5700.

Next, an address 5412 indicates an address in the reconfiguration information storage unit 5500 of the configuration information associated with the operation code represented by the operation code type 5411. In the present embodiment, the address is used, but any information that can identify the reconstruction information such as an ID may be used.
The used area number 5413 represents the number of areas when the reconfigurable computing unit 5600 is used. For example, the instruction of the operation code type 5411 “Sub” uses the reconfigurable arithmetic unit 5600 reconfigured with the configuration information stored in the address indicated by the address 5412 “addr1”, and the reconfigurable arithmetic unit 5600 is used. For reconfiguration, the number of used areas 5413 “3” is required.

  In the case of the present embodiment, taking into account the number of areas of the reconfigurable computing unit 5600 used by instructions, the order of instructions and instructions when compiling to convert the program into machine language, and when converting to the instruction code 5110 in this embodiment. The number of the area to be reconfigured is determined beforehand. That is, at the time of compiling, the order of instructions to be executed is taken into consideration, the instructions are arranged in such an order that they can be reconfigured during the execution of the previous instruction, and the areas to be reconfigured are determined. In addition, the area number to be used can be known by the instruction decoding unit by, for example, specifying the area number with an operand or determining the area number for each instruction.

<Operation>
Next, how the instruction is executed will be described with reference to FIGS.
FIG. 8 shows an example of a program using the instruction set according to the present invention, and FIG. 9 shows an example of a pipeline operation of a processor that operates the program.
FIG. 10 is a flowchart showing instruction execution processing of the processor of this embodiment.

First, the program of FIG. 8 will be briefly described.
The instruction code of the operation code 5111 “Add” and the operand 5112 “r0, r1, r2” means adding the contents of the register 1 and the contents of the register 2 and assigning the result to the register 0. The operation code 5111 “Sub” The instruction code of the operand 5112 “r3, r1, r3” means that the contents of the register 3 are subtracted from the contents of the register 1 and the result is substituted into the register 3.

  The instruction code of opcode 5111 “Reconf0” and operand 5112 “r2, r0,0xfe” performs the operation “Reconf0” using the contents of register 0 and the immediate value “0xfe”, and assigns the result to register 2 The instruction code of opcode 5111 “Reconf1” and operand 5112 “r3, r1, r3” performs the operation “Reconf1” using the contents of register 1 and the contents of register 3, and the result is stored in register 3. It means to assign.

Next, the operation of the processor that executes the program will be described with reference to FIGS. Description will be made along the flowchart of FIG. 10 with reference to the time chart of FIG.
Assume that the program shown in FIG. 8 is stored in the instruction storage unit 5010.
First, the instruction fetch unit 5100 fetches the instruction code “Add r0, r1, r2” (FIG. 10: step S800, FIG. 9: step S500), and passes it to the instruction decode unit 5200.

The instruction decoding unit 5200 that has received the instruction code analyzes the received instruction code.
If the received instruction code is a code indicating completion (FIG. 10: step S810: Y), the instruction decoding unit 5200 ends the process.
If the instruction code is not a code indicating completion (FIG. 10: Step S810: N), the instruction decoding unit 5200 passes the operation code 5111 “Add” to the address table storage unit 5400, and the address of the configuration information Request.

The address table storage unit 5400 refers to the instruction information table 5410, searches the operation code type 5411 for the presence of the passed operation code 5111 “Add”, and as a result, the reconfigurable arithmetic unit 5600 uses it. A message to the effect is returned to the instruction decoding unit 5200 (FIG. 10: Step S820: N, FIG. 9: Step S510).
The instruction decoding unit 5200 that has received that the reconfigurable computing unit 5600 is not used passes the decoded instruction “Add r0, r1, r2” to the arithmetic control unit 5300.

The calculation control unit 5300, to which the decoding result is passed, issues an instruction to the fixed function calculator 5700 and executes the instruction code “Add r0, r1, r2” (FIG. 10: Steps S830 and 840).
The instruction fetch unit 5100 fetches the instruction code “Add r0, r1, r2” and then fetches the next instruction code “Sub r3, r1, r3” (FIG. 10: step S800, FIG. 9: step S520), and the instruction The data is passed to the decoding unit 5200.

Receiving the instruction code, the instruction decoding unit 5200 passes the operation code 5111 “Sub” to the address table storage unit 5400 to request the address of the configuration information.
The address table storage unit 5400 refers to the instruction information table 5410 and searches the operation code type 5411 for the passed operation code 5111 “Sub”. As a result, the address table storage unit 5400 decodes the address 5412 “addr1”. Return to unit 5200 (FIG. 10: step S820: Y, FIG. 9: step S600).

The instruction decode unit 5200 that has received the address passes the received address 5412 “addr1” to the reconfiguration information storage unit 5500, and sends the configuration information of the address to the reconfigurable computing unit 5600 to instruct that reconfiguration is performed. To do.
The instruction decoding unit 5200 that has given the instruction passes the decoded instruction of “Sub r3, r1, r3” to the arithmetic control unit 5300.

On the other hand, the reconfiguration information storage unit 5500 that received the instruction transmits the received address configuration information to the reconfigurable computing unit 5600 to perform reconfiguration (FIG. 10: step S850, FIG. 9: step S610).
This reconfiguration reconfigures three areas of the four areas of the reconfigurable computing unit 5600 (see FIG. 7).

The arithmetic control unit 5300 to which the decoding result is passed issues an instruction to the reconfigurable arithmetic unit 5600 and executes the instruction code “Sub r3, r1, r3” (FIG. 10: step S860, FIG. 9: step S620). .
Thereafter, the execution result is written to the register 3 (FIG. 9: Step S630).
In this way, instructions are sequentially executed simultaneously.

Here, when the case where the instruction code “Reconf0 r2, r0,0xfe” next to the instruction code “Sub r3, r1, r3” is executed is executed, this opcode “Reconf0” uses the reconfigurable computing unit 5600.
Therefore, reconfiguration is performed while “Sub r3, r1, r3” is being executed (FIG. 9: Step S620) (FIG. 9: Step S700).

Since this operation code type 5411 “Reconf0” has the number of used areas 5413 “1”, it can be reconfigured even if “Sub r3, r1, r3” is executing using three areas. Become.
The same applies when the next instruction code “Reconf1 r3, r1, r3” is executed.
Thus, in a processor having a reconfigurable arithmetic unit, it becomes possible to control the reconfigurable arithmetic unit in units of instructions, and flexible and high-performance arithmetic processing can be realized with high area efficiency. .

<Modification>
Next, a modification of the second embodiment will be described.
In the second embodiment, the reconfigurable computing unit is reconfigured for each instruction. However, in this modification, an example in which a plurality of instructions are reconfigured at once will be described. Since a plurality of instructions can be executed at the same time, the processing speed can be improved.

How an instruction is executed will be described with reference to FIGS.
FIG. 11 shows an example of a program using the instruction set of the present modification, and FIG. 12 shows an example of a pipeline operation of a processor that operates the program.
FIG. 13 is a flowchart showing instruction execution processing of the processor according to this modification.
First, the contents of each command in the program of FIG. 11 are the same as those of FIG.

  However, “Reconf0 r2, r0,0xfe” and “Reconf1 r3, r1, r3” are different in the same stage. In FIG. 11, for convenience of explanation, “Reconf0 r2, r0,0xfe” and “Reconf1 r3, r1, r3” are shown side by side to indicate that they are executed at the same time. It is assumed that the compiler outputs the instruction so that the instruction decoding unit 5200 can interpret the execution.

  For example, considering the number of areas of the reconfigurable computing unit 5600 used by instructions, the order of instructions and the number of areas to be reconfigured by instructions are determined at the time of compilation. That is, at the time of compiling, in consideration of the order of instruction execution, instructions that can be executed at the same time and that can be reconfigured at the same time are selected, and the areas to be reconfigured are determined. For the instructions to be executed in parallel and the area number to be used, for example, an instruction code indicating parallel execution is provided, and these instructions and the area number are described in the operand.

Specifically, in compilation, “Sub” and “Reconf0” can be reconfigured at the same time, considering the number of used areas 5413, but “Sub” and “Reconf1” cannot be reconfigured at the same time. become. This is because “Sub” and “Reconf0” use four areas together, but “Sub” and “Reconf1” require five areas together (see FIG. 7).
The operation of the processor that executes the program will be briefly described with reference to FIGS. Description will be made along the flowchart of FIG. 13 with reference to the time chart of FIG.

The flowchart of FIG. 13 describes only the differences from the flowchart of FIG. Specifically, it is from step S900 to step S920.
“Reconf0 r2, r0,0xfe” and “Reconf1 r3, r1, r3” use a reconfigurable computing unit, and the instruction decode unit 5200 analyzed that they are executed at the same time has an operation code 5111 “Reconf0” and “Reconf0” "Reconf1" is passed to the address table storage unit 5400 to request the address of the configuration information.

The address table storage unit 5400 refers to the instruction information table 5410 and returns addresses 5412 “addr4” and “addr5” to the instruction decoding unit 5200 (FIG. 13: step S820: Y, step S900: Y).
The instruction decode unit 5200 that has received the address passes the received addresses 5412 “addr4” and “addr5” to the reconfiguration information storage unit 5500 and sends the configuration information of the address to the reconfigurable computing unit 5600 for reconfiguration. Instruct them to do it.

The instruction decoding unit 5200 that has given the instruction passes the decoded instructions of “Reconf0 r2, r0,0xfe” and “Reconf1 r3, r1, r3” to the arithmetic control unit 5300.
On the other hand, the reconfiguration information storage unit 5500 that received the instruction transmits the received address configuration information to the reconfigurable computing unit 5600 to perform reconfiguration (FIG. 13: step S910, FIG. 12: step S700).

The arithmetic control unit 5300 to which the decoding result is passed issues an instruction to the reconfigurable arithmetic unit 5600 and executes the instruction codes “Reconf0 r2, r0,0xfe” and “Reconf1 r3, r1, r3” (FIG. 13: Step S920, FIG. 12: Step S710).
The instruction decoding unit 5200 that has received the instruction code does not use the reconfigurable computing unit (FIG. 13: step S820: N), and if it uses one instruction (FIG. 13: step S900: N). The same processing as that in FIG. 10 is performed (FIG. 13: Step S830 to Step S870).

Although the case where two instructions using a reconfigurable computing unit are processed simultaneously has been described here, the number of instructions that can be issued simultaneously is not limited to two. Further, it may be processed simultaneously with an instruction using the fixed function computing unit 5700.
<Supplement>
The processor according to the present invention has been described above based on the embodiment. However, the processor may be partially modified, and the present invention is not limited to the above-described embodiment. That is,
(1) In the second embodiment, the operation code of the instruction code is associated with the configuration information, but the present invention is not limited to this.

For example, a code indicating configuration information may be inserted in a part of the operand. As shown in FIG. 14, the ID of the configuration information or the like is entered in the operand field 5160 of the instruction code 5150, and the configuration information is specified according to the ID at the time of execution.
(2) In the second embodiment, for the convenience of explanation, the execution of a plurality of fixed function computing units is not described in detail, but these fixed function computing units and reconfigurable computing units can be executed simultaneously. In some cases, a plurality of instructions may be issued simultaneously.

Depending on the determination of the instructions to be issued at the same time, the calculation efficiency can be greatly improved.
That is, in an arithmetic unit configured by reconfigurable hardware, a plurality of types of arithmetic functions can be selectively executed. Therefore, an arbitrary instruction can be executed, and by using the instruction set according to the present invention, it is possible to create a program that realizes an optimum function with improved instruction parallelism.

The operation for determining instructions to be issued at the same time may be performed in the processor at the time of instruction interpretation, or may be performed in advance at the time of a program given to the processor.
(3) In the embodiment, the reconfigurable computing unit is divided into a plurality of homogeneous areas, but each area may have a different logical block, and the size of the area is It may be different.
(4) In the embodiment, the logical block constituting the reconfigurable arithmetic unit is a circuit unit including a look-up table and a flip-flop, but the logical block is an ALU (Arithmetic and Logical Unit), shift or It may be configured by a unit that performs data control, logical operation, a flip-flop, or the like, that is, by a combination of general logic circuits.

  Since the processor according to the present invention can realize flexible and high-performance processing while suppressing the circuit scale, it is particularly useful as an arithmetic unit of an image processing LSI.

FIG. 11 illustrates a configuration example of a processor 1000. FIG. 2A is a diagram illustrating a configuration example and content example of the thread information table 1410, and FIG. 2B is a time chart illustrating a thread execution example. FIG. 3A is a diagram illustrating a configuration example and content example of the thread information table 1420, and FIGS. 3B and 3C are time charts illustrating thread execution examples. It is a flowchart which shows the process of the thread control of this processor. 6 is a diagram illustrating a configuration example of a processor 5000 according to the second embodiment. FIG. It is a figure which shows the structural example of the instruction code used in Embodiment 2. FIG. 5 is a diagram showing a configuration example and content example of an instruction information table 5410. FIG. It is an example of a program using the instruction set concerning Embodiment 2. It is an example of the pipeline operation | movement of the processor which operated the program. 6 is a flowchart illustrating instruction execution processing of the processor according to the second embodiment. It is an example of a program using the instruction set of a modification. It is an example of the pipeline operation | movement of the processor which operated the program of the modification. It is a flowchart which shows the instruction execution process of the processor of a modification. It is a figure which shows the modification of the structure of the instruction code used in Embodiment 2. FIG.

Explanation of symbols

1000 5000 processor 1100 multi-thread processor 1110 thread schedule unit 1110 thread schedule unit 1120 fixed function computing unit 1200 reconfigurable computing unit 1300 configuration information storage unit 1300 reconfiguration information storage unit 1400 reconfiguration control unit 1410 1420 thread information table 5010 instruction Storage unit 5100 Instruction fetch unit 5110 5150 Instruction code 5111 Operation code 5112 Operand 5200 Instruction decode unit 5300 Operation control unit 5400 Address table storage unit 5410 Instruction information table 5413 Number of used areas 5500 Reconfiguration information storage unit 5600 Reconfigurable arithmetic unit 5700 Fixed function Computing unit

Claims (5)

A processor for executing a program comprising a plurality of instructions,
A reconfigurable integrated circuit; and
Reconfiguration means for reconfiguring a portion of the integrated circuit based on circuit configuration information;
Configuration information storage means for storing circuit configuration information corresponding to each of a plurality of instructions;
Selection means for selecting two or more instructions capable of simultaneously reconfiguring the integrated circuit based on the circuit configuration information;
And a processor for executing the two or more instructions in parallel using an integrated circuit reconfigured based on circuit configuration information corresponding to the two or more instructions selected by the selection means. An instruction fetch unit that reads an instruction code including an operation code and an operand from the instruction storage unit;
An instruction decode unit for decoding the read instruction code;
An instruction execution unit including a reconfigurable computing unit;
A control unit for controlling the operation of the instruction execution unit according to the decoding result of the instruction decoding unit;
For each type of opcode, a configuration information storage unit that stores circuit configuration information for configuring a circuit necessary for executing the process indicated by the opcode,
With
The instruction decoding unit instructs the reconfigurable computing unit to perform reconfiguration according to a decoding result,
The reconfigurable computing unit performs reconfiguration using circuit configuration information corresponding to the decoded opcode in accordance with an instruction from the instruction decoding unit,
The control unit is configured to issue a decoded instruction code to a reconfigurable computing unit that has been reconfigured, thereby controlling the data indicated by the operand to execute the process indicated by the opcode. The instruction decoding unit selects two or more instructions that can be simultaneously reconfigured in the reconfigurable computing unit based on the circuit configuration information,
The reconfigurable computing unit performs reconfiguration using circuit configuration information corresponding to two or more selected instructions,
The processor according to claim 2, wherein the control unit controls to execute the two or more instructions using two or more reconfigured circuits. The instruction execution unit further includes a fixed function computing unit,
Wherein, when the circuit configuration information corresponding to the operation code which is decoded is not present in the configuration information storage unit, a processor according to claim 2, wherein the controls to execute instructions using the fixed function calculator.   The processor according to claim 2, wherein the operand includes a code indicating correspondence between an operation code and circuit configuration information.

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