JP4552644B2 - Bus arbitration system and bus arbitration method - Google Patents

Description

  The present invention relates to a bus arbitration system and a bus arbitration method for arbitrating bus use requests for accessing memories from a plurality of bus masters.

Conventionally, there are a round robin method and a first-come-first-served basis when arbitrating bus use requests for accessing memories from a plurality of bus masters. In the round-robin method, the bus master that has received the latest bus use permission is arbitrated so that the priority order of the next bus use permission is the lowest, and the bus use permission is cyclically granted to bus use requests from each bus master. Is made. On the other hand, in the first-come-first-served basis method, bus use permission is made in the order of input in response to bus use requests from a plurality of bus masters (for example, see Patent Document 1).
JP 2001-67308 A

  However, in the round robin method, when the bus use requests from a plurality of bus masters compete, the bus use permission cannot be continuously given for the bus use requests from the same bus master. For this reason, when the bus master reads data from the memory, it may not be possible to read appropriate data.

  FIG. 1 is a timing chart of bus arbitration by a conventional round robin method. In FIG. 1, when accessing the memory, the bus master A outputs a bus use request “REQ1” for executing the write command “write1” to the arbiter that performs bus arbitration. The bus use request “REQ2” for executing the write command “write2” is output. Thereafter, the bus master B outputs a bus use request “REQ3” for executing the read command “read1” to the arbiter. The write commands “write1”, “write2” and the read command “read1” are for accessing the same address space of the memory.

  In this case, if there are no conflicting bus use requests for accessing the same address space of the memory, the arbiter sends a bus use request “REQ1”, “REQ2” from the bus master A, and a bus use request from the bus master B. The bus use permission is performed in the order of “REQ3”, and a bus use permission response (ACK) is returned to each. Accordingly, the bus master B reads the data in the memory after being written by executing the write commands “write1” and “write2”.

  On the other hand, as shown in FIG. 1, the execution of the write command “write1” (internal processing) is prolonged for some reason and the internal bus becomes in use, and a bus use request for accessing the same address space of the memory When a bus use request “REQ2” from the bus master A and a bus use request “REQ3” from the bus master B compete, the arbiter performs bus arbitration by the round robin method. In other words, when the use of the internal bus for execution of the write command “write1” is finished and the arbitration timing has arrived, the arbiter first grants bus use to “REQ3” from the bus master B and reads When the internal bus is used to execute the command “read1” and the use of the internal bus is completed, the bus use is permitted for “REQ2” from the bus master A, and the write command “write2” is executed. For the internal bus to use. Accordingly, the bus master B reads the data in the memory after being written by executing the write command “write1”, and reads data different from the case where the bus use requests are not in conflict.

  On the other hand, in the first-come-first-served basis, as described above, there is no problem that the data to be read differs depending on the presence / absence of bus use request conflict. However, in the first-come-first-served basis, internal bus assignments are biased against bus masters with high frequency of bus use requests, processing of other bus masters is delayed, the required performance cannot be met, or the overall system performance deteriorates .

    FIG. 2 is a timing chart of bus arbitration according to a conventional first-come-first-served basis. In FIG. 2, the arbiter sends a bus use request “BUS1” from the bus master A, a bus use request “REQ2” from the bus master A, a bus use request “REQ3” from the bus master B, and a bus from the bus master A. The use request “REQ4”, the bus use request “REQ5” from the bus master C, and the bus use request “REQ6” from the bus master A are input in this order, and the bus use is permitted in this input order. Accordingly, the allocation of the internal bus is biased with respect to the bus master A having a high frequency of bus use requests, and the time until the bus use permission is issued for the bus use requests of the other bus masters B and C is prolonged. C delays processing.

  The present invention has been made to solve the above-described conventional problems, and provides a bus arbitration system and a bus arbitration method capable of performing appropriate bus arbitration.

  The bus arbitration system of the present invention arbitrates a bus use request for accessing a memory from a plurality of bus masters, a bus use request storage means for storing a bus use request input from the bus master, and the bus For each bus use request stored in the use request storage means, address space duplication determination means for judging whether or not the address space of the memory to be accessed overlaps with other bus use requests, and the address space duplication judgment means In response to the bus use request determined that the address space of the memory to be accessed overlaps with another bus use request, the bus use is permitted in the order of input from the bus master, and the address space duplication determination means uses the address space duplication determination means. In response to a bus use request that has been determined that the memory address space does not overlap with other bus use requests. And a bus use arbitration means for performing a bus grant in the order of robin system.

  With this configuration, bus round-trip buses are used because bus arbitration is performed in the order of input for bus use requests that have overlapping address spaces in the memory to be accessed, in other words, for conflicting bus use requests. As in the arbitration, it is possible to prevent the read data from being different depending on the presence or absence of a bus use request conflict. On the other hand, for bus use requests where the address space of the memory to be accessed does not overlap, in other words, for bus use requests that do not conflict, bus arbitration is performed in a round-robin fashion, so a bus master with a high frequency of bus use requests. In contrast, the bus allocation is biased and the processing of other bus masters is prevented from being delayed. That is, normally, the bus allocation is prevented from being biased with respect to the bus master having a high frequency of bus use requests by the round robin method, and appropriate data is read when a conflict occurs in the bus use requests. Can be.

  In the bus arbitration system according to the present invention, the bus use request includes a start address and a size of an address space of an access destination memory, and the address space duplication determination means includes an access destination memory included in the bus use request. Whether or not the address space of the memory to be accessed overlaps with another bus use request is determined based on the head address and size of the address space.

  In the bus arbitration system according to the present invention, the address space duplication determination means may determine the end of the address space of the access destination memory based on the start address and size of the address space of the access destination memory included in the bus use request. An address is calculated, and it is determined whether or not the address space of the access destination memory of another bus use request is included between the start address and the end address of the access destination address space.

  With this configuration, the address space of the access destination memory corresponding to each bus use request is specified by the head address and the end address, and the duplication is determined.

  In the bus arbitration system according to the present invention, the bus use request storage means stores the bus use request in association with input order information from the bus master, and the bus use arbitration means stores the address space duplication determination. In response to the bus use request determined by the means that the address space of the memory to be accessed overlaps with other bus use requests, the bus use is permitted in the order according to the information of the input order.

  With this configuration, the input order of bus use requests from the bus master is specified, and bus arbitration is performed in the input order.

  The bus arbitration method of the present invention arbitrates a bus use request for accessing a memory from a plurality of bus masters, and uses the bus use request input from the bus master in a use request storage means. A request storage step, and an address space duplication determination step for determining whether or not the address space of the memory to be accessed overlaps with another bus use request for each of the bus use requests stored in the bus use request storage means The bus use permission is determined in the order of input from the bus master in response to the bus use request determined in the address space duplication determination step that the address space of the access destination memory is duplicated with other bus use requests, and the address space In the duplication judgment step, the address space of the accessed memory does not overlap with other bus use requests. Against the determined bus use request and has a bus arbitration performing a bus grant in the order of a round-robin fashion.

  In the bus arbitration method of the present invention, the bus use request includes a start address and a size of an address space of an access destination memory, and the address space duplication determination step includes an access destination memory included in the bus use request. Whether or not the address space of the memory to be accessed overlaps with another bus use request is determined based on the head address and size of the address space.

  In the bus arbitration method of the present invention, the address space duplication determination step may be configured such that the address space end of the access destination memory is based on the start address and the size of the address space of the access destination memory included in the bus use request. An address is calculated, and it is determined whether or not the address space of the access destination memory of another bus use request is included between the start address and the end address of the access destination address space.

  Further, in the bus arbitration method of the present invention, the bus use request storing step associates the bus use request with information on the input order from the bus master and stores the information in the bus use request storing means, and the bus use arbitration step. However, in the address space duplication determination step, for the bus use request determined that the address space of the memory to be accessed overlaps with another bus use request, the bus use is permitted in the order according to the information of the input order. .

  According to the present invention, normally, when a bus use request conflict occurs while preventing the bus assignment from being biased with respect to a bus master having a high frequency of bus use requests by the round robin method, appropriate data is used. Can be read out.

  Hereinafter, a bus arbitration system according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 3 is a diagram showing a configuration of the bus arbitration system of the present embodiment. The bus arbitration system 100 shown in FIG. 3 arbitrates requests for use of an internal bus for accessing memories from a plurality of bus masters. The command management circuit 110, the arbitration selection circuit 120, the first-come-first-served arbiter 130, and the round robin The arbiter 140 is configured.

  The command management circuit 110 includes a command queue 112 and an address comparison circuit 114. The command management circuit 110 inputs a bus use request from each bus master. This bus use request includes the identification information of the output bus master, the head address, and the size. Here, the start address indicates the start address of the address space of the memory accessed by the command executed when use of the internal bus is permitted according to the bus use request, and the size is the size of the address space. Indicates.

  Further, each time a bus use request is input, the command management circuit 110 adds the input order information to the newly input bus use request (new bus use request) and stores it in the command queue 112. Here, the input order information represents the input order of the added bus use request to the command management circuit 110. Note that the capacity of the command queue 112 is set according to the number of bus masters from which the bus use request is output. When a bus use request exceeding the capacity is generated, the bus use request exceeding the capacity is generated. Are discarded without being stored in the command queue 112.

  Further, the address comparison circuit 114 is included in the combination of the start address and size included in the new bus use request in the command queue 112 and other bus use requests (existing bus use requests) already stored in the command queue 112. Whether or not there is a conflict between the new bus use request and the existing bus use request is determined based on the combination of the start address and the size. Here, the contention of the bus use request means that the address space of the memory accessed by the command executed when the use of the internal bus is permitted according to the bus use request is changed according to the other bus use request. Indicates that the address space of the memory accessed by a command executed when use of the bus is permitted overlaps.

  If there is a conflict between the new bus use request and the existing bus use request, the address comparison circuit 114112114 outputs address hit information indicating the conflict to the arbitration selection circuit 120. Further, the address comparison circuit 114112114 generates the result of the determination as to whether there is a conflict as arbitration result information, and outputs the result to the round robin arbiter 140 and the outside via the selection comparison circuit 120. This arbitration result information is composed of input order information added to each bus use request determined to be in conflict.

  Further, each time the new bus use request is stored in the command queue 112 together with the input order information, the address comparison circuit 114 generates an internal request corresponding to the new bus use request and outputs the internal request to the arbitration selection circuit 120. Here, the internal request includes bus master identification information included in the corresponding bus use request and input order information added to the corresponding bus use request.

  FIG. 4 is a diagram illustrating a detailed configuration of the arbitration selection circuit 120. The arbitration selection circuit 120 illustrated in FIG. 4 includes selectors 122 and 124. The selector 122 outputs an internal request to the first-come-first-served arbiter 130 when address hit information is input. The internal request output to the first-come-first-served arbiter 130 is an internal request corresponding to each competing bus use request. On the other hand, the selector 122 outputs an internal request to the round robin arbiter 140 when address hit information is not input. The internal request output to the round robin arbiter 140 is an internal request corresponding to a bus use request that does not conflict. The processing of the selector 124 will be described later.

  Again, referring back to FIG. First-come-first-served arbiter 130 grants bus use in a first-come-first-served basis based on the input internal request. Next, the first-come-first-served arbiter 130 returns a bus use permission response (ACK) to the bus master specified by the identification information of the bus master included in the internal request for which bus use is permitted. Furthermore, the first-come-first-served order arbiter 130 returns the input order information included in the internal request for which the bus use is permitted to the arbitration selection circuit 120.

  On the other hand, the round robin arbiter 140 grants bus use in a round robin manner based on the input internal request. Next, the round robin arbiter 140 returns a bus use permission response (ACK) to the bus master specified by the identification information of the bus master included in the internal request for which bus use is permitted. Further, the round robin arbiter 140 returns the input order information included in the internal request that is subject to bus use permission to the arbitration selection circuit 120.

  In addition, when the round robin arbiter 140 inputs arbitration result information, the same input order information included in the arbitration result information among the internal requests that have been input so far but are not yet subject to bus use is input. Excludes items including order information from the bus use permission target.

  The selector 124 in the adjustment selection circuit 120 outputs, to the command management circuit 110, the input order information included in the internal request that is the subject of bus use permission from the first-come-first-served arbiter 130 and the round robin arbiter 140 as a queue cancellation flag. .

  When the command management circuit 110 receives the queue cancellation flag, the command management circuit 110 deletes the input order information represented by the queue cancellation flag and the bus use request to which the input order information is added from the command queue 112. As a result, the bus use request permitted to use the internal bus is deleted from the command queue 112, and a new bus use request can be stored.

  Next, the operation of the bus arbitration system will be described with reference to the flowchart. FIG. 5 is a flowchart showing the operation of the bus arbitration system 100.

  The command management circuit 110 determines whether or not a new bus use request (new bus use request) from any of the bus masters has been input (S101). When a new bus use request is input, the command management circuit 110 adds the input order information indicating the input order of the new bus use request to the command management circuit 110 to the new bus use request and stores it in the command queue 112. (S102).

  Next, the address comparison circuit 114 in the command management circuit 110 receives the combination of the start address and size included in the new bus use request in the command queue 112, the start address included in the existing bus use request in the command queue 112, and Based on the size combination, it is determined whether or not the new bus use request is in conflict with the existing bus use request, and an internal request corresponding to the new bus use request is generated (S103).

  Specifically, the address comparison circuit 114 includes a combination of the start address and size included in the new bus use request in the command queue 112, and a combination of the start address and size included in the existing bus use request in the command queue 112. Based on each of these, a value obtained by adding the size to the head address is calculated. This value indicates the end address of the address space of the memory accessed by the command executed when the use of the internal bus is permitted in response to the bus use request. Further, the address comparison circuit 114 is configured so that in the address space of the memory, the start address included in the new bus use request is ahead of the end address corresponding to the existing bus use request, or the end address corresponding to the new bus use request. Is behind the start address included in the existing bus use request, it is determined that the address space of the access destination overlaps and the new bus use request conflicts with the existing bus use request. For example, in FIG. 6, since the head address corresponding to the new bus use request in queue # 2 of command queue 112 is ahead of the end address included in the existing bus use request in queue # 1, the new bus use request already exists. It is determined that there is a conflict with the bus use request.

  The internal request generated by the address comparison circuit 114 is output to the arbitration selection circuit 120.

  If there is a conflict between the new bus use request and the existing bus use request as a result of the determination of the presence / absence of the conflict in S103 (Yes in S104), the address comparison circuit 114112114 generates address hit information (S105). The generated address hit information is output to the arbitration selection circuit 120.

  Further, the address comparison circuit 114112114 generates arbitration result information (S106). The generated arbitration result information is output to the round robin arbiter 140 and the outside via the selective comparison circuit 120.

  When the address hit information is input, the selector 122 in the arbitration selection circuit 120 receives the internal request corresponding to the new bus use request and the internal request corresponding to the existing bus use request that conflicts with the new bus use request. Output to the forward arbiter 130. The first-come-first-served arbiter 130 sets the bus use permission by the first-come-first-served method based on the input internal requests (S107). As a result, the bus use is permitted in accordance with the order of input from the bus master to the command management circuit 110 for each competing bus use request.

  Further, when the round robin arbiter 140 inputs the arbitration result information, the same input order as the input order information included in the arbitration result information is included in the internal request that has been input so far but has not yet been permitted to use the bus. It is determined whether or not there is information including information. If there is an internal request that includes the same input order information as the input order information included in the arbitration result information, the internal request was originally not competing with the other bus use permission for the corresponding bus use permission. Although the round robin arbiter 140 was subject to the bus use permission, it subsequently conflicted with the new bus use permission input by the command management circuit 110, so that the bus use permission was changed to the first-come-first-served basis arbiter 130. Is. For this reason, the round robin arbiter 140 excludes an internal request including the same input order information as the input order information included in the arbitration result information from the bus use permission target. As a result, the existing bus use request competing with the new bus use permission is excluded from the round-robin bus use permission target (S108).

  On the other hand, if there is no conflict between the new bus use request and the existing bus use request as a result of the determination of the presence / absence of conflict in S103 (No in S104), the address comparison circuit 114112114 does not generate address hit information. Only mediation result information is generated (S109). The generated arbitration result information is output to the round robin arbiter 140 and the outside via the selective comparison circuit 120.

  The selector 122 in the selection comparison circuit 120 outputs an internal request corresponding to a new bus use request that does not conflict with an existing bus use request to the round robin arbiter 140 when address hit information is not input. Then, the round robin arbiter 140 sets the bus use permission by the round robin method based on the input internal request.

  As described above, when each of the first-come-first-served arbiter 130 and the round robin arbiter 140 sets the bus use permission, the bus use permission (bus arbitration) is performed based on the setting.

  FIG. 7 is a timing chart of bus arbitration according to a first-come-first-served basis with respect to competing bus use requests. In FIG. 7, when accessing the memory, the bus master A outputs a bus use request “REQ1” for executing the write command “write1” to the command management circuit 110, and then writes A bus use request “REQ2” for executing the command “write2” is output. Thereafter, the bus master B outputs a bus use request “REQ3” for executing the read command “read1” to the command management circuit 110. Accordingly, the input order in the command management circuit 110 is the order of the bus use request “REQ1”, the bus use request “REQ2”, and the bus use request “REQ3”. The write commands “write1”, “write2” and the read command “read1” are for accessing the same address space of the memory.

  In this case, the execution of the write command “write1” is prolonged for some reason and the internal bus becomes in use, and a bus use request from the bus master A, which is a request to use the bus for accessing the same address space of the memory. REQ2 ”and the bus use request“ REQ3 ”from the bus master B compete, in other words, if the internal request corresponding to the bus use request“ REQ2 ”and the internal request corresponding to the bus use request“ REQ3 ”compete, The address comparison circuit 114112114 in the management circuit 110 generates address hit information and outputs it to the arbitration selection circuit 120. Then, the arbitration selection circuit 120 outputs the internal request corresponding to the bus use request “REQ2” and the internal request corresponding to the bus use request “REQ3” to the first-come-first-served basis arbiter 130.

  When receiving these internal requests, the first-come-first-served arbiter 140 sets the bus use permission in the order of the bus use request “REQ2” and the bus use request “REQ3” in accordance with the order input by the command management circuit 1102.

  Then, the first-come-first-served arbiter 140 ends the use of the internal bus for executing the write command “write1” corresponding to the bus use request “REQ1”, and when the arbitration timing arrives, the bus use request “REQ2” is set. In response to the corresponding internal request, the bus use request “REQ2” is permitted to use the bus, and the internal bus is used to execute the write command “write2” corresponding to the bus use request “REQ2”. Further, when the use of the internal bus is completed, the bus use permission is granted to the bus use request “REQ3” in response to the internal request corresponding to the bus use request “REQ3”, and the bus use request “REQ3” is handled. The internal bus is used to execute the read command “read1” to be executed.

  FIG. 8 is a timing chart of bus arbitration by a round robin method for bus use requests that do not conflict. In FIG. 8, the bus master A outputs a bus use request “REQ1” to the command management circuit 110, and subsequently outputs a bus use request “REQ2”. Thereafter, the bus master B outputs a bus use request “REQ3” to the command management circuit 110. Further, the bus master A outputs a bus use request “REQ4” to the command management circuit 110. Subsequently, the bus master B outputs a bus use request “REQ5” to the command management circuit 110, and then The bus master A outputs a bus use request “REQ6” to the command management circuit 110. Accordingly, the input order in the command management circuit 110 is as follows: bus use request “REQ1”, bus use request “REQ2”, bus use request “REQ3”, bus use request “REQ4”, bus use request “REQ5”, bus use request “ REQ6 ".

  In this case, the bus use request “REQ2” from the bus master A and the bus use request “from the bus master B” while the bus use permission for the bus use request “REQ1” from the bus master A is performed and the internal bus is used. REQ3 ”is input to the command management circuit 110, and when an internal request corresponding to these bus use requests is input to the round robin arbiter 140, the round robin arbiter 140 receives the bus use request“ REQ3 ”from the bus master B, The bus use permission is set in the order of the bus use request “REQ2” from the bus master A.

  The first-come-first-served arbiter 140 completes the bus use request in response to the internal request corresponding to the bus use request “REQ3” when the use of the internal bus corresponding to the bus use request “REQ1” is completed and the arbitration timing has come. When the use of the bus is granted to “REQ3”, the internal bus is used, and the use of the internal bus is completed, the bus use request “REQ2” is received in response to the internal request corresponding to the bus use request “REQ2”. Is permitted to use the internal bus.

  Further, while the bus use permission for the bus use request “REQ4” from the bus master A is performed and the internal bus is used, the bus use request “REQ5” from the bus master C and the bus use request “REQ6” from the bus master A are used. ”Is input to the command management circuit 110, and when an internal request corresponding to these bus use requests is input to the round robin arbiter 140, the round robin arbiter 140 receives the bus use request“ REQ5 ”from the bus master C, the bus master The bus use permission is set in the order of the bus use request “REQ6” from A.

  The first-come-first-served arbiter 140 terminates the use of the internal bus corresponding to the bus use request “REQ4”, and when the arbitration timing arrives, the bus use request according to the internal request corresponding to the bus use request “REQ5”. When the use of the bus is permitted to “REQ5”, the internal bus is used, and the use of the internal bus is completed, the bus use request “REQ6” is generated in response to the internal request corresponding to the bus use request “REQ6”. Is permitted to use the internal bus.

  In this way, the bus arbitration system 100 performs bus arbitration by the round robin method in the normal case where the address space of the memory to be accessed does not overlap between the bus use requests, that is, the bus use requests do not compete. Therefore, it is possible to prevent the bus assignment from being biased with respect to a bus master having a high frequency of bus use requests and delaying the processing of other bus masters. On the other hand, the bus arbitration system 100 has a first-come-first-served basis for the conflicting bus use requests when the address space of the access destination memory overlaps between the bus use requests, that is, when the bus use requests compete. Thus, the bus arbitration is performed in the order of input, so that the read data is prevented from differing depending on the presence or absence of bus use request contention as in the conventional round-robin bus arbitration.

  As described above, the bus arbitration system and the bus arbitration method according to the present invention prevent the bus allocation request from being biased with respect to the bus master having a high bus use request frequency by the round robin method, and When contention occurs, appropriate data can be read out, which is useful as a bus arbitration system and a bus arbitration method.

It is a timing chart of the bus arbitration by the conventional round robin system. It is a timing chart of the bus arbitration by the conventional first-come-first-served system. It is a figure which shows the structure of the bus arbitration system of this embodiment. It is a figure which shows the detailed structure of an arbitration selection circuit. It is a flowchart which shows operation | movement of a bus arbitration system. It is a figure which shows an example of the competition state of a new bus use request and an existing bus use request. It is a timing chart of the bus arbitration by the first-come-first-served basis with respect to competing bus use requests. It is a timing chart of the bus arbitration by the round robin method with respect to the bus use request | requirement which does not compete.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Bus arbitration system 110 Command management circuit 112 Command queue address comparison circuit Command queue 114 Address comparison circuit Command queue address comparison circuit 120 Arbitration selection circuit 122, 124 Selector 130 First-come-first-served basis arbiter 140 Round robin arbiter

Claims (8)

In a bus arbitration system that arbitrates bus use requests to access memory from multiple bus masters,
Bus use request storage means for storing a bus use request input from the bus master;
For each of the bus use requests stored in the bus use request storage means, address space duplication determination means for judging whether or not the address space of the access destination memory overlaps with other bus use requests;
In response to the bus use request determined by the address space duplication determination means that the address space of the memory to be accessed is duplicated with other bus use requests, the bus use is permitted in the input order from the bus master, and the address space duplication is performed. A bus use arbitration unit for permitting bus use in the order of a round-robin method in response to a bus use request that is determined by the judging unit to have an address space of an access destination memory that does not overlap with other bus use requests; A characteristic bus arbitration system. The bus use request includes a start address and a size of an address space of an access destination memory,
The address space duplication determination means determines whether the address space of the access destination memory overlaps with other bus use requests based on the start address and size of the address space of the access destination memory included in the bus use request. The bus arbitration system according to claim 1, wherein: The address space duplication determination means calculates the end address of the address space of the access destination memory based on the start address and the size of the address space of the access destination memory included in the bus use request, and the access destination address 3. The bus arbitration system according to claim 2, wherein it is determined whether or not an address space of a memory to be accessed by another bus use request is included between the head address and the end address of the space. The bus use request storage means stores the information on the input order from the bus master in association with the bus use request,
The bus use arbitration unit is configured to respond to the bus use request determined by the address space duplication determination unit that the address space of the access destination memory overlaps with another bus use request in an order according to the information of the input order. 4. The bus arbitration system according to claim 1, wherein a bus use permission is given. In a bus arbitration method for arbitrating bus use requests for accessing memory from a plurality of bus masters,
A use request storage step of storing in the use request storage means a bus use request input from the bus master;
For each bus use request stored in the bus use request storage means, an address space duplication determination step for judging whether the address space of the memory to be accessed overlaps with other bus use requests;
In response to the bus use request determined in the address space duplication determination step that the address space of the access destination memory is duplicated with other bus use requests, the bus use is permitted in the input order from the bus master, and the address space duplication is performed. A bus use arbitration step for permitting the use of a bus in the order of a round-robin method in response to a bus use request that is determined in the judging step that the address space of the memory to be accessed does not overlap with other bus use requests. A characteristic bus arbitration method. The bus use request includes a start address and a size of an address space of an access destination memory,
The address space duplication determination step determines whether the address space of the access destination memory overlaps with another bus use request based on the start address and the size of the address space of the access destination memory included in the bus use request. The bus arbitration method according to claim 5, wherein the bus arbitration method is determined. The address space duplication determination step calculates the end address of the address space of the access destination memory based on the start address and the size of the address space of the access destination memory included in the bus use request, and the access destination address 8. The bus arbitration method according to claim 7, wherein it is determined whether or not an address space of an access destination memory of another bus use request is included between the head address and the end address of the space. In the bus use request storage step, the bus use request storage means stores the bus use request in association with information on the input order from the bus master,
In the bus use arbitration step, in response to the bus use request determined in the address space duplication determination step that the address space of the access destination memory is duplicated with another bus use request, the bus use arbitration step is performed in an order according to the information of the input order. 8. The bus arbitration method according to claim 5, wherein a bus use permission is performed.

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