JP3341260B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus capable of measuring the performance of each instruction executed in the information apparatus.

[0002]

2. Description of the Related Art As a performance measurement of an information processing apparatus, there is a case where an instruction processing time (for example, a time required for processing a memory access instruction and an IO peripheral device access instruction) is measured. A conventional performance measurement method is disclosed in, for example, Japanese Patent Application Laid-Open No. 2-3124.
7, JP-A-2-31248, JP-A-2-14
As disclosed in Japanese Patent No. 4636, for example, by counting the processing time of a plurality of instructions executed within a designated range and measuring the execution time and the number of executions of the instruction, the average instruction execution time (performance (Measured value) could be calculated.

As a concrete example, as shown in FIG. 6, a plurality of instruction codes A1, A
The average instruction execution time (performance measurement value) is obtained by separately counting the processing times of 2, A3, and A4, and measuring the total (T = t1 + t2 + t3 + t4) and the number of executions (four times in this case) of the instruction execution time. Was calculated. here,
The instruction codes A1, A2, A3, and A4 indicate that the instruction contents are the same, but the execution times t1, t2, t3, and t4 vary.

[0004]

However, in the conventional performance measurement method, a plurality of instructions (for example, an instruction code A
(A1, A2, A3, A4) are being executed simultaneously in one system, the exact execution time of a certain instruction (for example, the instruction code A1) cannot be known. That is, although it was possible to observe the average instruction execution time within a certain range, it was not possible to accurately measure the execution time for each specific one instruction (for example, the instruction code A1).

[0005] As means for measuring the instruction execution time per instruction, a circuit and pins for observing the instruction execution time are provided at an interface portion (bus or the like) of the instruction generation circuit, and the logic is used by using a logic analyzer or the like. It is conceivable to set a probe on the pin and observe it. However, this means that equipment such as a logic analyzer is required,
There are drawbacks in that individual pins are required for the measurement, that the measurement time is long, that the measurement is performed with a great burden, and that efficient measurement cannot be performed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an information processing apparatus capable of measuring the performance of each instruction executed in an information device and not placing a great burden on a measurer at the time of measurement. .

[0007]

Means for Solving the Problems To solve the above problems, the present invention generates a plurality of instruction codes at random,
In an information processing apparatus that performs a process according to the instruction code under the control of the instruction processing means, from among the plurality of instruction codes, an instruction code extracting means for setting an instruction code to be measured , and Instruction code
Unique instruction identifier adding method that adds a unique instruction identifier
And an instruction code set by the instruction code extracting means.
And the unique instruction identifier adding means adds an instruction identifier
If the instruction code matches, the added instruction
An instruction identifier storage means for storing only the identifier, the instruction code extraction unit to be measured and set instruction code before
Measurement flag set means for serial and instruction code randomly generated to set a flag indicating that the effect is measured <br/> Teichu if they match, the measuring flag set means in said measurement
If you set the flag indicating that is the measurement, the measuring removing means to eliminate the measurement of other instruction code, under the exclusion of other instruction code by the measuring removing means, by the measuring flag set means Flag indicating that
When set, the unique instruction identifier adding means instructs
The measurement of the instruction execution time of the instruction code obtained by adding a decree identifier
Instruction execution time measuring means to be started, and the entire information processing apparatus
Control the body and issue an instruction processing completion ID after completing the instruction processing.
And an instruction processing means for executing the instruction.
And a command processing completion ID to be stored in the command identifier storage means.
The instruction identifier is compared with the stored instruction identifier.
Terminates instruction execution time measurement by instruction execution time measurement means.
Characterized in that that.

[0008] In this way, since the instruction code other than the instruction code to be measured is eliminated by the measurement elimination means, only the instruction code to be measured can be measured alone.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings by dividing it into [I] principle explanation and [II] embodiment explanation. [I] Principle Description In the present invention, it is possible to measure the processing time of a desired individual instruction code in a state where an information processing apparatus to which the present invention is applied performs a normal process.

As shown in FIG. 3, the principle of the present invention is that a plurality of instruction codes (A1, A2, A3, A4, B1, B2,
When C) is in conflict, the execution times of the individual instructions whose performance is to be measured may differ as described above. Therefore, the measurement target is sampled, and the processing time of the execution state for each instruction is measured. For example, the instruction codes A for performance measurement include instruction codes A1 (execution time t1), A2 (t2), A3 (t3), and A4 (t4) having different execution times.
There are four types of execution time, sampling is performed, and the execution time of each instruction code (for example, A1) is measured.

FIG. 1 is a functional block diagram illustrating the principle of the present invention, and FIG. 2 is a processing flowchart of FIG. Now, consider a case where the execution time t1 of the instruction code A1 is measured. As shown in FIG. 1 and FIG.
Diagnosis processing device (diagnosis processor) 11 as “ extraction means ”
The instruction code A1 to be measured is set 12 (step S1a), and the instruction code A1 is input to the instruction code comparison unit 15 (step S2).

From the other side, the instruction generating circuit 13 randomly issues instruction codes (α, β, γ, δ...) Generally used in the information processing apparatus (step S1b), and the instruction code is being measured. The instruction identifier ID for identifying the
Added by D adding unit 14 (instruction code α + ID (α))
(Step S1b), input to the instruction code comparison unit 15 (Step S2). Here, the instruction identifier ID (α) is
This indicates that the instruction identifier is a unique instruction identifier (the same instruction identifier is not added to any other instruction) added only to the instruction code α.

The instruction code comparison unit 15 compares the input instruction code A1 with the instruction code α (excluding ID (α)) (step S2).
2: YES), the added instruction identifier ID (α) is stored in the measurement target ID storage unit 16 as “instruction identifier storage means” until the measurement processing of the instruction (instruction code A1) is completed (step S3). If the flag (measurement flag) indicating that the performance of the matched instruction (that is, instruction code A1) is being measured at the same time is not "1" (step S4: NO), the "measurement flag setting means" The in-measurement flag setting unit 17 sets the in-measurement flag (sets "1") (step S5). If the measurement flag is “1” (step S4: YES) and if the instruction code A1 does not match the instruction code α (step S2: NO), the instruction code A1 is out of the measurement target, and The normal processing of the information processing device is executed.

In step S5, the measuring flag "1" is set.
Is set, the execution time counter (counter) 18 constituting the "instruction execution time measuring means" counts up (+1) 18a for each machine clock, until the measurement processing of the instruction code A1 is completed (step S7). Are continued to be added and accumulated (step S6). In this case, while the performance measurement flag is set to “1”, the subsequent measurement target instruction code (for example, the instruction B1 in FIG. 3) is issued by the “measurement elimination unit” (not shown). In this case, the instruction execution time is not measured.

An instruction processing completion ID from the instruction processing unit 21 controlling the entire information processing apparatus is an instruction processing completion ID.
The instruction generation circuit 13 and the ID comparison unit 19 via the storage unit 24
Is sent back (step S7). This reply ID is compared with the command identifier (in this case, ID (α)) stored in the measurement target ID storage unit 16 by the ID comparison unit 19 (step S8). Then, the value of the execution time counting unit 18 (accumulated value of the count) is stored in the execution time saving unit 23, and sampling is performed according to a read instruction from the diagnostic processing device 11. By this sampling, the execution time t1 of the instruction code A1 is measured (step S9). Therefore, since the execution time of the measurement target is saved in the execution time saving unit 23, the execution time of the subsequent instruction whose instruction code matches is counted as the next performance measurement instruction.

Thereafter, the above operation is repeatedly executed, and the processing time of a certain instruction is sampled. Based on the sampled result, it is possible to analyze the performance bottleneck of the information processing device, and it is possible to obtain execution time data with sufficient accuracy without affecting the actual operation. In addition, useful information for hardware tuning (adjustment) can be obtained.

[II] Description of Embodiment (1) First Embodiment FIG. 4 is a block diagram of an information processing apparatus J of this embodiment.
In FIG. 4, an instruction generation circuit 51 is provided in each memory or I
It has a function of generating a command for accessing the O peripheral device and adding a unique command identifier (hereinafter, referred to as ID) to the access command. That is, the instruction generation circuit 51
Of the instruction generation circuit 13 and the instruction ID adding unit 14.

The instruction designation register 53 stores an instruction code (corresponding to the instruction code A1 in FIG. 3 ) to be measured by the diagnostic processor 62 (corresponding to the diagnostic processor 11) via the diagnostic interface circuit 61.

The first comparison circuit 55 (the instruction code comparison unit 15)
) Is a general instruction code (an instruction code excluding an ID) transmitted from the instruction generation circuit 13 and used in the information processing apparatus, and an instruction code for performance measurement stored in the instruction designation register 53. A1 is compared, and if a match is detected, an instruction to start performance measurement of an access instruction (in this case, instruction code A1) to a memory or an IO peripheral device is issued. The instruction ID register 54 is provided in the first comparison circuit 5
5 detects a match and stores the ID of the instruction to be accessed (for example, the ID of the instruction code A1) when the performance of the previously issued instruction to be accessed is not measured.

The second comparison circuit 56 compares the ID of a reply (reply) to the access instruction (instruction code A1) from the instruction processing circuit 52 with the content (ID) stored in the instruction ID register 54. When a match is detected by the second comparison circuit 56, the access instruction to be measured (the instruction code A
The end of the performance measurement of 1) is instructed. The flag 57 is used when the first comparison circuit 55 detects a match and the performance measurement of the access instruction (instruction code A1) is not performed.
1 is set to indicate that the access instruction is being executed. When a match is detected by the second comparison circuit 56, it is reset to "0" to indicate that the access instruction has been completed.

The counter 58 determines that the flag 57 is "1".
At this time, "+1" is added for each machine clock, the execution time of the instruction whose performance is to be measured is counted, and the second comparison circuit 56 sets "1".
Reset if. Counter value save register 59
Saves and stores the value of the counter 58 when the second comparison circuit 56 detects a match. Counter valid flag 6
0 is set to “1” to indicate that the counter value saving register 59 is valid when the second comparison circuit 56 detects a match, and the diagnostic interface circuit 61
Reset when an instruction to read the counter value saving register 59 is issued.

The value of the counter value saving register 59 is validated only when the performance measurement data is instructed to be read from the diagnostic interface circuit 61 and the counter valid flag is "1". The counter value saving register 59 and the counter valid flag 60 are controlled as a performance measurement control signal via the diagnostic interface circuit 61 to read the performance measurement value from the diagnostic processor 11, and the performance measurement result of the access instruction to the memory or the IO peripheral device is obtained. The diagnostic interface circuit 61 controls the transmission of the instruction to the diagnostic processor, and traces the instruction ID according to the type of the instruction executed in the information processing apparatus. The execution time is accurately sampled each time there is a read instruction from the diagnostic processor 11.

Next, the operation of this embodiment will be described.
Here, a memory access instruction will be mainly described. Note that the same operation is performed in the case of an access instruction to an IO peripheral device.

In order to measure the performance of a memory access instruction for writing or reading to or from the instruction processing circuit 52, the diagnostic interface 62
1 transmits a performance measurement target instruction (instruction code A1).
The performance measurement target instruction is set in the instruction designation register 53. The instruction generation circuit 51 issues a memory access instruction with an ID added to the instruction processing circuit 52. Here, the ID is unique within the information processing apparatus J as described above, and is carried around between the instruction generation circuit 51 and the instruction processing circuit 52 until the processing is completed.

The first comparing circuit 55 compares the transmitted output of the instruction designation register 53 (that is, the instruction code A1) with the transmitted code of the memory access instruction, and when a match is detected, The ID of the memory access is set in the instruction ID register 54. At the same time, the flag 57
Is set to "1" to instruct the start of performance measurement. Here, when the flag 57 is already “1”, that is, when the performance measurement of the previously issued memory access instruction has been performed, in other words, when the processing of the instruction whose performance is to be measured has not been completed, Even if the 1 comparison circuit 55 detects a match in a subsequent memory access instruction, the instruction ID register 54 is not updated.

For example, a memory access instruction that matches the instruction code stored in the instruction designation register 53 is an instruction code a → an instruction b → an instruction c → an instruction d → an instruction e → an instruction f
→. . . When the instruction generation circuit 51 continuously issues → instruction l → instruction m → instruction n, the first issued instruction code a becomes the instruction whose performance is to be measured, and only the ID accompanying the instruction code a is issued. It is set in the ID register 54.
At the same time, "1" is set to the flag 57 to indicate that one performance measurement target instruction is being executed, and that the counter 58 for counting the execution time of the performance measurement target instruction is set to "+1" every machine clock. To instruct. Flag 57 is "
During 1 ", the counter 58 continues to add" +1 ".

Here, the instruction ID register 54 is not updated until the execution of the instruction code a is completed. That is, the counter 58 counts only the execution time of the instruction code a . If the execution of the instruction code a is completed before issuing the instruction n, the next instruction whose performance is to be measured is the instruction n. Therefore, the instructions c to l match the instruction code of the instruction whose performance is to be measured, but the execution time is not counted. In this example, the execution time of only the instruction code a and the instruction n is counted,
Only when there is a read instruction from the diagnostic processor 11, sampling is performed as a performance measurement result. The instruction measurement result is sequentially updated each time execution of the performance measurement target instruction is completed.

The instruction processing circuit 52 replies (replies) via the reply ID of the memory access instruction issued from the instruction generation circuit 13. The second comparison circuit 56 compares the reply ID with the output of the instruction ID register 54. When a match is detected, it indicates that the execution of the performance measurement target instruction has been completed, resets the flag 57, and resets the counter 58. The value is stored in the counter value saving register 59. Further, "1" is set to the counter valid flag 60 to indicate that the value of the counter value saving register 59 is valid.

On the other hand, the diagnostic processor 62 instructs a diagnostic interface circuit (diagnosis processor) 62 to periodically read and sample the performance measurement data of the memory access instruction stored in the counter value saving register 59, (Diagnosis processor) 6
From 2, the value of the counter value saving register 59 is read and controlled. When a read instruction is issued from the diagnostic interface circuit 61 and the counter valid flag 60 is “0”, it indicates that the instruction whose performance is to be measured is not being executed or is being executed.
Invalidates the value sent from.

As described above, the instruction designation register 53
Only the instruction that matches the instruction set in the instruction is set as the performance measurement target instruction, and by tracing the ID of the instruction issued from the instruction generation circuit 51, the memory access instruction execution indicating the execution start and completion timing of the performance measurement target instruction is performed. Time can be measured accurately and easily. Also,
It is possible to obtain distribution information of the execution time required for processing of the instruction whose performance is to be measured from the sampled data obtained by repeatedly performing the above operation.

(2) Second Embodiment FIG. 5 is a block diagram of the present embodiment. The difference between the present embodiment and the first embodiment is that an instruction code register 70 enclosed by a dashed line is added. The present embodiment is a sampling of the instruction execution time when a specific value (for example, ALL “1”) other than the instruction code transmitted from the instruction generation circuit 51 is set in the instruction designation register 53.

The diagnostic processor 62 instructs the diagnostic interface circuit 61 to measure the instruction execution time for the instruction processing circuit 52 with all instruction codes as performance targets. The instruction sets a value (here, for example, ALL “1” ) other than the instruction code transmitted from the instruction generation circuit 51 in the instruction designation register 53. By setting "ALL1" in the instruction designation register 53, it becomes effective to set all instructions to be executed in the information processing apparatus as performance measurement target instructions, and a first comparison circuit for comparing the instruction designation register 53 with the instruction code. When the flag 57 is not "1" as in the first embodiment, the output of the flag 55 is changed to "1" by the execution start signal of the first instruction.
1 ". At the same time, the instruction ID associated with the first instruction is set in the instruction ID register 54, and the instruction ID
An instruction code indicating the type is set in the instruction code register 70.

The flag 57 remains "1" until the first instruction is completed. Since the performance measurement is being executed, the instruction ID register 54 and the instruction code register 70 are not updated until the first instruction is completed.

For example, when the memory access instruction is read instruction code a → write instruction b → write instruction c → read instruction d → read instruction e → write instruction f →. . . When the instruction generation circuit 51 continuously issues → write instruction l → write instruction m → write instruction n, the first issued read instruction code a becomes a performance measurement target instruction and is attached to the read instruction code a. Only the ID to be executed is set in the instruction ID register 54. Further, the instruction code of the read instruction code a is set in the instruction code register 70. At the same time, the flag 57
Is set to "1" to indicate that one performance measurement target instruction is being executed, and the counter 58 for counting the execution time of the performance measurement target instruction is set to "+1" every machine clock.
To do so. While the flag 57 is "1", the counter 58 continues to add "+1".

Here, the instruction ID register 54 is not updated until the execution of the read instruction code a is completed. That is, the counter 58 counts only the execution time of the read instruction code a. The execution of the read instruction code a corresponds to the write instruction n.
, The next instruction whose performance is to be measured is a write instruction n. Therefore, from the above-mentioned instruction b to instruction l
Until, the instruction is not a performance measurement instruction, and the execution time is not counted. In this example, a read instruction code a and a write instruction n
Only count the execution time.

The instruction processing circuit 52 returns the reply ID of the memory access instruction issued from the instruction generation circuit 51. The second comparison circuit 56 calculates the reply ID and the instruction I
The outputs of the D register 54 are compared, and when a match is detected,
This indicates that the execution of the performance measurement target instruction is completed, the flag 57 is reset, and the value of the counter 58 is stored in the counter value saving register 59. Further, "1" is set to the counter valid flag 60 to indicate that the value of the counter value saving register 59 is valid.

On the other hand, the diagnostic processor 11 instructs a diagnostic interface circuit (diagnosis processor) 62 to periodically read and sample the performance measurement data of the memory access instruction stored in the counter value saving register 59, (Diagnosis processor) 6
From 2, the value of the counter value saving register 59 is read and controlled. When a read instruction is issued from the diagnostic interface circuit 61 and the counter valid flag 60 is “0”, it indicates that the instruction whose performance is to be measured is not being executed or is being executed.
Invalidates the value sent from. In addition, a command to read the instruction code register 70 is issued, and the instruction code of the performance measurement target is read from the instruction code register 70.

As described above, all the instructions processed in the information processing apparatus are subjected to performance measurement, and the means for holding the instruction code and the trace of the ID of the instruction whose performance is to be measured enable the execution of the instruction to be started. It indicates the completion timing and samples the instruction execution time and instruction code.

The above-described diagnostic processor or PC
An information processing apparatus provided with a means for arbitrarily setting an interval for reading a performance measurement result from a command instruction register, an instruction ID register, a comparison circuit, a flag, a counter,
An information processing apparatus including a counter value saving register and a counter valid flag in a multiplexed manner and capable of simultaneously performing performance measurements corresponding to a plurality of types (instruction codes) is not illustrated. However, the operation of the above-described embodiment is performed.

[0040]

As described above, according to the present invention, the following effects can be obtained. First, an instruction for performance measurement to be issued in the information processing device is specified, and if the instruction matches the instruction on the left, a unique I
A diagnostic circuit for deciding the execution start and completion of the performance measurement target instruction by tracing D; counting the instruction execution time by a counter for counting the instruction execution time of the performance measurement target; The instruction execution time, which is the performance measurement result, is read more regularly, and the instruction execution time is sampled. In the above case, even if the same type of instruction is executed in an overlapped manner, since the ID attached to each instruction is unique, only one instruction with the instruction ID set is counted as the performance measurement target and the instruction execution time is counted. Is possible.

Second, a value which does not overlap with the instruction code used in the instruction generation circuit 51 is set in the instruction specification register 53 (for example, "ALL 1" is set in the instruction specification register).
Means for making the performance measurement target instruction effective for all instructions executed in the information processing device,
By providing a register for storing the code of the instruction to be measured, it is possible to simultaneously sample the instruction execution time and the instruction type.

Third, when performance measurement is performed, a diagnostic processor is connected as necessary, and a PC or the like is provided as an alternative function in place of the diagnostic processor. It is possible to implement.

Therefore, the present invention makes it possible to implement the above-mentioned performance measurement without compromising the original operation with a relatively simple and small amount of HW (hardware), and repeatedly executes each of the above operations. As a result, it is possible to obtain the processing time of each instruction in the information processing apparatus (distribution of the instruction execution time of the instruction whose performance is to be measured, frequency distribution in the type of instruction) from the sampled performance measurement result with sufficient accuracy. . That is, it is possible to obtain sampling data with sufficient accuracy for performing the performance analysis of the information processing apparatus.

Further, by analyzing the sampled data described above, it is possible to relatively easily analyze the performance bottleneck in the information processing apparatus, and further improve the performance based on the performance bottleneck. To provide useful information as a means for tuning a program and hardware for the purpose.

[Brief description of the drawings]

FIG. 1 is a functional block diagram illustrating the principle of the present invention.

FIG. 2 is a flowchart illustrating the principle of the present invention.

FIG. 3 is a diagram showing an example of an occurrence state of an instruction code to which the present invention is applied.

FIG. 4 is a block diagram of a first embodiment of the present invention.

FIG. 5 is a block diagram of the second embodiment.

FIG. 6 is a diagram illustrating an example of a conventional case where the contents of instruction codes are the same but execution times are different.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Diagnostic processor 12 Performance measurement target instruction set 13 Instruction generation circuit 14 Instruction ID addition part 15 Instruction code comparison part 16 Measurement target ID storage part 17 Under measurement flag 18 Execution time counting part 19 ID comparison part 21 Instruction processing part 22 Performance measurement value Control circuit 23 Execution time saving unit

Claims (3)

(57) [Claims] 1. A method for generating a plurality of instruction codes at random,
An information processing apparatus for performing a process corresponding to the instruction code under the control of the instruction processing unit from among the plurality of instruction codes, and the instruction code extraction means for setting an instruction code to be measured, generated in the random Unique instruction knowledge in instruction code
A unique instruction identifier adding means for adding an identifier, and an instruction code set by the instruction code extracting means,
The instruction that the unique instruction identifier adding means added the instruction identifier
If the instruction code matches, the added instruction identifier
A command identifier storage means for storing only the instruction code extracting means and an instruction code to be measured is set and the instruction code randomly generated matches
Measurement flag set means for setting a flag indicating that is being measured when, to the effect that the measurement flag set means is in the measurement shown
If you set the A flag, a measuring exclusion means for excluding the measurements of the other instruction code, under the exclusion of other instruction code by the measuring removing means,
The fact that the measurement is being performed by the measuring flag setting means
Is set, the unique instruction identification
The instruction addition time measuring means for starting measurement of the instruction execution time of the instruction code to which the instruction identifier is added by the child addition means, and the entire information processing apparatus are controlled , and the instruction is executed after the completion of the instruction processing.
And a command processing unit for issuing a decree processing completion ID, the command processing completion ID that the instruction processing unit issues, the
Compare with the instruction identifier stored in the instruction identifier storage means,
If they match, the instruction by the instruction execution time measuring means
An information processing apparatus for ending measurement of an execution time . Reading the measured instruction execution time.
2. The information processing apparatus according to claim 1, further comprising means for arbitrarily setting an interval . 3. Multiple means for measuring said instruction execution time
Instruction execution time corresponding to multiple instruction codes
The information processing apparatus according to claim 1 , further comprising a unit that simultaneously performs measurement of the information.