JP3227200B2 - Display control device and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device and method, and more particularly to a display control device and method, for example, which can use a ferroelectric liquid crystal as an operating medium for updating a display and maintain an updated display state by applying an electric field or the like. The present invention relates to a display control device and method for a display device having a display element.

[0002]

2. Description of the Related Art In general, a display device is used as an information display means for performing a visual expression function of information in an information processing system or the like.
Display devices are widely known.

In display control in a CRT display device, C
The writing operation of the system side CPU to the video memory as the display data buffer of the RT side and the reading and display operations of the display data from the video memory by the CRT controller of the CRT side are executed independently of each other.

In the case of CRT display control as described above,
The writing of display data to the video memory to change the display information and the operation of reading the display data from the video memory and displaying it are independent, so the program on the information processing system takes into account any display timing, etc. There is an advantage that desired display data can be written at an arbitrary timing without the necessity of performing.

On the other hand, the CRT, in particular, requires a certain length in the thickness direction of the display screen, and therefore has a large volume as a whole, making it difficult to reduce the size of the entire display device. In addition, this allows a degree of freedom in using an information processing system using such a CRT as a display,
That is, the degree of freedom such as installation location and portability is impaired.

A liquid crystal display (hereinafter, referred to as LCD) can be used to compensate for this. That is,
According to the LCD, the overall size of the display device is reduced (especially thinner).
Can be achieved. Some of such LCDs include the above-described ferroelectric liquid crystal (hereinafter, FLC: Ferroelectric).
There is a display (hereinafter, referred to as FLCD: FLC display) using a liquid crystal cell of a tri-liquid crystal. One of its features is that the liquid crystal cell has a display state preserving property when an electric field is applied. It is in. That is, in the FLCD, the liquid crystal cell is sufficiently thin, and the molecules of the elongated FLC therein are oriented in the first stable state or the second stable state depending on the direction of application of the electric field, and the electric field is removed. However, the respective alignment states are maintained. Due to such bistability of FLC molecules, FLC
D has memory. Such FLC and FLCD
Are described in, for example, Japanese Patent Application No. 62-76357.

As a result, when driving the FLCD,
Unlike CRTs and other liquid crystal displays, there is a margin of time in the cycle of continuous refresh driving of the display screen.
Apart from the continuous refresh driving, the partial rewriting driving for updating the display state of only the portion corresponding to the change on the display screen becomes possible.

As one of the methods, a flag is prepared for each scan line on the display screen, and when rewriting occurs in the VRAM, the corresponding flag is set, and the scan line of the display device corresponding to the set flag is set. There is a means of rewriting the priority.

If the display device has a temperature dependency in the rewriting time for the scan line, control for that is necessary. Control such as changing the refresh driving cycle and the number of jumping lines in the interlaced scanning is performed by the temperature. There is a method based on information.

[0010]

However, in the above-mentioned conventional example, it is necessary to make the flag judgment by the number of scanning lines on the display screen, and a high resolution (for example, a screen size of 128) is required.
In the case of (0 dots × 1024 lines), the time spent for the flag determination is long, and the throughput of the entire display control is reduced.

Since the rewriting time of the scanning line of the display device depends on the temperature, the interlace value is increased when the temperature is lowered, that is, when the rewriting time is increased, so that the field frequency is increased to suppress flicker. , Cannot follow at high speed.

[0012]

According to the present invention, one or two or more rewrite flag registers having increased redundancy are provided in parallel with rewrite flag registers corresponding to each scan line on a screen, and these are rewritten in an environment such as temperature. In this case, the display device whose rewriting performance depends on temperature is optimally accessed by switching and using it.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of an information processing system using a display device having a display control device according to one embodiment of the present invention.

In FIG. 1, reference numeral 101 denotes a CPU for controlling the entire information processing system, and reference numeral 102 denotes an arithmetic processor for supporting the arithmetic processing of the CPU 101 at high speed. 1
Numeral 03 denotes a ROM in which programs for realizing the basic control functions of the CPU 101 are stored, and numeral 104 denotes a ROM 103 executed by the CPU 101 and a hard disk drive 111 described later
And a main memory used to store a program loaded from the floppy disk device 113 or as a work area when executing the program.

Reference numeral 105 designates a connection between the main memory 104 and a VRAM 212, which will be described later, without intervention of the CPU 101.
Alternatively, D for transferring data between the main memory 104 and the VRAM 212 and various devices constituting the system.
MA Controller (Direct Memory Ac)
ESS Controller (hereinafter referred to as DMAC).

Reference numeral 106 denotes an interrupt controller for controlling hardware interrupts generated by various devices constituting the system. Reference numeral 107 denotes a real-time clock, which is a C-MO for storing a calendar, a clock function, and nonvolatile information.
Includes SRAM.

Reference numeral 108 denotes a real-time clock 107 even when power (not shown) is supplied to the system.
Backup lithium battery to function, 109
Is a keyboard for inputting character information such as various characters, control information, etc., 110 is a keyboard controller for controlling the keyboard 109, 111 is a hard disk device as an external storage device, and 112 is a hard disk device between the hard disk device 111 and the system. HDD (Hard Disk Drive) that performs data transfer and other controls between
e) Controller, 113 is a floppy disk device as an external storage device, 114 is an FDD (Floppy Disk Drive) controller for performing data transfer and other controls between the floppy disk device 113 and the present system, and 115 is a mouse as a pointing device , 116 are a mouse controller for making a signal connection between the mouse 115 and the present system, 117 is an external interface for connecting an external input / output device having, for example, an RS232C interface, and 118 is a printer interface for connecting an external printer However, other external devices can be connected.

Reference numeral 201 denotes an FLC display device (hereinafter, referred to as FLCD) having a display screen using a ferroelectric liquid crystal as a display medium; 210, an FLCD interface for controlling the FLCD 201; 119, a system bus for signal connection between the above devices. And comprises a data bus, a control bus, and an address bus.

FIG. 2 is a block diagram showing details of the FLCD 201 and the FLCD interface 210.

In the figure, reference numeral 202 denotes an FLCD unit which is a main component of the FLCD 201;
01 a temperature sensor for measuring the internal atmosphere temperature and the temperature of one or both of the FLCD units 202;
Reference numeral 1 denotes an A / D converter for converting an analog signal, which is output information of the temperature sensor 203, into a digital signal used for a logic circuit.

A VRAM 212 is a memory for storing display data supplied via the system bus 119. The VRAM 212 has a bit information capacity corresponding to the pixels of the FLCD unit 202. , Each pixel is composed of a plurality of bits.

Reference numeral 213 denotes a CRTC (Cat) for mainly accessing the VRAM 212 and creating various timings based on various control signals supplied via the system bus 119.
(hodo Ray Tube Controller)
The connection lines to each unit other than the VRAM 212 are omitted.

Reference numeral 214 denotes a partial write detection unit for detecting the change of the contents of the VRAM 212 and the scan line in the FLCD unit 202 corresponding to the changed position of the VRAM 212, and 301 has a plurality of registers corresponding to each scan line of the FLCD unit 202. , Partial write detection unit 2
According to the information from the FLCD 14, the FLCD unit 202
This is a group of rewrite flag registers that stores, as flag information, which scan line needs to be rewritten, the details of which will be described later.

Reference numeral 215 denotes a selector for selecting an output of one rewrite flag register from the output of the rewrite flag register group 301. Reference numeral 216 denotes a scan time and a partial rewrite of the FLCD unit 202 based on temperature information from the A / D converter 211. This is a timing control unit that determines an interlace mode when no occurrence occurs and controls each unit in the FLCD interface 210, and a connection line with each unit is omitted.

Reference numeral 217 denotes a partial rewrite control unit for controlling partial rewrite performed on the FLCD unit 202 based on the flag information of the rewrite flag register selected by the selector 215. Reference numeral 218 denotes a CRTC 213 and the VRAM 212 of the partial rewrite control unit 217. An address control section arbitrating access to the FLCD interface 210
Is an interface that generates a signal composed of at least display data and scan line information supplied from each unit constituting the FLCD 201.

FIG. 3 shows an example of the rewrite flag register group 301.

In the figure, reference numeral 302 denotes a partial write detection unit 2
A specific flag is turned on by the rewrite flag information from 14
The rewrite flag register (1) corresponding to each scan line of the FLCD unit 202, which can clear all flags or a specific flag directly or indirectly under the control of the partial rewrite control unit 217. ).

Reference numeral 303 denotes a rewrite flag register (1) 30
Flag values for two consecutive two scan lines (flag O
N is set to 1), and its value is set, and, like the rewrite flag register (1) 302, directly or indirectly under the control of the partial rewrite control unit 217, all flags or a specific flag are set. A rewrite flag register (2) capable of clearing a flag.

Reference numeral 304 denotes a rewrite flag register (2) 30
OR operation is performed on two consecutive flag values of 3 and the value is set. Under the control of the partial rewrite control unit 217 similarly to the rewrite flag register (1) 302, all the flags or A rewrite flag register (3) capable of clearing a specific flag.

305 is a rewrite flag register (3) 30
A rewrite flag register (4) that performs an OR logic operation on two consecutive four flag values, sets the value, and can clear all flags or a specific flag under the control of the partial rewrite control unit 217.

Rewrite flag register (1) 302-
(4) The values of 305 are output to the selector 215, respectively.

FIG. 4 is a conceptual diagram showing the relationship between the display screen of the FLCD 202 and the rewrite flag register group 301.

In the figure, when the scan line 2 and the scan line 3 on the display screen of the FLCD 202 are rewritten, the flags corresponding to the scan line 2 and the scan line 3 in the rewrite flag register (1) 302 are turned ON. Rewrite flag registers (2) 303, (3) 304,
(4) The state of all the flags 305 is shown.

In this figure, the rewrite flag register group 301
And the relationship between each scan line on the display screen.
The difference in the visual size of each bit of the register is meaningless.

In FIG. 2, when writing to the VRAM 212 has not occurred, the CRTC 213 controls each part of the FLCD interface 210 and sends display data to the FLCD 201.

In this case, the CRTC 213 accesses the VRAM 212 through the address control unit 218, and the display data read from the VRAM 212 is transmitted to the FLCD 2 together with the scanning line information by the interface 219.
01 is supplied. Here, the scanning line information supplied to the FLCD 201 is not a fixed interlace,
Since it is necessary to partially rewrite the scanning line information to be described later, the display data is added with the scanning line information or information capable of specifying an address on the screen by other means.

FIG. 5 shows an example of a time chart transmitted by the interface 219.

In the figure, CLK is a transfer clock, AH /
DL is a command / image data identification signal. When it is at a high level, it indicates that the information of PIX0 to PIX7 is scanning line information (a0 to a11) and command data (m0 to m3), and when it is at a low level, it is displayed. Indicates data.

Here, PIX0 to PIX7 are signals supplied from the interface 219 through the eight parallel lines of the FLCD 201.

HSYNC is a horizontal synchronizing signal supplied from the CRTC 213 to the FLCD 201 via the interface 219. The address control unit 218
213, the access to the VRAM 212 is executed, and the access is performed by the FLCD unit 20.
2 is supplied to the interface 219 for which scan line.

At this time, the display data read from the VRAM 212 is supplied to the interface 219, and the interface 219 supplies the FLCD 201 with a signal obtained by adding scan line information to the display data. In this case, the rewriting time of the scanning line and the method of interlace are controlled by the CRTC 213. At this time, F
If the LCD unit 202 has a temperature dependency in the rewriting time for the scanning line and the rewriting time based on the temperature and the control of the interlace method are necessary, the temperature sensor 203 is used.
Then, the temperature of the FLCD unit 202 and / or the internal atmosphere temperature of the FLCD 201 are measured, the information is A / D converted by the A / D converter 211, and the temperature is converted into digital data by using the digitized temperature information. Alternatively, the CRTC 213 performs control by a control signal or a timing signal generated by the timing control unit 216 based on the information.

The above is the operation when the data in the VRAM 212 is fixed, that is, when the contents of the VRAM 212 are not rewritten. Next, the operation when the contents of the VRAM 212 are rewritten will be described with reference to FIG.

First, at step 701, a normal interlace display is performed. At 702, it is detected whether the VRAM has been partially replaced. Rewriting of VRAM 212
It is executed from the CPU 101 and other devices connected to the system bus 119. In this case, the VRAM 21
The contents of 2 are partially or entirely rewritten by the address, data, and control signals supplied via the system bus 119. Therefore, by monitoring these signals, the partial write detection unit 214 allows the VRAM 21
2 can be detected, whereby a scan line to be changed on the screen of the FLCD unit 202 can be determined. Also, the partial write detection unit 2
14 monitors the signal supplied to the FLCD interface 210 via the system bus 119 and directly
The same purpose can be achieved by monitoring a signal supplied to the memory element of the RAM 212 or a signal similar thereto. This case is useful when the VRAM 212 is rewritten not only through the system bus 119 but also from the CRTC 213.

Although the above has achieved the object by hardware, a method of achieving the object by software will be described.

For example, when rewriting the contents of the VRAM 212 by adding a device driver as a display function, the method is realized by supplying the address of the rewritten portion to the partial write detection unit 214. In this case, the hardware configuration for detection by the partial write detection unit 214 is considerably simplified. By the above method, F
The partial write detection unit 214 that has detected which scan line on the screen of the LCD unit 202 has changed,
At 3 and 704, the information is set as a rewrite flag in the rewrite flag register (1) 302 of the rewrite flag register group 301. The internal logical configuration of the rewrite flag register group 301 is as shown in FIG. 3. When the number of scan lines is 1024, the number of rewrite flag registers (1) 302 is 1024 and the number of rewrite flag registers (2) 303 is Are 512, the number of registers in the rewrite flag register (3) 304 is 256, and the number of registers in the rewrite flag register (4) 305 is 128.
Individual.

FLCD supporting color or gradation display
In the case of targeting 201, one pixel of the FLCD unit 202 is composed of a plurality of bits, and when individually controlling the rewriting, the number of registers of the rewriting flag register group 303 increases accordingly. If the rewrite flag register (1) 302 is defined as a lower register and the rewrite flag register (4) 305 is defined as an upper register, when the lower register is flag-set by the partial write detector 214, the information is unconditionally stored in the upper register. Will have an effect.

The selector 215 uses the digital temperature information from the A / D converter 211 to rewrite the flag (1).
One of the outputs 302 to (4) 305 is selected and supplied to the partial rewrite control unit 217 as rewrite line information. When the relationship between the temperature of the FLCD unit 202 and the scan line rewriting time is A in FIG. 6, the rewriting flag register group 301 is selected based on the temperature.

That is, when the temperature is low, the scan line rewriting time is long, so that the output of the rewriting flag register (1) 302 is selected by the selector 215. Thereby, FL
The rewriting of the CD unit 202 is executed only for the scan line that needs to be rewritten, that is, only the portion where the contents of the VRAM 212 have been changed.

At a high temperature, the output of the rewrite flag register (4) 305 is selected by the selector 215 because the scan line rewrite time is short, and this has four times the redundancy as compared with the rewrite flag register (1) 302. Performs rewriting of the scanning line based on the flag information of the rewriting flag register (4) 305.

That is, when one flag is ON, rewriting of four scan lines is performed unconditionally.

The rewriting control is performed by the partial rewriting control unit 21.
7 and the scan line rewriting is required by the flag information of the rewriting flag register group 301,
The interlace display performed by the TC 213 is stopped, and the partial rewrite control unit 217 accesses the VRAM 212. The CRTC 213 and the partial rewrite control unit 217 access the VRAM 212 for display.
These accesses are arbitrated by the address control unit 218 based on the control of the partial rewrite control unit 217.

The address control unit 218 further includes an FLCD
Scan line information to be rewritten by unit 202
It is generated based on a signal supplied from C 213 or the partial rewrite control unit 217, and supplied to the interface 219. The interface 219 sends the scanning line information supplied from the address control unit 218 and the display data read from the VRAM 212 to the FLCD 201. At 705, the status of the CRTC 213 is checked. At 706, partial rewrite control unit 217 sets rewrite flag register group 3
The rewriting of the scanning line is performed for one flag based on the information that the flag 01 is ON. Then, at 707, the flag is cleared each time the scan line is rewritten. In this case, the upper flag is set to the flag O at 708.
It is clear from FIG. 3 that the condition is unconditionally affected as in the case of N.

The lower registers are cleared for all flags that use the cleared flag as the propagation flag.

(Other Embodiment 1) Next, another embodiment will be described with reference to FIG. In the figure, 701 to 70
8 is the same operation as in FIG.

FIG. 8 is a flow chart showing the operation when there is a temperature change that changes the selection of the rewrite flag register group 301 when partial rewrite is being performed. 8
At 01, a temperature change is detected, and it is detected whether there is a temperature range change shown in FIG. If there is a change in the temperature range, 8
At 02 and 803, prior to changing the rewrite flag register, a refresh scan is performed, and the partial rewrite control unit 217 clears all the contents of the rewrite flag register group 301. Thereafter, the same operation as shown in FIG. 7 is performed.

As described above, according to this embodiment, the refresh scan is performed, and then the partial writing is detected, so that the influence of the change in temperature on the display speed can be suppressed.

(Second Embodiment) Next, another embodiment will be described with reference to FIG.

When the VRAM 212 is rewritten, not only partial rewriting of the display screen but also VR
A case where the present invention is applied to a normal refresh cycle in which rewriting to the AM 212 has not occurred will be described.

It is assumed that the internal logic of the rewrite flag register group 301 is as shown in FIG. 3, and that interlacing at the time of refresh is performed every 16 lines, that is, 16 fields are written to complete one frame. 1 line, 17 lines for the rewrite flag register (1) 302,
33 lines ... and the flag register is turned on every 16 lines
If N, the states of the other rewrite flag registers are as shown in FIG. Here, it is assumed that the upper flag register at the time of high temperature is selected and the rewrite flag register (3) 304 is selected so that the refresh operation is performed. In this case, since the flags corresponding to the lines 1 to 4 are ON, the lines 1 to 4 are scanned, and then the flag corresponding to the lines 17 to 20 is ON.
Scanning 7 to 20 lines and scanning 1009 to 1012 complete one field. It goes without saying that the flag corresponding to the scanned line is cleared. Hereinafter, similarly, scanning of unscanned 5 to 8 lines, 21 to 24
, And refreshing of one frame is completed when the four-field scanning is completed. By repeating this, a refresh operation is performed.

Here, N indicates an offset value of the scan line, M indicates a value added to N of the scan line, and I indicates the number of scan lines corresponding to one flag. At 901, initial values are set for I, N, and M. This initial value is set in advance in the main memory 104 or the ROM 103.
May be input from the value stored in the keyboard 109 or the like.

Next, it is determined from the temperature which register of the rewrite flag register group 301 is selected.
At 901 it is determined whether or not the rewrite flag register (1) 302 has been selected.
At 2, set 2 to I. Hereinafter, similarly, 903 to 907
Executed until

Here, the rewrite flag register (3) 30
Since 4 is selected, I = 4 and 905 to 9
Move to 08. At 908, the (N + M) th line is transferred, and M + 1 is input to M. At 909, M = I is checked. That is, in 908 and 909, four lines are sequentially transferred from the upper one line.

At 910, N + 16 is input to N.
This is because every 16 lines. At 911,
0 is input to M. This is because the transfer is performed from the uppermost line of the four lines to be transferred. N at 912
Is greater than 1024, that is, whether all scan lines of one screen have been exceeded. If not exceeded, execution is sequentially performed from 908. If so, it is checked at 913 whether N is equal to 1024, ie, whether all scan lines have been executed. When N is equal to 1024, the process is repeated from 901 and executed. If N and 1024 are not equal, N is not equal to N-1024 because all scan lines have not been scanned.
+ I is input and executed sequentially from 908.

As described above, the present invention can be applied to normal refresh.

(Other Embodiment 3) The configuration of the rewrite flag register group 301 in FIG. 3 is as follows.

That is, 1. Lowest register (rewrite flag register (1) 30
2) corresponds to each line of the screen; 2. The number of rewrite flag registers is four, The operation to the upper register is a 2-input OR logic.

This is an example, and is naturally optimized by the temperature characteristics of the display device, the scale of the control circuit, and the like. For example, as shown in FIG. In the lowest register, one flag corresponds to two lines on the screen. 2. The number of rewrite flag registers is 2, There is an advantage that the operation of the upper register can be simplified by including a control circuit for switching between the upper and lower registers by reducing the number of registers and performing a 4-input OR logic operation.

[0069]

As described above, according to the present invention,
The display device can be optimally accessed by having a plurality of rewrite flag registers corresponding to each scanning line on the screen and switching and using the rewrite flag registers according to changes in environment such as temperature.

[Brief description of the drawings]

FIG. 1 is a block diagram of an information processing system using a display device including a display control device of the present invention.

FIG. 2 is a block diagram showing details of an FLCD interface.

FIG. 3 is a diagram showing a rewrite flag register group.

FIG. 4 is a conceptual diagram showing a relationship between a display screen of an FLCD and a rewrite flag register group.

FIG. 5 is a time chart of signals supplied from an interface 219.

FIG. 6 is a diagram showing a relationship between temperature and rewriting time of FLCD.

FIG. 7 is a flowchart showing the operation of the embodiment.

FIG. 8 is a flowchart showing an operation of another embodiment 1.

FIG. 9 is a conceptual diagram showing an example of a rewrite flag register group during a refresh operation.

FIG. 10 is a flowchart showing a refresh operation.

FIG. 11 is a diagram showing another example of a rewrite flag register group.

[Explanation of symbols]

 201 FLCD interface 202 FLCD unit 203 Temperature sensor 211 A / D converter 212 VRAM 213 CRTC 214 Partial write detector 215 Selector 216 Timing controller 217 Partial rewrite controller 218 Address controller 219 Interface 301 Rewrite flag register group

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masami Shimakura 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Morimoto 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inside (72) Inventor Junichi Tanahashi 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Tatsuya Sakashita 3-30-2, Shimomaruko, Ota-ku, Tokyo Canon Inc. ( 72) Inventor Kenzo Ina 3-30-2 Shimomaruko, Ota-ku, Tokyo Within Canon Inc. (58) Field surveyed (Int.Cl. ⁷ , DB name) G09G 3/36 G02F 1/133 560 G06F 15 / 02 315

Claims (6)

(57) [Claims] 1. A table having a display element having temperature-dependent characteristics.
A display control device for updating the display state of the display of the shown device, the corresponding to each predetermined number of display lines of the display device 1
A first flag unit having a first flag, a setting unit for setting a first flag corresponding to a display line on which the display element is updated, and a plurality of first flags corresponding to a plurality of the first flags .
Set if at least one of the flags is set
A second flag means having a second flag to be performed; a detecting means for detecting temperature information of the display device; and detecting either the first flag means or the second flag means based on the detection by the detecting means. Selecting means for selecting, the first flag means or the second flag selected by the selecting means.
The display line of the display device is driven based on the flag means.
A display control device comprising: control means for controlling movement . Wherein said supply means for supplying the data to be displayed on the display device, the storage of the storage means and the storage means, the supplied data is stored for storing data supplied from said supply means <br /> and a detection means for detecting the position, according to claim wherein said setting means, and sets the first flag of the first flag means based on the detected storage location by the detecting means 2. The display control device according to 1. 3. The control means reads the data at the position indicated by the set flag from the selected first flag means or the selected second flag means from the storage means, and controls the display device. The display control device according to claim 2, wherein: 4. The display control device according to claim 1, wherein the display device is a ferroelectric liquid crystal display device. 5. A table having a display element having temperature-dependent characteristics.
A display control method for updating the display state of the shown device, the display device provides data to be displayed on, and stores data said supply in the storage means, said storage means said supplied data is stored detecting a memory <br/> position, based on the storage position the detected first flag corresponding to the predetermined number of display lines of the display device, and, second corresponding to a plurality of the first flag set the second flag, the display based on the setting of either flag of the selected first flag or second flag based on the temperature information of the device, controls the driving of the display lines of the display device that The display control method characterized by the above-mentioned. 6. The display control method according to claim 5, wherein said display device is a ferroelectric liquid crystal display device.