JP3189799B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3189799B2 JP3189799B2 JP23319798A JP23319798A JP3189799B2 JP 3189799 B2 JP3189799 B2 JP 3189799B2 JP 23319798 A JP23319798 A JP 23319798A JP 23319798 A JP23319798 A JP 23319798A JP 3189799 B2 JP3189799 B2 JP 3189799B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor device
- resin film
- semiconductor chip
- back surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Dicing (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体チップのパ
ッド電極膜上に形成された突起電極先端部を外部接続端
子となす半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a protruding electrode tip formed on a pad electrode film of a semiconductor chip is used as an external connection terminal.
【0002】[0002]
【従来の技術】一般にパターン形成が完了した半導体ウ
エハは裏面研削法を用いて所定の厚みに研削される。こ
の裏面研削法は、保護フィルムとなる塩化ビニールなど
を基材とする軟質性フィルムを半導体ウエハのパターン
面に貼り付け、軟質フィルム上から半導体ウエハを均一
に加圧して回転させながら、ダイヤモンド粒が樹脂中に
練入された粒石により半導体ウエハ裏面を研削、除去す
るものである。2. Description of the Related Art Generally, a semiconductor wafer on which a pattern has been formed is ground to a predetermined thickness using a back surface grinding method. In this backside grinding method, a soft film made of a base material such as vinyl chloride as a protective film is attached to the pattern surface of a semiconductor wafer, and while the semiconductor wafer is uniformly pressed and rotated from above the soft film, diamond grains are removed. This is to grind and remove the back surface of the semiconductor wafer with the granules mixed in the resin.
【0003】そして研削された半導体ウエハのスクライ
ブラインを切断して個々の半導体チップに分割し、半導
体チップと外部端子リードとをボンディングワイヤある
いはTABリードなどを介して相互に電気的に接合さ
せ、樹脂封止後に外部端子リードを加工形成させるとい
うものが一般的な技術であった。The scribe line of the ground semiconductor wafer is cut and divided into individual semiconductor chips, and the semiconductor chips and external terminal leads are electrically connected to each other via bonding wires or TAB leads. It is a general technique to process and form external terminal leads after sealing.
【0004】また、半導体ウエハ上にAuバンプなどの
突起電極を形成させるには、前記裏面研削法による半導
体ウエハ裏面を研削し、除去する前もしくは後に、Cr
などのバリア金属膜を形成して、Au電解メッキ法によ
りAuバンプを選択的に形成させていた。In order to form a bump electrode such as an Au bump on a semiconductor wafer, the back surface of the semiconductor wafer is ground by the above-described back surface grinding method, and before or after the removal, the Cr is removed.
Such a barrier metal film is formed, and an Au bump is selectively formed by an Au electrolytic plating method.
【0005】[0005]
【発明が解決しようとする課題】半導体装置は、コンピ
ュータ、ワークステーション、パーソナルコンピュー
タ、ワードプロセッサ、携帯電話、小型携帯カムコーダ
などのあらゆる機器に多量に搭載されている。近年、こ
れらの機器の小型化、軽量化の進展は著しく、また、今
後これらの機器の小型化、軽量化そして高性能化、高機
能化はさらに進むことから、これらの機器に搭載される
半導体装置の小型化、薄形化、高信頼性化への要求は、
半導体素子の高集積化、高機能化という要求と合わせて
加速度的に増大していくものと予測される。しかしなが
ら、半導体ウエハの大口径化の進展にともない従来の裏
面研削法による半導体ウエハ厚の加工には、ハンドリン
グ時もしくは研削時の半導体ウエハの破損防止という制
約により厚みを薄くすることに限界が生じ、この結果、
半導体装置に収納する半導体チップが厚くなり、半導体
装置の薄形化ひいては機器の薄形化を阻害する要因とな
っている。さらに、半導体ウエハは裏面研削時のAuバ
ンプへの荷重集中による半導体ウエハの破損を回避する
ために、Auバンプの形成を裏面研削後に行っているの
が一般的であり、Auバンプを形成した後に裏面研削を
行うことは、荷重の局部集中による半導体ウエハの破損
を回避することを考慮すると、非常な困難さを伴うおそ
れがあった。A large number of semiconductor devices are mounted on various devices such as computers, workstations, personal computers, word processors, mobile phones, and small portable camcorders. In recent years, the progress of miniaturization and weight reduction of these devices has been remarkable, and since the miniaturization, weight reduction, high performance and high function of these devices will further advance in the future, semiconductors mounted on these devices will be The demand for smaller, thinner, and more reliable equipment is
It is expected that the number of semiconductor elements will increase at an accelerating rate in accordance with the demand for higher integration and higher functionality. However, as the diameter of semiconductor wafers increases, the processing of semiconductor wafer thickness by the conventional backside grinding method has a limitation in reducing the thickness due to the restriction of preventing damage to the semiconductor wafer during handling or grinding. As a result,
A semiconductor chip accommodated in a semiconductor device becomes thicker, which is a factor that hinders the thinning of the semiconductor device and the thinning of equipment. Further, in order to avoid damage to the semiconductor wafer due to concentration of a load on the Au bump during grinding of the back surface of the semiconductor wafer, the formation of the Au bump is generally performed after the back surface grinding. Performing the back surface grinding may be very difficult in consideration of avoiding damage to the semiconductor wafer due to local concentration of load.
【0006】一方、機器内での半導体装置が占める実装
面積は、半導体素子の高集積化、高機能化にともない増
大する方向にあり、特に、従来の半導体装置の内側はボ
ンディングワイヤ、インナーリードなどの電気的導通経
路を必要とし、かつ、半導体装置の外側には接合を得る
ためのアウターリードを必要とするために本質的に実装
面積は大きくなり、さらには、樹脂厚みと半導体チップ
厚みからなる実装高さも高くなり、これらのことが半導
体装置の小型化、軽量化を阻害し、ひいては、機器の小
型化、軽量化を阻害する要因となっていた。On the other hand, the mounting area occupied by a semiconductor device in a device tends to increase with the increase in the degree of integration and function of a semiconductor element. In particular, the inside of a conventional semiconductor device includes bonding wires and inner leads. Requires an electrical conduction path, and requires an outer lead on the outside of the semiconductor device to obtain a junction, which essentially increases the mounting area, and further comprises a resin thickness and a semiconductor chip thickness. The mounting height has also been increased, and these factors have hindered miniaturization and weight reduction of the semiconductor device, and thus hindered miniaturization and weight reduction of equipment.
【0007】さらに、研削後に分割される半導体チップ
の素子面は外部からのわずかな力により簡単に損傷を受
けやすく、組立工程や実装工程における半導体チップの
ハンドリングや装置条件の設定には細心の注意が必要で
あった。Further, the element surface of the semiconductor chip which is divided after grinding is easily damaged by a small external force, and care must be taken in handling the semiconductor chip and setting device conditions in the assembling process and the mounting process. Was needed.
【0008】本発明は、半導体ウエハを裏面研削により
薄く加工しても半導体ウエハ破損が生じないようにする
ことと同時に半導体チップの素子面への損傷が生じない
ようにすること、そして、2次元的な電気的導通経路を
最小にして実装面積を小さくし、かつ、樹脂厚みおよび
半導体チップ厚みを最小にして実装高さを小さくするこ
とを目的としている。It is an object of the present invention to prevent the semiconductor wafer from being damaged even when the semiconductor wafer is thinned by grinding the back surface, and at the same time, to prevent the element surface of the semiconductor chip from being damaged. It is an object of the present invention to reduce a mounting area by minimizing an electrical conduction path and to reduce a mounting height by minimizing a resin thickness and a semiconductor chip thickness.
【0009】[0009]
【課題を解決するための手段】前述の課題を解決するた
め、本発明に係る半導体装置の製造方法は、半導体基板
に複数の半導体素子を形成する工程と、前記半導体素子
の電極に接続された突起電極群を形成する工程と、前記
突起電極群の先端部を露出して、前記半導体基板上に樹
脂膜を形成する工程と、前記半導体基板のスクライブラ
イン上の前記樹脂膜を除去するとともに、前記樹脂膜の
表面及び前記スクライブライン上の樹脂膜の側面に、選
択的に絶縁保護強化膜を形成した後に、前記半導体素子
を分割して個々の半導体装置を得る工程と、からなるこ
とを特徴とするものである。半導体基板を半導体素子単
位に分割して個々の半導体装置を得る工程においては、
半導体基板のスクライブライン上の樹脂膜を除去した
後、あるいは除去する前に、樹脂膜の表面あるいは樹脂
膜の表面及び側面に、絶縁保護強化膜を形成した後に分
割することが望ましい。In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of semiconductor elements on a semiconductor substrate and a step of forming a plurality of semiconductor elements on the semiconductor element. Forming a protruding electrode group, exposing the tip of the protruding electrode group, forming a resin film on the semiconductor substrate, and removing the resin film on a scribe line of the semiconductor substrate; A step of selectively forming an insulation protection reinforcing film on the surface of the resin film and the side surface of the resin film on the scribe line, and then dividing the semiconductor element to obtain individual semiconductor devices. It is assumed that. In the step of dividing the semiconductor substrate into semiconductor element units to obtain individual semiconductor devices,
After or before the removal of the resin film on the scribe line of the semiconductor substrate, it is desirable to divide the surface of the resin film or the surface and side surfaces of the resin film after forming an insulation protection reinforcing film.
【0010】前述の手段によれば、半導体チップに分割
する前の半導体基板を裏面研削により薄く加工しても、
半導体基板上に形成された樹脂膜が保護強化板として作
用するために、裏面研削中およびハンドリング時の半導
体基板の破損を回避できる。また同時に、組立工程や実
装工程におけるベア状態での半導体チップのハンドリン
グはなくなり、半導体チップの素子面の損傷も回避でき
る。また、半導体チップの電極上に外部接続端子となる
突起電極群を形成し、この先端部を露出して半導体チッ
プの表面を樹脂膜で封止することにより、容易に2次元
的な電気的導通経路を最小にし、かつ、樹脂厚みおよび
半導体チップ厚みを薄くさせた小型、薄型の半導体装置
の製造方法を提供することができる。According to the above-described means, even if the semiconductor substrate before being divided into the semiconductor chips is thinned by grinding the back surface,
Since the resin film formed on the semiconductor substrate acts as a protective reinforcing plate, damage to the semiconductor substrate during back surface grinding and handling can be avoided. At the same time, handling of the semiconductor chip in a bare state in the assembling process and the mounting process is eliminated, and damage to the element surface of the semiconductor chip can be avoided. Also, a protruding electrode group serving as an external connection terminal is formed on the electrode of the semiconductor chip, and the tip is exposed and the surface of the semiconductor chip is sealed with a resin film, so that two-dimensional electrical conduction can be easily performed. It is possible to provide a method for manufacturing a small and thin semiconductor device in which the number of paths is minimized and the thickness of the resin and the thickness of the semiconductor chip are reduced.
【0011】[0011]
【発明の実施の形態】本発明の第1の実施例を図1およ
び図2にもとづいて説明する。図1は本発明の第1の実
施例の半導体装置を示す斜視図であり、図2は第1の実
施例の半導体装置の製造方法について説明する断面図で
ある。図1は表面に樹脂膜3および突起電極5を形成し
た半導体ウエハ1を個々の半導体チップ2の大きさに切
断した状態を示しており、切断前において表面に樹脂膜
3を形成した状態で半導体ウエハ1の裏面を裏面研削法
を用いて鏡面状に研削を行って、半導体ウエハ1の厚み
を薄く加工した後、スクライブライン4をダイシングブ
レードを用いて切断している。この半導体ウエハ1の裏
面の研削は、裏面研削前に半導体ウエハ1の表面に樹脂
膜3を形成させることにより、樹脂膜3を保護強化板と
して機能させ、6インチ径の半導体ウエハ1であればウ
エハプロセス加工時の厚みが約0.6mmのものが裏面
研削法により0.35mm〜0.4mm程度まで半導体
ウエハ1の厚みを薄く加工でき、8インチ径の半導体ウ
エハ1であってもウエハプロセス加工時の厚みが0.7
mm程度のものが同様に0.4mm〜0.5mm程度ま
で半導体ウエハ1の厚みを薄く加工できる。このことに
より、半導体ウエハ1の厚み、すなわち、半導体ウエハ
1の大きさ如何に関わらず半導体ウエハ1の厚みを薄く
加工することができる。ここで、この樹脂膜3を形成す
る樹脂材料には、例えば低応力、高耐熱性を有するポリ
イミド樹脂を用いており、樹脂部の形成方法には一般に
よく用いられているポリイミド樹脂をスピンコーティン
グした後に熱硬化させる方法を用いている。また所定の
樹脂膜厚を得るためには、スピンコーティングを繰り返
すことにより容易に得られる。なお、半導体ウエハ1の
表面に形成される樹脂膜3の樹脂材料としては、前述の
ようなポリイミド樹脂の代わりに、低応力、低収縮性を
有するエポキシ系の樹脂を用いることも可能であり、所
定の樹脂膜3の厚みはスキージ印刷法を用いることによ
り容易に得ることができ、この結果、樹脂膜3の保護強
化板としての機能はさらに向上することになる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a perspective view illustrating a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment. FIG. 1 shows a state in which a semiconductor wafer 1 on which a resin film 3 and a bump electrode 5 are formed on the surface is cut to the size of individual semiconductor chips 2. The back surface of the wafer 1 is mirror-polished using a back surface grinding method so that the thickness of the semiconductor wafer 1 is reduced, and then the scribe lines 4 are cut using a dicing blade. The grinding of the back surface of the semiconductor wafer 1 is performed by forming the resin film 3 on the surface of the semiconductor wafer 1 before grinding the back surface so that the resin film 3 functions as a protective reinforcing plate. A wafer having a thickness of about 0.6 mm at the time of wafer processing can be thinned to about 0.35 mm to about 0.4 mm by a back surface grinding method. 0.7 when processed
In the same manner, the thickness of the semiconductor wafer 1 can be reduced to about 0.4 mm to about 0.5 mm. Thus, the thickness of the semiconductor wafer 1, that is, the thickness of the semiconductor wafer 1 can be reduced regardless of the size of the semiconductor wafer 1. Here, as a resin material for forming the resin film 3, for example, a polyimide resin having low stress and high heat resistance is used, and a polyimide resin generally used in a method of forming a resin portion is spin-coated. A method of heat curing later is used. Further, in order to obtain a predetermined resin film thickness, it can be easily obtained by repeating spin coating. In addition, as the resin material of the resin film 3 formed on the surface of the semiconductor wafer 1, an epoxy resin having low stress and low shrinkage can be used instead of the above-described polyimide resin. The predetermined thickness of the resin film 3 can be easily obtained by using the squeegee printing method. As a result, the function of the resin film 3 as a protective reinforcing plate is further improved.
【0012】本発明の第1の実施例の半導体装置の製造
方法を図2にもとづいて説明する。まず、第1の工程で
は図2Aに示すように、パターンが形成された0.6m
m程度の厚みを有する半導体ウエハ1の電極パッド上
に、クロム薄膜を介して電解メッキ法により選択的にA
uメッキを施し、円柱状の突起電極5を約100μmの
高さで形成する。つぎに、第2の工程では図2Bに示す
ように、半導体ウエハ1上に突起電極5の上端部を覆う
程度の厚みで樹脂膜3を形成する。そして、第3の工程
では図2Cに示すように、この樹脂膜3を保護強化板と
して半導体ウエハ1の裏面を裏面研削法により研削し半
導体ウエハ1の厚みを0.4mm程度となるように薄く
加工する。第4の工程では図2Dに示すように、半導体
ウエハ1の上部に設けられた樹脂膜3の上面を軽くエッ
チングし、突起電極5の上端部を露出させる。第5の工
程では図2Eに示すように、ダイシングブレードにてス
クライブライン4の樹脂膜3を削り取り、高温乾燥後、
プラズマCVD法によりシリコンナイトライド膜6を突
起電極5の上端部を除いて選択的に形成させる。最後
に、第6の工程では図2Fに示すように、ダイシング用
粘着性テープ(図示せず)にこの半導体ウエハ1を貼
り、スクライブライン4で半導体ウエハ1を完全にダイ
シングブレードにて削りとり、1個1個の半導体チップ
2に分離する。なお、スクライブライン4の樹脂膜3を
取り除くためには、第5の工程で説明したような物理的
な方法だけではなく、化学的エッチングによる方法も可
能である。一方、シリコンナイトライド膜6の形成は、
絶縁強化保護としての機能は若干低下するが、樹脂膜3
の軽いエッチング直後に行うことも可能である。A method for manufacturing a semiconductor device according to a first embodiment of the present invention will be described with reference to FIG. First, in the first step, as shown in FIG.
m selectively on the electrode pads of the semiconductor wafer 1 having a thickness of about m by electrolytic plating via a chromium thin film.
U-plating is applied to form columnar projecting electrodes 5 at a height of about 100 μm. Next, in the second step, as shown in FIG. 2B, a resin film 3 is formed on the semiconductor wafer 1 so as to cover the upper end of the bump electrode 5. In the third step, as shown in FIG. 2C, the resin film 3 is used as a protective reinforcing plate, and the back surface of the semiconductor wafer 1 is ground by a back surface grinding method so that the thickness of the semiconductor wafer 1 is reduced to about 0.4 mm. Process. In the fourth step, as shown in FIG. 2D, the upper surface of the resin film 3 provided on the upper part of the semiconductor wafer 1 is lightly etched to expose the upper end of the bump electrode 5. In the fifth step, as shown in FIG. 2E, the resin film 3 of the scribe line 4 is scraped off with a dicing blade, dried at a high temperature,
A silicon nitride film 6 is selectively formed by a plasma CVD method except for the upper end of the bump electrode 5. Finally, in a sixth step, as shown in FIG. 2F, the semiconductor wafer 1 is pasted on an adhesive tape for dicing (not shown), and the semiconductor wafer 1 is completely scraped off with a dicing blade along a scribe line 4, Each semiconductor chip 2 is separated. In addition, in order to remove the resin film 3 of the scribe line 4, not only the physical method described in the fifth step, but also a method by chemical etching is possible. On the other hand, the formation of the silicon nitride film 6
Although the function as insulation protection is slightly reduced, the resin film 3
Can be performed immediately after light etching.
【0013】さらに、図1において前述のように個々の
半導体チップ2の大きさに切り出された半導体装置は、
既に説明した通り裏面研削を施されて薄くなった半導体
チップ2の上面に樹脂膜3が形成されており、この樹脂
膜3の上面からは半導体チップ2のパッド電極に対して
垂直に形成された円柱状の突起電極5の先端部が突出し
ており、その突起電極5は電解メッキ法を用いて形成さ
れたAu電極であり、その高さは80μm〜100μm
である。ただし、この突起電極5の形状は、円柱状であ
っても良いし、角柱状であっても良い。一方、この突起
電極5の突出量は、突起電極5の高さ、樹脂膜3の厚
み、そして、接合安定性から決定され、第1の実施例で
は20μm程度を突出させている。また、第1の実施例
では、半導体チップ2の側面がダイシングされた状態で
露出しており、同様にその裏面が研削された状態で露出
している。さらに、図1では特に図示してはいないが、
これら半導体チップ2の側面、裏面および突起電極5表
面を除いた樹脂膜3最表面には半導体装置としての信頼
性を高めるためのシリコンナイトライド膜6がプラズマ
CVD法により200℃〜250℃の比較的低温で1μ
m程度形成され、樹脂膜3への水分吸湿による半導体装
置の信頼性低下を防ぐ絶縁保護強化膜としている。Further, as shown in FIG. 1, the semiconductor device cut out to the size of each semiconductor chip 2 as described above,
As described above, the resin film 3 is formed on the upper surface of the semiconductor chip 2 which has been thinned by the back surface grinding, and is formed perpendicularly to the pad electrode of the semiconductor chip 2 from the upper surface of the resin film 3. The tip of the cylindrical protruding electrode 5 protrudes, and the protruding electrode 5 is an Au electrode formed by using an electrolytic plating method, and has a height of 80 μm to 100 μm.
It is. However, the shape of the projecting electrode 5 may be cylindrical or prismatic. On the other hand, the amount of protrusion of the protruding electrode 5 is determined by the height of the protruding electrode 5, the thickness of the resin film 3, and the bonding stability. In the first embodiment, the amount of protrusion is about 20 μm. In the first embodiment, the side surface of the semiconductor chip 2 is exposed in a diced state, and similarly, the back surface is exposed in a ground state. Further, although not specifically shown in FIG. 1,
A silicon nitride film 6 for improving the reliability as a semiconductor device is formed on the outermost surface of the resin film 3 excluding the side and back surfaces of the semiconductor chip 2 and the surface of the bump electrode 5 by a plasma CVD method at a temperature of 200 ° C. to 250 ° C. 1μ at low temperature
m, and serves as an insulation protection reinforced film for preventing a decrease in the reliability of the semiconductor device due to moisture absorption into the resin film 3.
【0014】本発明の第1の実施例の半導体装置を種々
の実装形態に適合できることを示すプリント配線板への
接合方法を図3にもとづいて説明する。図3は、図1に
示した本発明の第1の実施例の半導体装置のプリント配
線板への接合方法を示す断面図である。図3Aにしめす
ように、フットパターン8が形成されたプリント配線板
7へ半導体装置が直接フェイスダウンボンディングされ
ており、フットパターン8上に予め設けられたAuバン
プ9と半導体チップ2の突起電極5が熱圧着により合金
接合されている。またこの合金接合部を含めた半導体装
置の信頼性を高めるために、半導体装置の周縁部をエポ
キシ系の封止樹脂10でポッティング法により封止して
いる。図3Bに示すように、図3Aに示した半導体装置
の裏面に高熱伝導性のシリコン系接着剤11を塗布し、
放熱板12となるAl合金板を貼付け、半導体装置から
の放熱性を積極的に向上させている。図3Cは、半導体
装置に形成された突起電極5のピッチが微細な場合につ
いての実施例であり、通常のテープキャリア方式のTA
Bテープと半導体チップ2との接合方法と全く同一な方
法で、第1の実施例の半導体装置とTABテープ13と
を突起電極5を介して接合させ、そして、このTABテ
ープ13のリードの終端部とプリント配線板7上のフッ
トパターン8とを半田接合法を用いて接合させ、この半
田接合部を含む半導体装置の周縁部を図3A,図3Bと
同様にエポキシ系の封止樹脂10でポッティング法によ
り封止させた例である。図3Dは、図3Cで説明した半
導体装置裏面に高熱伝導性のシリコン系接着剤11を塗
布し、放熱板12となるAl合金板を貼り付け、半導体
装置からの放熱性を向上させている。A method of joining the semiconductor device of the first embodiment of the present invention to a printed wiring board showing that it can be adapted to various mounting forms will be described with reference to FIG. FIG. 3 is a sectional view showing a method of joining the semiconductor device of the first embodiment of the present invention shown in FIG. 1 to a printed wiring board. As shown in FIG. 3A, the semiconductor device is directly face-down bonded to the printed wiring board 7 on which the foot pattern 8 is formed, and the Au bump 9 previously provided on the foot pattern 8 and the projection electrode 5 of the semiconductor chip 2 Are joined by thermocompression bonding. Further, in order to enhance the reliability of the semiconductor device including the alloy joint, the peripheral portion of the semiconductor device is sealed with an epoxy-based sealing resin 10 by a potting method. As shown in FIG. 3B, a silicon adhesive 11 having high thermal conductivity is applied to the back surface of the semiconductor device shown in FIG. 3A,
An Al alloy plate serving as the heat radiating plate 12 is adhered, and heat radiation from the semiconductor device is positively improved. FIG. 3C shows an example in which the pitch of the protruding electrodes 5 formed on the semiconductor device is fine.
The semiconductor device of the first embodiment and the TAB tape 13 are joined via the protruding electrodes 5 in exactly the same manner as the method of joining the B tape and the semiconductor chip 2, and the ends of the leads of the TAB tape 13 are terminated. The portion and the foot pattern 8 on the printed wiring board 7 are joined using a solder joining method, and the peripheral portion of the semiconductor device including the solder joint is covered with an epoxy-based sealing resin 10 as in FIGS. 3A and 3B. This is an example of sealing by a potting method. In FIG. 3D, a silicon-based adhesive 11 having high thermal conductivity is applied to the back surface of the semiconductor device described with reference to FIG. 3C, and an Al alloy plate serving as a heat radiating plate 12 is adhered to improve heat radiation from the semiconductor device.
【0015】次に、本発明の第2の実施例を図4にもと
づいて説明する。図4Aは、本発明の第2の実施例の半
導体装置を示す斜視図であり、図4Bは図4Aの側面図
を示している。図4A、図4Bに示すように、裏面研削
により薄く加工された半導体チップ2上に2つの異なる
高さを有した突起電極5が千鳥状に半導体チップ2の周
囲に形成されている。そして、半導体チップ2の内側に
形成された突起電極5の配列には高い突起電極5が、そ
の外側に形成された突起電極5の配列には低い突起電極
5が形成され、突出量が20μm前後となるように樹脂
膜3が段状に形成されている。このように半導体装置を
構成したことにより、半導体チップ2上の突起電極5が
微細ピッチとなっても、隣接リード間のショートが生じ
にくいTABボンディングが容易に行えるようになる。Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 4A is a perspective view showing a semiconductor device according to a second embodiment of the present invention, and FIG. 4B is a side view of FIG. 4A. As shown in FIG. 4A and FIG. 4B, projecting electrodes 5 having two different heights are formed around the semiconductor chip 2 in a staggered manner on the semiconductor chip 2 which is thinly processed by the back surface grinding. A high protruding electrode 5 is formed in the array of the protruding electrodes 5 formed inside the semiconductor chip 2, and a low protruding electrode 5 is formed in the array of the protruding electrodes 5 formed outside the semiconductor chip 2. The protruding amount is about 20 μm. The resin film 3 is formed in a step shape so that By configuring the semiconductor device in this way, even if the protruding electrodes 5 on the semiconductor chip 2 have a fine pitch, it is possible to easily perform TAB bonding in which a short circuit between adjacent leads hardly occurs.
【0016】つぎに本発明の第3の実施例および第4の
実施例を、図5および図6にもとづいて説明する。図5
および図6は、それぞれ第3の実施例および第4の実施
例の半導体装置を示す斜視図である。図5に示す第3の
実施例は、半導体装置に突出させた突起電極5の周囲部
の樹脂膜3に凹部14を形成させてあり、この凹部14
には、図3Aに示す突起電極5とフットパターン8との
接合材料にAuバンプ9の代わりに半田を用いたとき
に、隣接した突起電極5間での半田ブリッジによるショ
ートを防ぐための半田だまりの役目を持たせている。一
方、図6に示す第4の実施例は、半導体装置に突設させ
た突起電極5の上端部と円柱側部のうちの外側部を露出
させた例であり、プリント配線板7に凹状の半導体装置
収納部(図示せず)と前記半導体装置収納部の側面に縦
状の導体パターン(図示せず)と底面に導体パターンを
連続して設け、第4の実施例に示した半導体装置をプリ
ント配線板7の半導体装置収納部に収納し、半導体装置
の突起電極5の上端部と円柱側部とを前記導体パターン
と半田接合させるようにして半田接合時の信頼性向上を
はかると同時に、プリント配線板7への実装時の高さの
低減をはかっている。Next, a third embodiment and a fourth embodiment of the present invention will be described with reference to FIGS. FIG.
And FIG. 6 are perspective views showing the semiconductor devices of the third embodiment and the fourth embodiment, respectively. In the third embodiment shown in FIG. 5, a recess 14 is formed in the resin film 3 around the protruding electrode 5 protruding from the semiconductor device.
3A, when solder is used instead of the Au bump 9 as a bonding material between the bump electrode 5 and the foot pattern 8 shown in FIG. 3A, a solder pool for preventing a short circuit due to a solder bridge between the adjacent bump electrodes 5 Has the role of. On the other hand, the fourth embodiment shown in FIG. 6 is an example in which the upper end portion of the protruding electrode 5 protruding from the semiconductor device and the outer side portion among the cylindrical side portions are exposed. The semiconductor device accommodating portion (not shown), the vertical conductor pattern (not shown) on the side surface of the semiconductor device accommodating portion, and the conductor pattern on the bottom surface are continuously provided. It is housed in the semiconductor device housing portion of the printed wiring board 7, and the upper end of the protruding electrode 5 of the semiconductor device and the cylindrical side are soldered to the conductor pattern so as to improve the reliability at the time of soldering. The height at the time of mounting on the printed wiring board 7 is reduced.
【0017】以上説明してきたように、本発明の半導体
装置の製造方法によれば、半導体チップ2の表面に樹脂
膜3を形成することにより、半導体ウエハ1の破損、半
導体チップ2の素子面の損傷を生じないようにすること
ができる。また、プリント配線板7への実装時の2次元
的な電気導通経路を最小にすると同時に実装高さを小さ
くすることができる。As described above, according to the method for manufacturing a semiconductor device of the present invention, the resin film 3 is formed on the surface of the semiconductor chip 2, thereby damaging the semiconductor wafer 1 and reducing the element surface of the semiconductor chip 2. Damage can be prevented. In addition, it is possible to minimize the two-dimensional electric conduction path at the time of mounting on the printed wiring board 7 and at the same time, to reduce the mounting height.
【0018】[0018]
【発明の効果】本発明に係る半導体装置の製造方法によ
ると、半導体チップに分割前の半導体基板を裏面研削に
より薄く加工しても、半導体基板上に形成された樹脂膜
が保護強化膜として機能するため、裏面研削中及びハン
ドリング時の半導体基板の破損を確実に回避することが
できる。また同時に、組立工程や実装工程におけるベア
状態での半導体チップのハンドリングはなくなるため、
半導体チップ素子面の損傷をも確実に回避することがで
きる。更に、半導体チップの電極上に外部接続端子とな
る突起電極群を形成し、少なくともその先端部を露出し
て半導体チップの表面を樹脂膜で封止するようにしてい
るため、2次元的な電気的導通経路を最小にし、かつ、
樹脂厚み及び半導体チップ厚みを薄くした高い信頼性を
有する小型かつ薄型の半導体装置を製造することができ
る。According to the method of manufacturing a semiconductor device of the present invention, the resin film formed on the semiconductor substrate functions as a protective enhancement film even if the semiconductor substrate before being divided into semiconductor chips is thinned by back grinding. Therefore, damage to the semiconductor substrate during back surface grinding and handling can be reliably avoided. At the same time, handling of semiconductor chips in a bare state in the assembly process and the mounting process is eliminated,
Damage to the semiconductor chip element surface can also be reliably avoided. Further, a protruding electrode group serving as an external connection terminal is formed on the electrode of the semiconductor chip, and at least the tip is exposed to seal the surface of the semiconductor chip with a resin film. The electrical conduction path is minimized, and
It is possible to manufacture a small and thin semiconductor device having high reliability by reducing the thickness of the resin and the thickness of the semiconductor chip.
【図1】 本発明の第1の実施例の半導体装置を示す斜
視図。FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present invention.
【図2】 本発明の第1の実施例の半導体装置の製造方
法について説明する断面図。FIG. 2 is a sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図3】 本発明の第1の実施例の半導体装置のプリン
ト配線板への接合方法を示す断面図。FIG. 3 is a cross-sectional view illustrating a method of joining the semiconductor device to the printed wiring board according to the first embodiment of the present invention.
【図4】 本発明の第2の実施例の半導体装置を示す斜
視図および断面図。FIG. 4 is a perspective view and a sectional view showing a semiconductor device according to a second embodiment of the present invention.
【図5】 本発明の第3の実施例の半導体装置を示す斜
視図。FIG. 5 is a perspective view showing a semiconductor device according to a third embodiment of the present invention.
【図6】 本発明の第4の実施例の半導体装置を示す斜
視図。FIG. 6 is a perspective view showing a semiconductor device according to a fourth embodiment of the present invention.
1 半導体ウエハ 2 半導体チップ 3 樹脂膜 4 スクライブライン 5 突起電極 6 シリコンナイトライド膜 7 プリント配線板 8 フットパターン 9 Auバンプ 10 封止樹脂 11 シリコン系接着剤 12 放熱板 13 TABテープ DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Semiconductor chip 3 Resin film 4 Scribe line 5 Projection electrode 6 Silicon nitride film 7 Printed wiring board 8 Foot pattern 9 Au bump 10 Sealing resin 11 Silicon adhesive 12 Heat sink 13 TAB tape
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭62−136049(JP,A) 特開 平3−101128(JP,A) 特開 昭54−45570(JP,A) 特開 平3−73534(JP,A) 特開 平2−189925(JP,A) 特開 平2−125633(JP,A) 特開 昭64−12553(JP,A) 特開 平4−266038(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/301 H01L 21/56 H01L 21/60 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-136049 (JP, A) JP-A-3-101128 (JP, A) JP-A-54-45570 (JP, A) JP-A-3- 73534 (JP, A) JP-A-2-189925 (JP, A) JP-A-2-125633 (JP, A) JP-A 64-12553 (JP, A) JP-A-4-266038 (JP, A) (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/301 H01L 21/56 H01L 21/60
Claims (1)
る工程と、 前記半導体素子の電極に接続された突起電極群を形成す
る工程と、 前記突起電極群の先端部を露出して、前記半導体基板上
に樹脂膜を形成する工程と、 前記半導体基板のスクライブライン上の前記樹脂膜を除
去するとともに、前記樹脂膜の表面及び前記スクライブ
ライン上の樹脂膜の側面に、選択的に絶縁保護強化膜を
形成した後に、前記半導体素子を分割して個々の半導体
装置を得る工程と、 からなることを特徴とする半導体装置の製造方法。A step of forming a plurality of semiconductor elements on a semiconductor substrate; a step of forming a protruding electrode group connected to electrodes of the semiconductor element; Forming a resin film on the substrate; removing the resin film on a scribe line of the semiconductor substrate; and selectively strengthening insulation protection on a surface of the resin film and a side surface of the resin film on the scribe line. Forming a film and then dividing the semiconductor element to obtain individual semiconductor devices. A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23319798A JP3189799B2 (en) | 1991-08-23 | 1998-08-19 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23319798A JP3189799B2 (en) | 1991-08-23 | 1998-08-19 | Method for manufacturing semiconductor device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP03211207A Division JP3128878B2 (en) | 1991-08-23 | 1991-08-23 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH11150090A JPH11150090A (en) | 1999-06-02 |
JP3189799B2 true JP3189799B2 (en) | 2001-07-16 |
Family
ID=16951279
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23319798A Expired - Fee Related JP3189799B2 (en) | 1991-08-23 | 1998-08-19 | Method for manufacturing semiconductor device |
Country Status (1)
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JP (1) | JP3189799B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102637589A (en) * | 2011-02-15 | 2012-08-15 | 日东电工株式会社 | Method of manufacturing semiconductor device |
US9279064B2 (en) | 2011-02-15 | 2016-03-08 | Nitto Denko Corporation | Manufacturing semiconductor device with film for forming protective layer |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3339838B2 (en) * | 1999-06-07 | 2002-10-28 | ローム株式会社 | Semiconductor device and method of manufacturing the same |
WO2001015223A1 (en) * | 1999-08-23 | 2001-03-01 | Rohm Co., Ltd. | Semiconductor device and method of manufacture thereof |
DE10023539B4 (en) * | 2000-05-13 | 2009-04-09 | Micronas Gmbh | Method for producing a component |
JP4856328B2 (en) | 2001-07-13 | 2012-01-18 | ローム株式会社 | Manufacturing method of semiconductor device |
JP3829325B2 (en) | 2002-02-07 | 2006-10-04 | 日本電気株式会社 | Semiconductor element, manufacturing method thereof, and manufacturing method of semiconductor device |
US7358618B2 (en) | 2002-07-15 | 2008-04-15 | Rohm Co., Ltd. | Semiconductor device and manufacturing method thereof |
JP2005191508A (en) | 2003-12-05 | 2005-07-14 | Rohm Co Ltd | Semiconductor device and manufacturing method for the same |
KR100884192B1 (en) | 2007-07-20 | 2009-02-18 | 앰코 테크놀로지 코리아 주식회사 | Manufacturing method of semiconductor package |
CN102473653B (en) | 2010-02-01 | 2016-05-04 | 丰田自动车株式会社 | The manufacture method of semiconductor device and semiconductor device |
WO2015041050A1 (en) * | 2013-09-17 | 2015-03-26 | 株式会社村田製作所 | Composite module |
US9397055B2 (en) * | 2014-05-29 | 2016-07-19 | Infineon Technologies Ag | Processing of thick metal pads |
JP2016174102A (en) * | 2015-03-17 | 2016-09-29 | 株式会社東芝 | Semiconductor manufacturing method and laminated body |
JP6558541B2 (en) * | 2015-12-09 | 2019-08-14 | 株式会社ディスコ | Wafer processing method |
-
1998
- 1998-08-19 JP JP23319798A patent/JP3189799B2/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102637589A (en) * | 2011-02-15 | 2012-08-15 | 日东电工株式会社 | Method of manufacturing semiconductor device |
US8518745B2 (en) | 2011-02-15 | 2013-08-27 | Nitto Denko Corporation | Method of manufacturing semiconductor device having a bumped wafer and protective layer |
KR101345984B1 (en) * | 2011-02-15 | 2014-01-02 | 닛토덴코 가부시키가이샤 | Method for manufacturing semiconductor device |
US9279064B2 (en) | 2011-02-15 | 2016-03-08 | Nitto Denko Corporation | Manufacturing semiconductor device with film for forming protective layer |
Also Published As
Publication number | Publication date |
---|---|
JPH11150090A (en) | 1999-06-02 |
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