JP3166912B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a wiring using copper (Cu) as a conductive material.

[0002]

2. Description of the Related Art Devices have been rapidly miniaturized in order to improve the performance of LSIs. However, as the wiring width becomes narrower, the wiring resistance increases, so that deterioration in speed due to wiring delay cannot be ignored. Is coming. In order to reduce the wiring resistance, it has been studied to use Cu having lower resistance than the conventional alloy containing Al as a main component as the wiring metal (although the volume resistivity of Al is 2.7 × 10 ⁻⁶ ). On the other hand, Cu
1.7 × 10 ⁻⁶ ). As a method of forming wiring using a material containing Cu as a main component, A
a method of patterning by photolithography in the same manner as in the case of using
A method called a “scene” method for embedding a Cu wiring in a wiring groove is known, but the latter method is mainly adopted because Cu is a material that is difficult to etch.

A method of forming a wiring by the damascene method is as follows. SiO 2 is formed on the semiconductor substrate on which the elements are formed.
_{2. An} interlayer insulating film made of an inorganic material such as boro-phospho-silicate glass (BPSG) is formed, and a wiring groove having a predetermined depth is formed by photolithography and dry etching. Next, after Cu is deposited so as to sufficiently fill the wiring groove, CMP (chemical mechanical
The Cu conductive layer on the interlayer insulating film is removed by polishing) to form a Cu wiring in the wiring groove.

[0004]

When forming a Cu wiring by the above-described damascene method, it is necessary to form an etching stopper in an interlayer insulating film in order to form a wiring groove with high depth accuracy ( For example, see JP-A-8-17918. Thus, the insulating film usually used as an etching stopper is a silicon nitride film, but this material has a relative dielectric constant of 4.7, which is larger than 3.8 of a silicon oxide film. In recent years, wiring density has become increasingly denser as wiring becomes finer. If an insulating film made of a high dielectric constant material is provided in an interlayer insulating film, the stray capacitance increases, resulting in an adverse effect of wiring delay. Can no longer be ignored and Cu
, The effect of reducing the wiring resistance is diminished.

On the other hand, when patterning a Cu conductive layer by a photolithography method, there is a problem that Cu is a material which is not easily etched and Cu is a material which is easily corroded. In other words, in the case of Al, even if O ₂ or the like adheres to the surface, if an Al ₂ O ₃ film is formed on the surface, it acts as a protective film, so that oxidation of the internal Al is prevented. However, such a protective film is not formed, and the halogen adhering to the surface diffuses into the inside, so that the presence of the surface adhering causes deterioration of the wiring. In the case of Cu, in an oxidizing atmosphere (high temperature + oxygen, O ₂ plasma, ozone), oxidation proceeds to the inside of the wiring to cause an increase in wiring resistance. As described above, Cu is a material that is difficult to be etched, and therefore, it is necessary to perform RIE with high energy in order to perform highly anisotropic etching. However, during the etching process, the photoresist film is deteriorated. Therefore, it is necessary to perform ashing to remove the resist film. O _{2 for} this ashing
Oxidizes the Cu wiring to increase the wiring resistance. Also, R
Reaction products and halogens generated during the IE process adhere to the side surfaces of the Cu wiring, causing deterioration of the Cu wiring and impairing long-term reliability. Therefore, an object of the present invention is to solve the above-described problems of the conventional technology, and an object of the present invention is to easily form a fine pattern Cu wiring having a low stray capacitance and a high long-term stability with a relatively small number of steps. That is, it is possible to form it.

[0006]

According to the present invention, there is provided a semiconductor device comprising: (1) depositing an interlayer insulating film on a semiconductor substrate and selectively removing the interlayer insulating film; Forming an opening exposing the surface of the diffusion layer and / or lower wiring layer on the surface of the semiconductor substrate; (2) forming an organic compound film on the interlayer insulating film; and (3) forming the organic compound film. Forming a wiring groove penetrating through the organic compound film; (4) applying a Cu wiring material layer over the entire surface so as to completely fill the wiring groove and the opening; Forming a Cu wiring and a conductive plug simultaneously by removing the Cu wiring material layer on the organic compound film so that the organic compound film and the Cu wiring material layer have substantially the same height; (6) ) Removing the organic compound film The method of manufacturing a semiconductor device characterized by comprising the steps, a, is provided. In order to achieve the above object, according to the present invention, (1 ′) an interlayer insulating film is deposited on a semiconductor substrate, and the interlayer insulating film is selectively removed to form a diffusion layer on the surface of the semiconductor substrate. And / or forming an opening exposing the surface of the lower wiring layer; (2 ') filling the inside of the opening with a conductive material to form a conductive plug in the opening; (3') A step of forming an organic compound film on the interlayer insulating film; (4 ') a step of forming a wiring groove penetrating the organic compound film in the organic compound film; C on the entire surface to be embedded
(6 ') removing the Cu wiring material layer on the organic compound film so that the heights of the organic compound film and the Cu wiring material layer are substantially the same. And (7 ') a step of removing the organic compound film.

[0007]

According to the manufacturing method of the present invention described above, since it is not necessary to pattern the Cu conductive layer by RIE having high energy and high anisotropy, it is possible to prevent the deterioration of the photoresist and the like. It is possible to prevent the Cu conductive layer from contacting an oxidizing atmosphere such as the above, and it is possible to prevent oxygen from attaching to the Cu wiring. Further, since the side surface of the Cu wiring is not exposed during patterning of the Cu conductive layer, it is possible to prevent reaction products and halogens from adhering to the side surface of the Cu wiring.
Therefore, it is possible to prevent oxidation and corrosion of the Cu wiring, prevent an increase in wiring resistance, and secure reliability. Further, since the wiring can be formed according to the groove pattern of the organic compound film, a highly accurate wiring pattern can be realized.

[0008]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view in the order of steps for describing an embodiment of the present invention. FIG. 1 (a)
As shown in FIG. 1, for example, a lower-layer metal wiring 2 is formed on a first interlayer insulating film 1 formed on a semiconductor substrate (not shown), and a second interlayer insulating film 3 is formed thereon. Selectively remove the two-layer insulating film by etching to remove the lower metal wiring 2
A via hole exposing the surface of the substrate. Further, a contact hole for exposing the surface of the diffusion layer formed on the semiconductor substrate is opened as needed.

[0009] Then, a conductive plug 4 is formed in the via hole by depositing a conductive material such as tungsten (W) and performing etch back (or CMP). At this time, a conductive plug is also formed in the contact hole as needed. However, the step of forming the conductive plug can be omitted, and the via hole (contact hole) can be filled with the wiring material at the same time as forming the upper layer wiring. Next, an organic compound film 5 is formed on the second interlayer insulating film 3, and a wiring groove 5a is formed in the organic compound film 5 in a desired wiring pattern shape. The wiring groove 5a is formed so as to penetrate the organic compound film 5. When the organic compound film is formed of a photoresist or a photosensitive heat-resistant resin, the wiring groove 5a can be formed by exposure and development. Then, preferably after exposure and development, the photoresist is subjected to a heat resistance treatment such as ultraviolet irradiation. The organic compound film 5 is made of polyimide to which no photosensitivity is given,
It can also be formed from a heat-resistant resin such as polyamide or benzocyclobutene. In this case, a photoresist film having an opening of a wiring groove pattern is formed on the organic compound film, and the organic compound film is etched by a dry etching method or the like using the photoresist film as a mask to form a wiring groove.

Next, as shown in FIG.
Is deposited to a thickness that completely fills the wiring groove 5a to form a wiring material layer 6A. When the conductive plug 4 is not formed in the via hole formed in the second interlayer insulating film 3, the inside of the via hole (and, if necessary, the contact hole) is also filled with the Cu layer (6A). Wiring material layer 6
Under the layer A, a base layer made of another material can be formed as a barrier layer or an adhesion layer. For example, Ta, Ti
An underlayer made of N, Ti / TiN, WSi, or the like can be formed thin (5 to 60 nm). These underlayers can be formed by a sputtering method, a reactive sputtering method, or the like. Cu can be deposited by a sputtering method, a CVD method, or an electrolytic plating method. In the case of forming by an electroplating method, it is preferable that a thin Cu layer is formed by a thin film technique such as a sputtering method, and then a thick Cu is electroplated thereon.

Next, as shown in FIG. 1C, the Cu layer (6A) deposited on the organic compound film 5 is removed to form the upper metal wiring 6 in the wiring groove. As a method for removing the Cu layer on the organic compound film 5, CMP (chemical mecha) is used.
nical polishing) method, RI such as ICP type (induction coil type) or ECR type (electron cyclotron resonance type)
E method or ion milling method can be adopted. Regardless of the removal method, care is taken so that the photoresist film and the like are not deteriorated. Next, as shown in FIG. 1D, the organic compound film 5 is removed by a wet method. Thereafter, if necessary, an interlayer insulating film and an upper layer wiring are further formed in an upper layer. When the upper wiring is not formed, a passivation film is formed on the upper metal wiring 6 and the second interlayer insulating film 3.

[0012]

Next, an embodiment of the present invention will be described in detail with reference to the drawings. [First Embodiment] FIGS. 2 (a) to 2 (d), 3 (e) to 3 (e)
(H) is sectional drawing of the order of a process which shows 1st Example of this invention. First, as shown in FIG. 2A, a lower metal wiring 102 is formed on a first interlayer insulating film made of an inorganic material such as SiO ₂ or BPSG formed on a semiconductor substrate on which a semiconductor element has been formed. I do. Next, as shown in FIG. 2B, the metal wiring is covered with a second interlayer insulating film 103 made of an inorganic material. Subsequently, a photoresist is applied, and exposure and development are performed to form a photoresist film 104 having an opening of a via hole pattern. Next, the second interlayer insulating film is selectively etched using the photoresist film 104 as a mask to open a via hole 103a, and the photoresist film 104 is peeled off. Here, etching is performed using a parallel plate narrow gap type RIE apparatus,
A mixed gas of C ₄ F ₈ / CO / Ar / O ₂ was used as an etching gas.

Next, as shown in FIG. 3E, a photoresist is applied, exposed and developed to form a photoresist film 105 having a wiring groove 105a having a desired wiring pattern shape. After pattern formation, the photoresist is irradiated with UV to improve the heat resistance. Then, FIG.
As shown in (f), Ta is sputtered to a thickness of 30 nm.
An underlayer 106a is formed to a thickness of about 50 nm, Cu is continuously deposited to a thickness of about 50 nm, and then Cu is deposited by an electrolytic plating method so as to completely fill the via hole 103a and the wiring groove 105a. To form a Cu layer 106b. The film formation temperature during sputtering is 150 ° C., and the photoresist 105 does not undergo thermal deterioration during film formation.
Subsequently, as shown in FIG.
The upper layer metal wiring 106 is formed by removing the Cu layer 106b and the underlying metal layer 106a on the layer 05 by dry etching. At this time, an ICP plasma etching apparatus was used as an etching apparatus, and Cl ₂ was used as an etching gas.
Etching was performed isotropically at an electrode temperature of 200 ° C. Finally, as shown in FIG. 3 (h), the photoresist film 105 between the wirings is stripped with a resist stripper. By suppressing the incident ion energy at the time of etch back (low bias power), the quality of the photoresist film 105 at the time of etch back can be prevented, and the photoresist film 105 can be separated without performing ashing. .

[Second Embodiment] FIGS. 4 (a) to 4 (d)
It is sectional drawing of a process order which shows the 2nd Example of this invention. In this embodiment, since the step shown in FIG. 2D of the first embodiment is performed as it is, the description up to the step shown in FIG. 2D is omitted. Thereafter, as shown in FIG. 4A, a 1.3 μm-thick polyimide film 107 is formed on the second interlayer insulating film 103, and a photolithography method and a dry etching method using O ₂ as an etching gas are performed. The polyimide in the wiring formation region is removed by the
7a is formed. Next, a Ti film and a TiN film were formed to a thickness of 20 nm and 30 nm by sputtering and reactive sputtering, respectively.
The underlayer metal layer 106a is formed to a thickness of 50 nm, and then Cu is sputtered to a thickness of 50 nm. Thereafter, Cu is deposited by an electrolytic plating method to form a Cu layer 106b.

Next, as shown in FIG. 4C, the Cu layer 10 on the polyimide film 107 is formed by ion milling.
6b, the underlying metal layer 106a is removed to remove the upper metal wiring 10
6 is formed. Thereafter, as shown in FIG. 4D, the polyimide film 107 is removed by etching by a wet method, and the step of forming the upper wiring is completed.

Third Embodiment FIGS. 5A to 5C and FIGS. 6D to 6G are sectional views showing a third embodiment of the present invention in the order of steps. In the present embodiment, the steps up to the step shown in FIG.
The description up to the step shown in FIG. FIG.
After processing into the state shown in FIG. 5A, as shown in FIG. 5B, a 30-nm-thick TiN film is formed by sputtering to form a barrier metal layer 104a, and then WF ₆
Tungsten (W) is deposited by a plasma CVD method using as a source gas to form a tungsten film 104b. Next, as shown in FIG.
mechanical polishing), the second interlayer insulating film 1
03 on tungsten film 103b, barrier metal layer 10
4a is polished and removed to form a conductive plug 104.

Next, as shown in FIG. 6D, a photoresist is applied, exposed and developed to form a photoresist film 105 having a wiring groove 105a having a desired wiring pattern shape. After pattern formation, the photoresist is irradiated with UV to improve the heat resistance. Then, FIG.
As shown in (e), TiN is deposited to a thickness of about 30 nm by a reactive sputtering method to form an underlayer 106a, and Cu is continuously deposited to a thickness of about 50 nm.
Cu is deposited by electrolytic plating so as to completely fill the wiring groove 105a to form a Cu layer 106b. The film formation temperature at the time of sputtering is 150 ° C., and the photoresist film 105 does not thermally deteriorate during the film formation. Subsequently, as shown in FIG.
The upper Cu layer 106b and the underlying metal layer 106a are removed by the CMP method to form the upper metal wiring 106. Finally,
As shown in FIG. 6G, the photoresist film 105 between the wirings is stripped by a resist stripper. Since the photoresist film 105 is not deteriorated during the CMP, the photoresist film 105 can be removed without performing ashing.

[0018]

As described above, in the method of manufacturing a semiconductor device according to the present invention, a wiring groove is formed in an organic compound film, a Cu layer filling the wiring groove is formed, and then the Cu layer on the organic compound film is removed. Since the removal is performed to further remove the organic compound film, a fine and highly reliable long-term Cu wiring can be formed with high precision. Further, since it is not necessary to form a high-dielectric-constant film such as a silicon nitride film on the interlayer insulating film, the stray capacitance can be suppressed even when the density of the wiring is increased. Further, according to the embodiment in which the organic compound film is formed of a photosensitive material such as a photoresist, a Cu wiring can be formed with a smaller number of steps.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view in a process order for describing an embodiment of the present invention.

FIG. 2 is a part of a process order sectional view for explaining the first embodiment of the present invention.

FIG. 3 is a view for explaining a first embodiment of the present invention;
Sectional sectional view in a step following the step.

FIG. 4 is a process order sectional view for explaining a second embodiment of the present invention.

FIG. 5 is a part of a process order sectional view for explaining a third embodiment of the present invention.

FIG. 6 is a view for explaining a third embodiment of the present invention;
Sectional sectional view in a step following the step.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 101 First interlayer insulating film 2, 102 Lower metal wiring 3, 103 Second interlayer insulating film 103a Via hole 4, 104 Conductive plug 104a Barrier metal layer 104b Tungsten film 5 Organic compound film 105 Photoresist film 5a, 105a, 107a Wiring groove 6, 106 Upper metal wiring 6A Wiring material layer 106a Base metal layer 106b Cu layer 107 Polyimide film

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205-21/3213 H01L 21/768

Claims (10)

(57) [Claims] 1. An interlayer insulating film is deposited on a semiconductor substrate.
Then, the interlayer insulating film is selectively removed, and the semiconductor substrate is removed.
Exposed surface of diffusion layer and / or lower wiring layer on board surface
Forming an opening to be formed; (2) forming an organic compound film on the interlayer insulating film; and (3) forming a wiring groove through the organic compound film in the organic compound film. (4) a step of depositing a Cu wiring material layer on the entire surface so as to completely fill the wiring groove and the opening; and (5) the height of the organic compound film and the Cu wiring material layer is reduced.
By removing the Cu wiring material layer on the organic compound film so as to be substantially the same, the Cu wiring and the conductive plastic are removed.
Forming a semiconductor device simultaneously ; and (6) removing the organic compound film. 2. An interlayer insulating film is deposited on a semiconductor substrate, and the interlayer insulating film is selectively removed to expose a surface of a diffusion layer and / or a lower wiring layer on a surface of the semiconductor substrate. Forming an opening; (2 ') filling the inside of the opening with a conductive material to form a conductive plug in the opening; and (3') forming an organic compound film on the interlayer insulating film. (4 ') forming a wiring groove through the organic compound film in the organic compound film; and (5') forming C on the entire surface so as to completely fill the wiring groove.
(6 ') removing the Cu wiring material layer on the organic compound film so that the heights of the organic compound film and the Cu wiring material layer are substantially the same. And (7 ') a step of removing the organic compound film. 3. The method according to claim 1, wherein the organic compound film is formed using a heat-resistant resin. 4. The method according to claim 1, wherein the organic compound film is formed using a photoresist. 5. The method according to claim 5, wherein the step (3) is performed before the step (4), or after the step (4 ′) and prior to the step (5 ′). The method for manufacturing a semiconductor device according to claim 4, wherein a treatment for improving heat resistance of the organic compound film is added by light irradiation. 6. The step (4) or the step (5 ′) is a step of forming a thin underlying metal layer and a Cu layer by a sputtering method and forming a thick Cu layer by an electrolytic plating method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein: 7. The method according to claim 5, wherein the step (5) or the step (6 ′) is a reactive ion etching (RIE).
Method, ion milling method or chemical mechanical polishing (CM
The method according to claim 1, wherein the method is performed by the method P). 8. The method according to claim 7, wherein said reactive etching is an ICP type or ECR type etching. 9. The method according to claim 1, wherein the step (6) or the step (7 ′) is performed by a wet method. 10. The method according to claim 6, further comprising, after the step (6) or the step (7 ′), a step of forming an upper interlayer insulating film and a step of forming an upper wiring layer. A method for manufacturing a semiconductor device according to claim 1.