JP2828992B2 - Digital protection relay - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital protection relay, and more particularly to a digital protection relay having a plurality of channels for inputting analog signals of a power system, and switching between the plurality of channels to form a power system. The present invention relates to a digital protection relay for taking an analog signal into an analog-to-digital converter.

[Prior art] Conventionally, digital protection relays have been published in IEEJ magazine 105, 12
No. 11 (1979-1) and Hitachi Review Review Vol. 61 No. 11 (1979-1)
As discussed in 1), the input filter is RC
It is composed of active filters, and an S / H circuit is provided at the subsequent stage of each filter to perform sampling at the same time.

[Problems to be solved by the invention]

In the above prior art, since the S / H circuit is provided for each channel, there is a problem that the number of elements is large and the circuit cannot be downsized. Furthermore, the characteristics deterioration due to the aging of the circuit, the influence of the ambient temperature, and the like have not been considered.

For this reason, a method of sequentially performing A / D conversion using a high-speed A / D to eliminate the S / H circuit has been considered, but when there are a plurality of channels, a signal for each channel is used. There has been a problem that the accuracy cannot be improved due to no consideration given to the influence of the sampling deviation that occurs when data is imported.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital protection relay which overcomes the above-mentioned disadvantages of the prior art, has a plurality of channels for inputting an analog signal of a power system, and can reduce the influence of a sampling shift generated when capturing a signal for each channel. Is to provide.

[Means for solving the problem]

In order to achieve the above object, in the digital protection relay of the present invention, a plurality of channels for inputting an analog signal of a power system and a multiplexer for sequentially switching the plurality of channels and transferring an analog signal sampled to analog-to-digital conversion means are provided. And a digital filter having an operation unit for inputting a digital signal converted by an analog-to-digital conversion unit and performing a filter operation, wherein the operation unit of the digital filter corrects a sampling phase difference between a plurality of channels. It is characterized by the following.

[Action]

ADVANTAGE OF THE INVENTION According to the digital protection relay of this invention, it becomes possible to correct | amend the phase difference which generate | occur | produces by switching a plurality of channels sequentially and to sample by a calculation part of a digital filter, and to reduce a phase difference.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a digital arithmetic processing unit to which the present invention is applied, in particular, an analog input unit.

In the figure, 1A, 1B and 1C are anti-aliasing filters for removing signals having a frequency component equal to or more than 1/2 of the analog / digital conversion frequency, 2 is a multiplexer, 3 is a sample / hold circuit, and 4 is an analog / digital. Converter 5, buffer memory 6, digital signal processor (DSP) 6, program ROM for instruction of DSP 8, multiport RAM 8 accessible from a plurality of directions, 9 internal bus of analog input circuit, 10 Is an interface circuit between a standardized bus (VMEbus, Multi bus, STDbus, etc.) and an analog input circuit, 11 is a timing control circuit, and 12 is a standardized bus.

In FIG. 1, in1, in2, and inN are analog input signals.

Next, the outline of the DSP 6 shown in FIG. 1 will be described.

FIG. 2 shows a block configuration of the DSP. In FIG. 2, 1 is an instruction ROM, and 2 is n bits × n.
It is a high-speed parallel multiplier of bits. This high-speed parallel multiplier multiplies input data inA and inB during one instruction cycle and outputs a result outC. 3 is a data RAM, 4 is an address register for specifying an address of an external memory of the DSP, 5 is a data register, and 6 is an ALU (Arithm
emetic Logic Unit), an arithmetic unit that performs processing at the time of addition and subtraction, 7 is an accumulator, 8 is a timing control circuit, 9
Is an internal bus (data bus, address bus) of the DSP.

As described above, the DSP has a multiplier as described above, so that the product-sum operation can be performed during one instruction cycle, and further, the pipeline processing can be performed. High-speed numerical operation of floating-point data can be realized.

The use of such a DSP makes it possible to realize a digital filter that repeats the product-sum operation of fixed and floating point data at high speed.

The digital filter has the following features as compared with the analog filter.

No adjustment on mounting is required. No aging. Easy to change specifications and characteristics. Compact size. Fig. 3 shows an example of a digital filter block configuration. This configuration is configured by a DSP program.

In the figure, (a) shows IIR (Infinite extent Impulse)
Response) type filter, (b) FIR (Finite extent)
This is a block configuration of an Impulse Response) type filter.

In FIG. 3A, Xn is an input signal, 1 is a multiplication unit for multiplying a gain coefficient H, 2, 3, 4, and 5 are filter coefficients B1,
A multiplication unit that multiplies B2, A1 and A2. 6 is a delay unit for delaying the signal Wn by one time of the sampling period T, and 7 is a signal Wn
A delay unit for delaying -1 by one time, 8, 9, 10 and 11 are addition units, and Yn is an output signal of a digital filter.

In FIG. 3 (b), Xn 'is the input signal, 12 and 13
Xn is a delay unit for delaying one time and Xn-1 for one time, 14, 15 and 16 are multipliers for multiplying filter coefficients A0 ', A1' and A2 ', 17 and 18 are adders, Yn' Is the output signal of the digital filter.

The operation in the digital filter is performed as follows. First, the operation formula of the IIR type digital filter described above is shown.

 Wn = H · Xn + B1 · Wn−1 + B2 · Wn−2 Equation (1) Yn = Wn + A1 · Wn−1 + A2 · Wn−2 Equation (2) H: Gain coefficients A1, A2, B1, B2: Filter coefficients Xn: input data Yn: output data Wn-1: one-time delay data of operation result Wn Wn-2: two-time delay data of operation result Wn Next, the operation expression of the FIR type digital filter is shown.

Yn '= A0.Xn' + A1.Xn-1 '+ A2.Xn-2' Equation (3) A0 ', A1', A2 ': Filter coefficient Xn-1': One-time delay data of input data Xn ' Xn-2 ': Two-time delay data of input / data Xn' Xn ': Input data Yn': Output data The digital filter of IIR formation and FIR type is programmed by software in DSP, and this program is executed. Can be easily realized. Therefore, it goes without saying that filters of different types and filters of different orders can be arbitrarily configured and changed by software.

Further, taking the above-mentioned IIR type digital filter as an example, with the same configuration, the low-pass filter, band-pass filter, high-pass filter, notch filter, low-pass notch filter, high-pass notch filter, and all-pass filter change the filter coefficient. It can be realized only by.

 The transfer function of each filter is shown below.

FIG. 4 shows an outline of frequency characteristics of various filters.

(A) low-pass filter (b) band-pass filter (c) high-pass filter (d) notch filter (e) low-pass notch filter (f) high-pass notch filter (g) all-pass filter From the above description, the digital filter is a coefficient A
By changing 1, A2, B1, and B2, the arithmetic processing is the same, and filters of different types can be easily changed.

Next, the operation of the embodiment when the present invention is applied to a digital protection relay device will be described.

FIG. 5 is a flowchart for explaining the operation of the embodiment.

This will be described below with reference to the block diagram of FIG. 1 and the flowchart of FIG.

The anti-aliasing filters 1A, 1B and 1C in FIG.
Signals in1, in2, and inN are input to the power system voltage and current via PT / CT (transformer / current transformer). The aliasing error prevention filters 1A, 1B and 1C prevent aliasing errors due to analog / digital conversion, operate as an input buffer, and input to the multiplexer (MPX) 2. The MPX switches a plurality of inputs periodically and sequentially and inputs them to the S / H circuit 3. S / H
The circuit 3 holds analog input data while the A / D converter 4 operates, in order to make the conversion information of the A / D converter 4 highly accurate. The A / D converter 4 converts the sampled and held analog signal into a digital signal and inputs the digital signal to the buffer memory 5. The DSP 6 inputs the input data stored in the buffer memory 5 via the internal bus 9 based on the program stored in the instruction ROM 7, and performs an operation.

The DSP 6 writes the result of the operation into the multi-port RAM 8 via the internal bus 9 again. As described above, since the multi-port RAM 8 is a dual-port RAM, bidirectional access is possible, so that output data is output from the port different from the port written from the DSP 6 via the interface circuit 10. It is.

 Next, a description will be given with reference to the flowchart of FIG.

In the flowchart of FIG.
Clear the internal memory and registers of P, and input the filter coefficient of the digital filter of each channel from the external memory. In step 2, a synchronization process is performed. This process makes the DSP wait for an external interrupt signal.

In step 3, the input data stored in the buffer memory 5 shown in FIG. 1 is input to a memory inside the DSP.

In step 4, the digital filter operation shown in equations (1) and (2) is performed on the input data of one channel. Different filter coefficients are stored in advance in the internal memory of the DSP shown in FIG. 6 for each channel, and those stored in areas A and B of the internal memory are used for input data of one channel.

In step 5, unlike the case of 1ch, the coefficients of the digital filter are changed using the data stored in the areas C to D in FIG. 6 in order to correct the phase difference due to sampling by sequentially switching. In step 6, 2ch
Filter operation is performed on the input data in the same manner as in 1cp. In step 7, similarly to step 5, the coefficients stored in the areas EF of FIG. 6 are used to change the coefficients of the digital filter. In step 8, a digital filter operation is performed on Nch input data in the same manner as in 1ch and 2ch.

In step 9, a protection operation is performed using the digitally filtered data.

In step 10, the operation result is output to a memory external to the DSP. FIG. 7 shows gain and phase characteristics in the case where the present invention is applied to a band-pass filter, the cutoff frequency of each channel is changed, and the phase difference is corrected by sequentially switching and sampling. FIG. 7A shows an example of a gain characteristic, and FIG. 7B shows an example of a phase characteristic.

In FIG. 7, reference numerals 1 and 1 'denote a gain characteristic and a phase characteristic of a reference channel. 2 and 2 'with respect to the reference channel, at the center frequency (fundamental frequency) f _0, is a characteristic example of a case where delaying the phase A only. 3 and 3 'are center frequencies (fundamental frequencies) with respect to the reference channel.
This is a characteristic example when the phase is advanced by B at f ₀ .

As apparent from FIG. 7, the gain difference between the band-pass filter at the center frequency (fundamental frequency) f ₀ with respect to the reference channel is only little phase difference. By adjusting this phase difference to the phase shift caused by the sampling shift, the sampling phase difference between channels can be corrected.

FIG. 8 shows an example of input / output waveforms of the digital filter when the characteristics are the same.

In FIG. 8, (a) shows input data to be input to each channel. (B), (c) and (d) are 1ch and 2ch
And Nch sampling command signals. (E),
(F) and (g) are output waveform examples of 1ch, 2ch, and Nch.

As is clear from FIG. 8, the sampling time is 1c
The outputs G1, G2, and G3 of the digital filter are the same in magnitude, although h, 2ch, and Nch are shifted by Δt. Therefore, it can be seen that the sampling phase difference between the channels due to the sampling deviation is corrected.

〔The invention's effect〕

ADVANTAGE OF THE INVENTION According to the digital protection relay of this invention, it becomes possible to perform the correction | amendment of the phase difference which generate | occur | produces by switching a plurality of channels sequentially, and a sampling, and a filter process simultaneously in the operation part of a digital filter. Since the effect of sampling deviation occurring when a signal is taken can be reduced, an effect is obtained that an analog signal input to a plurality of channels can be detected at high speed and with high accuracy.

[Brief description of the drawings]

1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of a DSP, FIG. 3 is a block diagram of a digital filter, FIG. 4 is a frequency characteristic diagram of the digital filter, FIG. FIG. 6 is a flowchart showing the operation of the embodiment of the present invention, FIG. 6 is a diagram showing the contents of the memory in the DSP, FIG. 7 is a characteristic diagram of the band-pass filter, and FIG. 1A, 1B, 1C… Return error prevention filter, 2… MPX, 3
... S / H, 4 ... A / D, 5 ... Buffer memory, 6 ... DS
P, 7 ROM, 8 RAM, 9 Internal bus, 10 IN
F, 11: Timing control, 12: Standardized bus.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Junzo Kawakami 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (56) References JP-A-60-84912 (JP, A) JP-A-60 -229618 (JP, A) JP-A-51-30339 (JP, A) JP-A-51-92055 (JP, A)

Claims (4)

(57) [Claims] 1. A plurality of channels for inputting an analog signal of a power system, a multiplexer for sequentially switching the plurality of channels and transferring an analog signal sampled to an analog-to-digital converter, and a multiplexer which is converted by the analog-to-digital converter. A digital filter having an operation unit for inputting a digital signal and performing a filter operation, wherein the operation unit of the digital filter corrects a sampling phase difference between the plurality of channels. . 2. The digital protection relay according to claim 1,
A digital protection relay, wherein the digital filter has different filter characteristics for each of the plurality of channels. 3. The digital protection relay according to claim 2,
The digital protection relay according to claim 1, wherein the filter characteristics of the plurality of channels are such that a gain of a fundamental frequency is substantially constant and a phase of the fundamental frequency is different. 4. The digital protection relay according to claim 2,
A digital protection relay, wherein the arithmetic unit includes a memory in which different filter coefficients are stored for each of the plurality of channels.