JP2004158170A - Memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable simultaneous reading and operating of the data, to increase the operating speed, and to decrease the costs by the reduction of computing elements. <P>SOLUTION: Each bit of 8-bit data is stored in eight memory cells ML of each unit UN of a memory cell array 110 in advance. A capacitor C of the eight memory cells ML has capacitance corresponding to the weight of each bit of the 8-bit data. At least two units UN, namely a plurality word lines WL regarding at least two data, are activated simultaneously. As a result, on each bit line BL, the accumulation charge of the capacitor C of a plurality of memory cells ML connected to the plurality of word lines WL regarding at least two activated data is connected each. A voltage signal of a value corresponding to an obtained total amount of charge is converted to a digital signal by an A/D convertor on the bit line BL. The digital signal corresponds to the addition result of the data stored in at least two units UN. <P>COPYRIGHT: (C)2004,JPO

Description

  The present invention relates to a memory device. More specifically, the present invention activates a plurality of word lines at the same time, combines charges stored in capacitors of a plurality of memory cells connected to the plurality of word lines on one bit line, and sets a value corresponding to the total amount of the charges. The present invention relates to a memory device capable of simultaneously reading data and performing arithmetic operations by outputting a digital signal, thereby improving arithmetic speed and reducing costs by reducing the number of arithmetic units.

  FIG. 8 shows a configuration example of a conventional memory block 200. The memory block 200 includes a memory cell array 210, a storage data input / output port 220, a row address decoder 230, and a control circuit 240.

  As shown in FIG. 9, the memory cell array 210 is orthogonal to the plurality of bit lines BL for transferring data extending in the row direction (row direction) and the plurality of bit lines BL extending in the column direction (column direction). It comprises a word line WL and memory cells ML connected to the bit line BL and the word line WL and arranged in a matrix.

  The memory cell ML has a DRAM structure and includes an access transistor T and a capacitor C. One end of the capacitor C is grounded, and the other end is connected to the bit line BL via the access transistor T. The gate of the access transistor T is connected to the word line WL. Reading and writing to the memory cell ML are performed by activating the word line WL to turn on the access transistor T, as is well known in the art.

  The storage data input / output port 220 includes a column address decoder 221, an address buffer 222, and an I / O buffer 223. The column address decoder 221 includes an I / O gate (column switch), a sense amplifier, and the like. The column address is input to the column address decoder 221 via the address buffer 222.

  The column address decoder 221 secures connection with a plurality of bit lines BL connected to a plurality of predetermined memory cells ML in the column direction of the memory cell array 210 in accordance with the column address supplied via the address buffer 222. Then, through the I / O buffer 223 and the column address decoder 221, writing and reading of storage data to and from a predetermined memory cell ML in the column direction are enabled.

  Further, the row address is input to the row address decoder 230 via the address buffer 231. The row address decoder 230 activates a word line WL connected to a predetermined memory cell ML in the row direction of the memory cell array 210 in accordance with a row address supplied via the address buffer 231, and the I / O buffer 223 In addition, through the column address decoder 221, the storage data can be written and read from / to the predetermined memory cell ML in the row direction.

  Further, the control circuit 240 controls the operation of each circuit described above of the memory block 200 based on the control input.

  When performing an operation using the data stored in the memory block 200, for example, performing addition, data to be added and added data are sequentially read from the memory block 200, and an adder provided separately from the memory block 200 is provided. Add them in. Therefore, there is an inconvenience that the operation speed cannot be increased because the data reading and the operation are sequentially performed. Further, since an arithmetic unit that is separate from the memory block 200 is required, there is a disadvantage that the operation becomes expensive accordingly. The same applies to other operations such as subtraction.

  SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory device which enables simultaneous processing of data reading and operation, thereby improving operation speed and reducing costs by reducing the number of operation units.

  A memory device according to the present invention is a memory device capable of coupling stored charges of capacitors of a plurality of memory cells connected to a plurality of activated word lines on one bit line. Activating means for activating simultaneously, and the accumulated charges of the capacitors of the plurality of memory cells connected to the plurality of word lines activated by the activating means are combined into the total amount of charges obtained on one bit line. Signal output means for outputting a digital signal of a corresponding value.

  In the present invention, a plurality of word lines are activated simultaneously. As a result, the charges stored in the capacitors of the memory cells connected to the activated word lines are combined on one bit line. Then, a digital signal having a value corresponding to the total charge is output.

  For example, a digital signal having a value corresponding to the total charge is obtained by converting the total charge into a voltage signal having a value corresponding to the total charge, and then converting the voltage signal from an analog signal to a digital signal. In this case, when converting a voltage signal into a digital signal, a digital signal of an arbitrary gradation can be obtained depending on the function of the A / D converter.

  Here, by simultaneously activating a plurality of word lines related to two or more data, a calculation result of the two or more data is obtained as a digital signal. For example, when data to be added is stored in a unit including a plurality of memory cells connected to a plurality of word lines related to each data, an addition result of the data is obtained as a digital signal. Further, for example, a unit including a plurality of memory cells connected to a plurality of word lines related to each data stores the minuend data or the subtrahend data, thereby obtaining a subtraction result of the data as a digital signal. . In this case, for example, the minuend data is data in straight binary format, and the subtrahend data is data in 2's complement format.

  As described above, a plurality of word lines are simultaneously activated, the charges stored in the capacitors of the plurality of memory cells connected to the plurality of word lines are combined on one bit line, and a digital signal having a value corresponding to the total amount of the charges is obtained. Is output, and simultaneous processing of data reading and calculation can be performed, so that the calculation speed can be improved and the cost can be reduced by reducing the number of calculation units.

Note that the number of memory cells for storing one piece of data can be reduced by including a plurality of memory cells connected to one bit line having different capacitances of capacitors. For example, when one data is N-bit data (N is an integer of control), the number of word lines related to the one data is N, and N memory cells connected to the N word lines are used. Are made to have a capacity corresponding to the weight of each bit of N-bit data. Thus, the number of memory cells for storing N-bit data is N. On the other hand, if the capacity of the capacitor of each memory cell is the same, 2 ^N -1 memory cells for storing N-bit data are required.

  According to the present invention, a plurality of word lines are simultaneously activated, charges accumulated in capacitors of a plurality of memory cells connected to the plurality of word lines are combined on one bit line, and a value corresponding to the total amount of the charges is combined. The configuration is such that a digital signal is output, so that simultaneous processing of data reading and calculation can be performed, the calculation speed can be improved, and the cost can be reduced by reducing the number of calculation units.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a configuration of a memory block 100 as an embodiment. The memory block 100 includes a memory cell array 110, a storage data input / output port 120, a row address decoder 130, an operation data output port 140, and a control circuit 150.

  As shown in FIG. 2, the memory cell array 110 is orthogonal to the plurality of bit lines BL for transferring data extending in the row direction (row direction) and the plurality of bit lines BL extending in the column direction (column direction). It comprises a word line WL and memory cells ML connected to the bit line BL and the word line WL and arranged in a matrix.

  The memory cell ML has a DRAM structure and includes an access transistor T and a capacitor C. One end of the capacitor C is grounded, and the other end is connected to the bit line BL via the access transistor T. The gate of the access transistor T is connected to the word line WL. Reading and writing to the memory cell ML are performed by activating the word line WL to turn on the access transistor T, as is well known in the art.

  Here, the plurality of memory cells ML connected to each bit line are divided into units UN for each of the eight memory cells ML connected to eight word lines WL, and each of the divided units UN Each bit of one 8-bit data can be stored.

  In this case, the capacitors C of the eight memory cells ML connected to the eight word lines have a capacity corresponding to the weight of each bit of the 8-bit data. In FIG. 2, the upper side is the LSB (least significant bit) side, and the lower side is the MSB (most significant bit) side. The capacity of the capacitor C of the eight memory cells ML constituting each unit UN is doubled sequentially from the LSB side to the MSB side. That is, assuming that the capacitance of the capacitor C of the LSB is p, the capacitance of the capacitor C of the eight memory cells ML constituting each unit UN is p, 2p, 4p, 8p, 16p, 32p, 64p from the LSB side, respectively. , 128p.

  The storage data input / output port 120 includes a storage data column address decoder 121, an address buffer 122, and an I / O buffer 123. The column address decoder 121 includes an I / O gate (column switch), a sense amplifier, and the like. The column address is input to the column address decoder 121 via the address buffer 122.

  The column address decoder 121 secures the connection with the bit line BL connected to the predetermined memory cell ML in the column direction of the memory cell array 110 in accordance with the column address supplied via the address buffer 122, and Through the O-buffer 123 and the column address decoder 121, writing and reading of storage data to and from a predetermined memory cell ML in the column direction is enabled.

  Also, a row address is input to the row address decoder 130 via the address buffer 131. The row address decoder 130 activates a word line WL connected to a predetermined memory cell ML in the row direction of the memory cell array 110 according to the row address supplied via the address buffer 131, and activates the I / O buffer 123 Through the column address decoder 121, writing and reading of storage data to and from the predetermined memory cell ML in the row direction are enabled.

  The operation data output port 140 includes an operation data output column address decoder 141, an address buffer 142, and an A / D converter 143. The column address decoder 141 includes an I / O gate (column switch), a sense amplifier, and the like. The column address is input to the column address decoder 141 via the address buffer 142.

  The column address decoder 141 secures connection with one bit line BL connected to a predetermined memory cell ML in the column direction of the memory cell array 110 in accordance with the column address supplied via the address buffer 142, A voltage signal having a value corresponding to the total amount of charges obtained on the one bit line BL is output. The A / D converter 143 converts the voltage signal (analog signal) output from the column address decoder 141 into a predetermined bit, for example, an 8-bit digital signal, and outputs it as operation data.

  Further, the control circuit 150 controls the operation of each of the above-described circuits of the memory block 100 based on the control input.

Next, the operation of the memory block 100 shown in FIG. 1 will be described.
This memory block 100 writes and reads stored data to and from a predetermined memory cell ML of the memory cell array 110 by the same operation as that of the conventional memory block 200 shown in FIG. Is possible.

  That is, the column address is input to the column address decoder 121 via the address buffer 122. The column address decoder 121 secures a connection with the bit line BL connected to a predetermined memory cell ML in the column direction of the memory cell array 110 in accordance with the column address. Also, a row address is input to the row address decoder 130 via the address buffer 131. The row address decoder 130 activates a word line WL connected to a predetermined memory cell ML in the row direction of the memory cell array 110 according to the row address. As a result, through the I / O buffer 123 and the column address decoder 121, the writing and reading of the storage data to and from the predetermined memory cells ML in the column direction and the row direction are performed.

  The operation of outputting operation data using the operation data output port 140 will be described. In each of the eight memory cells ML of each unit UN of the memory cell array 110, each bit of 8-bit data is stored in advance.

  The row address is input to the row address decoder 130 via the address buffer 131. The row address decoder 130 simultaneously activates two or more units UN in the row direction of the memory cell array 110, that is, a plurality of word lines WL related to two or more data, corresponding to the row address. As a result, on each bit line BL, the accumulated charges of the capacitors C of the plurality of memory cells ML connected to the plurality of word lines WL relating to the activated two or more data are respectively coupled.

Here, assuming that the total capacitance of the capacitors C of the plurality of memory cells ML is Cm, the total charge stored therein is Qc, and the capacitance of the bit line BL is Cb, the total bit line charge Qb is expressed by the following equation. become that way. That is, the total bit line charge Qb is proportional to the total charge Qc stored in the capacitors C of the plurality of memory cells ML.
Qb = Qc × Cb / (Cm + Cb) (1)

  In this state, a column address is input to the column address decoder 141 via the address buffer 142. The column address decoder 141 secures connection with one bit line BL connected to a predetermined memory cell ML in the column direction of the memory cell array 110 in accordance with the column address. As a result, the column address decoder 141 outputs a voltage signal having a value corresponding to the total amount of charges obtained on the bit line BL for which connection has been secured.

  Then, this voltage signal is converted into an 8-bit digital signal by the A / D converter 143, and addition data corresponding to the addition result of the two or more data stored in the two or more units UN is obtained. In this case, by sequentially changing one bit line BL for which connection is ensured by the column address decoder 141, addition data corresponding to each bit line BL is sequentially obtained from the A / D converter 143.

  Here, a specific example of the addition operation will be described with reference to FIG. This specific example is an example in which two 8-bit data are added. The unit UN1 stores 8-bit data as augend data. The 8-bit data is “00010100”, which is “20” in decimal notation. On the other hand, the unit UN2 stores 8-bit data as addend data. The 8-bit data is “10000101”, which is “133” in decimal notation.

  In this way, the data of the augend and the addend are stored in each of UN1 and UN2, so that only the capacitor C which is not hatched among the memory cells ML of these units UN1 and UN2 stores the charge. State. In this case, the total amount of charge stored in all the capacitors C of the eight memory cells ML of the unit UN1 is 20q, where q is the charge stored in the capacitor C of the memory cell ML of LSB. Similarly, the total amount of charges stored in all the capacitors C of the eight memory cells ML of the unit UN2 is 133q.

  In such a state, when the plurality of word lines WL related to the two units UN1 and UN2 are simultaneously activated and the access transistor T of each memory cell ML is turned on, the respective units UN1 and UN1 on the bit line BL are turned on. The stored charges at UN2 are combined. Thus, the total amount of charges coupled on the bit line BL is equivalent to "153" in decimal. That is, from the above equation (1), the total bit line charge Qb is Qb = 153q × Cb / (Cm + Cb).

  Therefore, the column address decoder 141 outputs a voltage signal having a value corresponding to the total amount of charge “153”. From the A / D converter 143, addition data corresponding to the addition result of the data stored in the two units UN1 and UN2 is obtained.

  Since the unit UN1 and the unit UN2 have an 8-bit output, the added data has a value of 9 bits. Therefore, if a 9-bit output A / D converter is used, the added data can be output with the accuracy of the values stored in the units UN1 and UN2. An 8-bit output A / D converter can also be used. In this case, since the output is an 8-bit output, the accuracy of the output value is low.

  FIG. 4 shows an example of the relationship between the total bit line charge and the output value (addition data) of the 8-bit output A / D converter 143. In the case of FIG. 4, the gradation conversion from 512 gradations to 256 gradations can be performed by such conversion characteristics. In FIG. 4, since the gradation changes from 512 gradations to 256 gradations, a value twice as large as this output value is the actual addition result.

  Note that the total bit line charge on the horizontal axis in FIG. 4 is normalized so that q × Cb / (Cm + Cb) becomes 1. The same applies to the total bit line charge on the horizontal axis in FIGS. 6 and 7 described later.

  As described above, in the present embodiment, simultaneous processing of data reading and addition can be performed, and the calculation speed can be improved. Further, in the present embodiment, there is no need to provide an arithmetic unit for performing the addition operation, and the cost can be reduced. Further, in the present embodiment, since gradation conversion can be performed by the A / D converter 143, if the A / D converter 143 can change the number of bits of the output digital signal, a dedicated circuit is used. , The gradation operation can be easily performed.

  In the above-described embodiment, an example in which the addition operation is performed has been described. However, a configuration in which the subtraction operation is performed may be employed.

  In this case, for example, when the minuend data and the minuend data are 8-bit data, the unit UN for storing the minuend is composed of eight memory cells ML, but the unit UN for storing the minuend is composed of nine memory cells ML. It consists of. This is because the 8-bit data of the minuend is stored as it is in the straight binary format, but the 8-bit data of the minuend is converted and stored in 2's complement format data (9 bits).

  Here, the reason why the data in the form of two's complement is 9 bits is that the data in the form of two's complement becomes "10000000" when the reduction number is 8-bit data and "00000000". That's why.

  Here, a specific example of the subtraction operation will be described with reference to FIG. In this specific example, 8-bit data as subtraction data is subtracted from 8-bit data as reduction data. In the unit UN1, 8-bit data as the minuend data is stored as it is in a straight binary format. The 8-bit data is “10000101”, which is “133” in decimal notation. On the other hand, in the unit UN2, 8-bit data as the subtraction data is converted into 2's complement data and stored as 9-bit data. The 8-bit data is “00010100”, which is “20” in decimal notation. The 9-bit data after the conversion into the 2's complement format is “011101100”.

  In this way, the data of the minuend and the decrement are stored in each of UN1 and UN2, so that only the unhatched capacitor C among the memory cells ML of these units UN1 and UN2 has accumulated electric charge. Become. In this case, the total amount of charge stored in all the capacitors C of the eight memory cells ML of the unit UN1 is 133q, where q is the charge stored in the capacitor C of the memory cell ML of LSB. Similarly, the total amount of charges stored in all the capacitors C of the nine memory cells ML of the unit UN2 is 236q.

  In such a state, when the plurality of word lines WL related to the two units UN1 and UN2 are simultaneously activated and the access transistor T of each memory cell ML is turned on, the respective units UN1 and UN1 on the bit line BL are turned on. The stored charges at UN2 are combined. Thus, the total amount of charges coupled on the bit line BL is equivalent to “369” in decimal.

  Therefore, the column address decoder 141 outputs a voltage signal having a value corresponding to the total amount of charge “369”. Here, “369” is “101110001” in binary notation. The MSB at this time is a sign bit, which indicates positive when "1" and negative when "0". Therefore, unlike the case of addition, the A / D converter 143 performs A / D conversion in consideration of the sign bit, and obtains data as a result of subtraction of the data stored in the two units UN1 and UN2. .

  6 and 7 show examples of the relationship between the total bit line charge and the output value (subtraction data) of the A / D converter 143, respectively. Here, FIG. 6 shows an example in which absolute value conversion is not performed, and FIG. 7 shows an example in which absolute value conversion is also performed. In the case of the example of FIG. 6, digital signals of “−255” to “255” are output corresponding to the total bit line charges “1” to “511”. On the other hand, in the example of FIG. 7, “255” to “1” corresponding to the total bit line charge amounts “1” to “255”, and “0” to “255” corresponding to “256” to “511”. Output a digital signal.

  Note that when the minuend data is 8-bit data, it can take a value in the range of “0” to “255” in decimal, but when the subtrahend data is also 8-bit data, it can take values from “0” to decimal. It can take a value in the range of "255". In this case, if the data of the minuend and the subtrahend are correctly stored in the two units UN1 and UN2, and the plurality of word lines WL related to the two units UN1 and UN2 are activated at the same time, the total amount of the bit line charges becomes It becomes "1" to "511" in decimal, and cannot be "0". For this reason, in FIGS. 6 and 7, conversion is performed also when the total bit line charge is “0”, but the converted digital value itself has no particular meaning.

  The subtraction data output from the A / D converter 143 is, for example, 9-bit data in which the MSB is a sign bit in the case of FIG. 6, and is 8-bit data in the case of FIG. However, similarly to the case of the above-described addition, the A / D converter 143 can perform gradation conversion.

  In the above-described embodiment, the case where the unit UN that stores one data is configured by eight or nine memory cells ML is described. However, the number of memory cells ML that configure the unit UN is different from this. It is not limited.

In the above embodiment, the capacity of the capacitor C of the memory cell ML storing the data of each bit is set to a size corresponding to the weight of the bit, so that the unit UN storing the data of 8 bits is divided into eight units UN. It can be configured only with the memory cell ML. However, if the capacitance of the capacitor C of the memory cell ML is all the same, it is necessary to allow the accumulation of charge amount of 256 gradations, the unit UN 2 ⁸ -1 memory cells ML Can be configured.

  Also, for example, the unit UN that stores 8-bit data can be configured with fewer memory cells ML instead of eight memory cells ML. For example, the unit UN can be constituted by four memory cells ML. In this case, two-bit charges are stored in the capacitor C of each memory cell ML.

  For example, when the 8-bit data is “10000101”, the first memory cell ML stores “01”, that is, a charge of a charge amount equivalent to “1” in decimal from the LSB side, and Of the memory cell ML stores the charge of "0100", that is, the charge amount corresponding to "4" in decimal, and the third memory cell ML stores "000000", that is, "0" in decimal. It is sufficient to accumulate the electric charge of the electric charge amount and to store the electric charge of the electric charge amount corresponding to "10000000", that is, "128" in the decimal number in the fourth memory cell ML. In this case, if the capacitance of the capacitor C of the four memory cells ML is p, the capacitance of the capacitor C of the first memory cell ML is p, the second is 4p, the third is 16p, and the fourth is 64p. Good.

  Further, in the above-described embodiment, the case where binary data is stored in each unit UN has been described. However, if data of each n-ary digit is stored in the memory cell ML of each unit UN, an n-ary operation is performed. You can do it too. In this case, data can be stored by storing a charge amount corresponding to the value of the corresponding digit in the capacitor C of the memory cell ML of each unit UN.

  For example, when storing data of “235” as a decimal number, the capacitor C of the memory cell ML storing the digit of 1 stores a charge of a charge amount corresponding to “5” and stores the digit of 10 The capacitor C of the memory ML accumulates an electric charge of an amount corresponding to “3 × 10”, and the capacitor C of the memory ML that stores 100 digits stores an electric charge of an amount of electric charge corresponding to “2 × 100” Should be accumulated. Of course, the capacitor C of the memory cell ML corresponding to each digit needs to have a capacity capable of storing the maximum accumulated charge amount of each digit.

  In addition, in the above-described embodiment, addition and subtraction are described as examples of operations, but multiplication and division can be performed by devising the format and arrangement of data input to each unit. For example, in the multiplication of M × N, M is copied to N units UN, and then the above-described addition operation is performed on the N units UN.

  Further, in the above embodiment, the memory cell ML of the memory cell array 110 has a DRAM structure, but is not limited to this. In short, it is only necessary that the charge stored in the capacitors of the plurality of memory cells connected to the plurality of activated word lines be combined on one bit line.

  The present invention enables simultaneous processing of data reading and calculation, thereby improving the calculation speed and reducing costs by reducing the number of calculation units. The present invention is intended for reading data from a memory and performing calculation processing such as addition and subtraction. Applicable.

FIG. 3 is a block diagram illustrating a configuration of a memory block according to an embodiment. FIG. 3 is a diagram illustrating a part of a memory cell array. FIG. 9 is a diagram for describing a specific example of an addition operation. FIG. 9 is a diagram illustrating a relationship (in the case of addition) between a total bit line charge and an output value. FIG. 9 is a diagram for explaining a specific example of a subtraction operation. FIG. 9 is a diagram illustrating a relationship between the total bit line charge and an output value (in the case of subtraction, no absolute value conversion is performed). FIG. 11 is a diagram illustrating a relationship between the total amount of bit line charges and an output value (in the case of subtraction, absolute value conversion is performed). FIG. 11 is a block diagram illustrating a configuration example of a conventional memory block. FIG. 3 is a diagram illustrating a part of a memory cell array.

Explanation of reference numerals

100 memory block, 110 memory cell array, 120 storage data input / output port, 121 storage data column address decoder, 122 address buffer, 123 I / O Buffer, 130: Row address decoder, 131: Address buffer, 140: Operation data output port, 141: Operation data output column address decoder, 142: Address buffer, 143 ... A / D converter, 150 ... control circuit

Claims (8)

A memory device capable of coupling, on one bit line, stored charges of capacitors of a plurality of memory cells connected to a plurality of activated word lines,
Activating means for simultaneously activating a plurality of word lines;
The stored charges of the capacitors of the plurality of memory cells connected to the plurality of word lines activated by the activating means are combined to output a digital signal having a value corresponding to the total amount of charges obtained on the one bit line. And a signal output unit. The signal output means,
Voltage conversion means for converting the total charge to a voltage signal having a value corresponding to the total charge;
2. The memory device according to claim 1, further comprising an analog-digital converter that converts the voltage signal converted by the voltage converter from an analog signal to a digital signal. 3. The memory device according to claim 1, wherein the plurality of memory cells connected to the one bit line include ones having different capacitances. The activation means,
The memory device according to claim 1, wherein a plurality of word lines for two or more data are simultaneously activated. When one data is N-bit data (N is a positive integer), the number of word lines related to the one data is N,
The memory device according to claim 4, wherein the capacitors of the N memory cells connected to the N word lines have a capacity corresponding to the weight of each bit of the N-bit data. The memory device according to claim 4, wherein data to be added is stored in a unit including a plurality of memory cells connected to a plurality of word lines related to each data. The memory device according to claim 4, wherein a unit including a plurality of memory cells connected to a plurality of word lines related to each data stores the minuend data or the subtrahend data, respectively. The memory device according to claim 7, wherein the minuend data is data in a straight binary format, and the minuend data is data in a 2's complement format.

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