JP2001337332A - Liquid crystal electrooptical device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize simplification of a process forming projections and a process scattering spacers which have been essential until now in the conventional manufacturing process of a multi-domain vertically aligned liquid crystal display device. SOLUTION: A space (cell gap) between substrates is held by wall-like spacers 15 formed in the liquid crystal display device. The wall-like spacers 15 have inclined side faces, and can control the switching direction of liquid crystal molecules. Thus, the liquid crystal display device of multi-domain vertically aligned wide viewing angle display with the uniform space (cell gap) between substrates is obtained by the wall-like spacers 15. Furthermore, when the manufacturing process of this liquid crystal display device is used, the omission of a rubbing process is realized, and also the omission of the spacer scattering process is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a liquid crystal display device realizing a wide viewing angle and a high-speed response, and a method of manufacturing the same. Further, the present invention relates to a technique for improving the productivity of the liquid crystal electro-optical device.

[0002]

2. Description of the Related Art A liquid crystal electro-optical device (hereinafter, referred to as a liquid crystal display device) using a semiconductor element is used as a direct-view display device such as a mobile computer, a video camera, a digital camera, a mobile phone, and a head-mounted display.
Also, development is actively being carried out as a projection type display device for the purpose of enlarged display by an optical system such as a lens such as a front and rear projector.

As a substitute for the CRT, the use of recent liquid crystal display devices has been expanding as a display device of a liquid crystal monitor and the screen size has been increasing.

Here, a general liquid crystal display device uses liquid crystal molecules having a long and thin structure and having two refractive indexes in a major axis (length) direction and a minor axis (thickness) direction as a display medium. Such a medium having two refractive indexes is called a uniaxial medium.

In a liquid crystal display device, such molecules have fluidity in a gap of about several μm between substrates without forming strong bonds between the molecules as in a solid state (they exist in a liquid state). There).

[0006] Since it has fluidity (is liquid), it is easy to change the arrangement state of liquid crystal molecules by an external action (such as an electric field or a magnetic field). In an actual liquid crystal display device, the behavior of these liquid crystal molecules is viewed macroscopically, and the arrangement is controlled by the action of an electric field or the like, thereby changing the optical characteristics to realize display.

Conventionally, as a liquid crystal alignment mode used in a transmission type liquid crystal display device, a TN mode (TN liquid crystal mode) in which the alignment of liquid crystal molecules is twisted by 90 ° from the light incident direction to the light emitting direction is used. It was common to do.

In a TN mode liquid crystal display device, a process such as rubbing is performed after forming an alignment film in order to determine the alignment direction of the liquid crystal. The rubbing directions of the upper and lower substrates are configured to be orthogonal. By injecting a liquid crystal material mixed with a chiral material that determines the rotation direction of the twist between the substrates, a liquid crystal display device that twists in a predetermined direction is formed.

At this time, the liquid crystal molecules in the liquid crystal are arranged with their long axes parallel to the substrate surface so as to have the most stable arrangement in terms of energy, and are aligned on the substrate surface depending on the rubbing conditions and the material of the alignment film. On the other hand, they are arranged at an angle of several degrees to about 10 degrees.

This angle is called a pretilt angle, and by securing this angle, the arrangement of the liquid crystal molecules at both ends of the major axis at the time of application of an electric field is deformed by aligning predetermined ends. Thereby, the orientation during operation becomes continuous, and it is possible to prevent an orientation defect such as a reverse tilt domain during display.

In a liquid crystal display device employing the TN mode,
Polarizing plates are arranged on the entrance and exit sides of the liquid crystal panel so that their polarization axes are orthogonal. Here, the polarizing plate has a transmission axis for light and an absorption axis orthogonal thereto.

When no electric field for operating the liquid crystal is applied, the liquid crystal maintains the initial twist alignment. Let us consider a case where light is incident from the outside.

Light passing through the first polarizing plate becomes linearly polarized light, and this light is incident on the liquid crystal panel. This light travels through the liquid crystal while maintaining its polarization state, but when it leaves the liquid crystal layer due to its optical rotation, the polarization axis is rotated by 90 ° and output. That is, it is linearly polarized light twisted by 90 ° with respect to the axis of the incident light. This linearly polarized light is incident on the second polarizing plate. At this time, because it matches the transmission axis of the second polarizing plate,
Light passes through the second polarizer to a "bright" state.

Next, consider the case where an electric field is applied to the liquid crystal of the liquid crystal display device.

When an electric field is applied between the counter electrode and the pixel electrode, the liquid crystal molecules are arranged almost perpendicular to the substrate except for the state near the interface of the substrate. Light can pass while maintaining its properties.

For this reason, the linearly polarized light that has entered the liquid crystal panel through the first polarizing plate is emitted while maintaining its properties. This outgoing light coincides with the absorption axis of the second polarizing plate and is absorbed here to obtain a "dark" state.

However, this TN mode has a problem that the visual field characteristics are poor. Outside the specific viewing angle range, a phenomenon occurs in which the contrast characteristic is extremely deteriorated and the gradation is inverted.

This is because when the alignment is deformed by an electric field so that the alignment state of the liquid crystal molecules is perpendicular to the substrate surface, the distance of light traveling through the liquid crystal medium and the distance depending on the angle and azimuth at which the observer looks at the liquid crystal panel. This is because the refractive index during the passage of light changes, so that light that is optically modulated differently is seen.

In the TN mode, the liquid crystal near the substrate interface receives a strong alignment regulating force, and the initial alignment state is almost maintained in this vicinity. For this reason, even if a considerably high saturation voltage of the liquid crystal of 5 V or more is applied, the liquid crystal does not become vertical in the vicinity.

These factors are known as factors that narrow the viewing characteristics of the TN mode.

Targeting the monitor market for personal computers, efforts are being made to develop liquid crystal monitors that can replace CRTs. However, it is difficult to say that the performance of the current liquid crystal display mode represented by the TN mode is sufficient to realize this. The biggest difficulty of the TN mode is the viewing angle characteristics. In particular, for a large screen, improvement of the viewing angle characteristics is desired.

As a liquid crystal display mode which can solve this problem, a vertical alignment type liquid crystal mode has been developed. This is a liquid crystal display mode in which the initial alignment of the liquid crystal is perpendicular to the substrate.
As the liquid crystal mode of the vertical alignment type, a liquid crystal having a negative dielectric anisotropy is used. This liquid crystal can be called a negative liquid crystal. Also in this case, display is realized by applying an electric field between the electrodes on both substrates.

In the vertical alignment type liquid crystal mode, the initial alignment state is substantially perpendicular to the substrate surface including the bulk portion from the substrate interface, so that the "dark" state and the quality of black are high. , High contrast can be realized. Moreover, since it is not affected by the vicinity of the interface unlike the TN mode,
The viewing characteristics are improved.

However, in the black or halftone display, as in the TN mode, the distance of light traveling through the liquid crystal medium and the light exiting from a path having a different refractive index vary depending on the angle and azimuth at which the observer views the liquid crystal display device. There is no difference in viewing the emitted light, and the visual field characteristics are not sufficient.

For this reason, there has been known a method of improving the viewing angle by forming a plurality of alignment states in a pixel. A method of forming a multi-domain by repeating rubbing in different directions after patterning a plurality of times while masking with a resist or the like is used (FPD Intelligence 199).
8, 5, p79).

In a liquid crystal display mode utilizing optical rotation such as a TN mode, the alignment control by rubbing as described above is generally performed. Although there is an increase in the number of steps of repeating the processes of resist coating, patterning, and rubbing a plurality of times, the advantage is that it can be easily applied as an extension of the conventional process.

A similar method can be used for the alignment control in the vertical alignment type liquid crystal mode.

However, since the liquid crystal display mode uses birefringence, a slight variation in the pretilt angle is noticeable as a variation in the amount of transmitted or reflected light. Due to the slight difference in the contact of the hair tips during rubbing, there is a problem that streak-like display unevenness is likely to occur.

In particular, in the case of enlarging and projecting with a projection type liquid crystal display device, an important issue is how to control the alignment so as to suppress streaky display unevenness in halftone display.

Even a direct-view type liquid crystal display device has this problem to some extent. Therefore, the process of repeating patterning and rubbing a plurality of times to improve the viewing angle is not a very good control method under the current conditions of the alignment film and the rubbing cloth.

The rubbing itself is a source of dust due to the process of rubbing the surface of the alignment film on the substrate with soft hair. Further, it is necessary to take sufficient measures against stress and destruction of elements on a substrate due to generation of static electricity.

In the vertical alignment type liquid crystal mode, if the alignment film is not rubbed, the pretilt angle of the liquid crystal is not determined in one direction, and disclination occurs when an electric field is applied to the liquid crystal display device.

For this reason, a method of realizing uniform alignment and aligning the liquid crystal without performing rubbing is generally sought, but this is a more urgent problem, especially in a vertical alignment type liquid crystal mode.

As a solution to this, for example, ““ Devel
opment of a Simple Processto Fabricate High-Qual
ity TFT-LCDs ”Koma et al., SID 96 Digest, Vol.XXVII, P-
39, 1996, pp. 558-561, discloses a means for providing a slit in an electrode to orient using an electric field gradient.

Further, a new alignment technique capable of withstanding mass production of a vertical alignment type liquid crystal mode has been developed. FIG. 33 shows the basic structure. For example, "" A Super-High-Image-Quality
Multi-Domain Vertical Alignment LCD by New Rubbin
g-Less Technology ”Takeda et al., SID98 DIGEST, Vol.X
In XIX, 41.1, 1998, pp1077-1080, a structure is formed on a substrate, and physical parameters such as the slope, spacing, and height of the surface of the structure in contact with the liquid crystal are adjusted. Means for manufacturing a liquid crystal display device by controlling the orientation by combining the action of an electric field depending on the ratio is disclosed. By using this new liquid crystal display mode, a viewing characteristic of 160 ° or more is realized.

As shown in FIG. 33, the pattern of the protrusions 5 finely processed as a structure on the ITO film 3 (transparent conductive film) of the active matrix substrate 1 and the counter substrate 2 determines the tilt direction of the liquid crystal molecules. This eliminates the need for a rubbing step for the alignment film 4. The liquid crystal 5 (negative liquid crystal) having negative dielectric anisotropy is automatically aligned by the pattern of the projections 5. (A) shows the orientation state of the liquid crystal when no electric field is applied (Off state), and (b) shows the orientation state of the liquid crystal when the electric field is applied (On state).

However, in the above method, the rubbing step of the alignment film is not required, but a complicated additional process for aligning the liquid crystal is required.

[0038]

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems, and to realize alignment of liquid crystal by utilizing a structure at the time of manufacturing a liquid crystal panel. Provided are a multi-domain vertical alignment type liquid crystal display device having a small variation in interval (cell gap unevenness) and a method for manufacturing the same.

The process can be simplified with a structure capable of reducing a rubbing step or the like as a source of dust without adding a special process. Further, the field of view characteristics are improved by applying this configuration. This provides a means for providing a product with high display quality and high reliability at a low price.

[0040]

In the liquid crystal display device of the present invention, first, electrodes are provided on each of a pair of substrates at least one of which is a transparent insulating substrate (transparent insulating substrate). Further, an alignment film is provided on the pair of substrates. A gap holding material for keeping the distance between the pair of substrates constant, here a wall-shaped spacer (wall-shaped spacer), with an alignment film provided on a transparent insulating substrate opposed to each other, A liquid crystal display device in which liquid crystal is sandwiched between a pair of substrates is manufactured. The liquid crystal display device is characterized in that the wall-shaped spacer has an inclined side surface to control a pretilt angle of the liquid crystal and to orient the liquid crystal.

The sectional shape of the wall-shaped spacer may be, for example, as shown in FIGS. The wall-shaped spacer is formed on one or both of the opposing and active matrix substrates. Here, a cross section in which attention is paid to either one of the substrates is shown. FIG.
9 (d) to 9 (f), the wall-shaped spacer is shown in FIG.
(C) are formed on the substrate in a state where the cross-sectional shape is upside down (such a state is called reverse taper). FIG.
9 (a) to 9 (f), assuming that the cell gap is d, an acute angle among the angles formed by the substrate surface and the tangent that can be drawn on the inclined side surface corresponding to 50% of the cell gap d. Is defined as a side surface taper angle θ. FIG.
In (a) and (d), the side surface taper angle θ coincides with the angle formed between the substrate surface and the inclined side surface. If the angle between the tangent and the normal to the substrate is α, then θ = 90 ° −α. Therefore,
The liquid crystal is inclined by α from the normal direction of the substrate. Any wall-shaped spacer having a side surface taper angle θ within the range of 75.0 ° to 89.9 ° may be used. However, regarding the orientation of the liquid crystal, the wall-shaped spacers shown in FIGS. 29A and 29D are optimal. Although the side surfaces of FIGS. 29 (b), (c), (e) and (f) can be said to be dented, they may have a bulged shape.

Further, in the liquid crystal display device of the present invention, the liquid crystal is oriented in a certain direction by the inclined side surfaces of the wall-shaped spacer and the shape of the electrode.

As the alignment film, it is preferable to use an alignment film for vertical alignment in which the liquid crystal is aligned perpendicular to the substrate.
In this case, the rubbing step can be omitted.

Further, in the liquid crystal display device of the present invention, after forming a gap holding material for keeping the interval between the substrates constant, here, a wall-shaped spacer, an alignment film is formed on the wall-shaped spacer. Is also good.

The liquid crystal molecules are aligned in a certain direction by using a liquid crystal display device having a wall-shaped spacer having inclined side surfaces as shown in FIGS. The alignment of the liquid crystal molecules in FIGS. 1 to 4 is a schematic diagram when no electric field is applied. Note that the black portions in the liquid crystal molecules indicate the ends of the liquid crystal molecules near the counter substrate.

In the liquid crystal display device of the present invention, a wall-shaped spacer having a trapezoidal cross section is disposed on at least one substrate.
The side taper angle of this trapezoid is from 75.0 ° to 89.9 °.
Preferably, it has an angle of 82 ° to 87 °. When no electric field is applied, the liquid crystal molecules receive a regulating force on the inclined side surface of the wall-shaped spacer, and are oriented substantially parallel to the side surfaces. When an electric field is applied, the liquid crystal molecules are oriented parallel to the substrate surface.

That is, the switching direction of the liquid crystal molecules can be controlled by using the liquid crystal display device in which the wall-shaped spacer having the inclined side surface is formed.

The wall-shaped spacer is made of an organic resin material containing at least one of acrylic, polyimide, polyimide amide, and epoxy, or one of silicon oxide and silicon oxynitride. It is characterized by being an inorganic material composed of these laminated films.

From an industrial point of view, when this manufacturing process is used, the alignment treatment corresponding to the rubbing process can be omitted, and the wall-shaped spacer has the role of maintaining the gap (gap) between the substrates. In addition, the step of dispersing the spacer can be omitted, and the productivity is improved. Further, the liquid crystal display device of the present invention has an advantage that it is possible to predict the occurrence of display unevenness only by inspecting the uniformity of the wall-shaped spacer formed on the substrate.

[0050]

Embodiments of the present invention will be described below with reference to the drawings. The present invention is not limited to these embodiments.

FIG. 1 is a sectional view of the liquid crystal display device according to the first embodiment. FIG. 2 is a cross-sectional view of the liquid crystal display device according to the second embodiment. FIG. 3 is a cross-sectional view of the liquid crystal display device according to the third embodiment. FIG. 4 is a sectional view of the liquid crystal display device according to the fourth embodiment.

FIG. 5 is a top view of the pixel portion shown in FIGS. The liquid crystal display of FIG. 5 cut along the line AA ′ corresponds to FIGS. In FIG. 5, the wall-shaped spacer 8 is shown.
5 and the source electrode 88 are shown. The shape of the wall-shaped spacer 85 seen from the observer is shown in FIGS.
(A) -2, FIG. 5 (b), FIG. 5 (c) -1, FIG. 9 (c)-
2, FIG. 5D and FIG. 5E are possible, but the present embodiment is not limited to these shapes. Also,
In FIG. 5 (a) -1, FIG. 5 (a) -2, and FIG. 5 (d),
The cross section of the spacer cut in parallel with the transparent insulating substrate (transparent insulating substrate) has a stripe shape. On the other hand, FIG.
(C) -1, In FIG. 5 (e), the spacer is branched (has a branch portion). 5 to 9, a wall-shaped spacer 85-1 is provided on a substrate.
2 means that they are formed on the opposing substrates, respectively. Line B indicates one pixel.

FIG. 6 is a top view of the pixel portion shown in FIG. 1 and shows the director of the liquid crystal molecules in the pixel when no voltage is applied. FIGS. 6 (a) -1 and (c) -1 are enlarged views of the vicinity of line B in FIGS. 5 (a) -1 and (c) -1, respectively. 85-1 is a wall-shaped spacer on the substrate;
2 is a wall-shaped spacer 85-2 on the counter substrate. FIG.
FIG. 3 is a top view of the pixel unit in FIG. 2 and shows directors of liquid crystal molecules in the pixel when no voltage is applied. FIGS. 7A-1 and 7C-1 correspond to FIG. 5A, respectively.
FIG. 2 is an enlarged view of the vicinity of line B in FIGS. Reference numeral 85-1 denotes a wall-like spacer having a bottom surface formed on a substrate.
5-2 is a wall-shaped spacer 85-2 on the opposing substrate.
FIG. 8 is a top view of the pixel unit of FIG. 3 and shows directors of liquid crystal molecules in the pixel when no voltage is applied.
FIGS. 8D and 8E show FIGS. 5D and 5E, respectively.
It is an enlarged view near the B line of (e). 85-1 is a wall-shaped spacer on the substrate, and 88 is a source electrode 88.
FIG. 9 is a top view of the pixel unit of FIG. 4 and shows directors of liquid crystal molecules in the pixel when no voltage is applied.
9 (a) -2 and (b) correspond to FIG. 5 (a)-
FIG. 2B is an enlarged view of the vicinity of line B in FIG. 85-1 is a wall-shaped spacer on the substrate, and 85-2 is a wall-shaped spacer 85-2 on the opposing substrate.

In the fifth embodiment, a method for manufacturing a liquid crystal display device is shown in FIGS. In Embodiment 6, a method for manufacturing a liquid crystal display device is shown in FIGS. In Embodiment 7, a method for manufacturing a liquid crystal display device is shown in FIGS.

In the eighth embodiment, a method for crystallizing a semiconductor layer is shown in FIGS.

In the ninth embodiment, FIG. 28 shows a counter substrate including a coloring layer (color filter). Embodiment 1
0, the thin film transistor of the present invention (Thin Fil)
FIGS. 30 to 32 show a semiconductor device incorporating an active matrix type liquid crystal display device using an mTransistor (TFT) circuit.

[Embodiment 1] (Method of Manufacturing Liquid Crystal Display) A method of manufacturing a liquid crystal display of the present invention will be described with reference to FIG. An active matrix substrate 11 and a counter substrate 12 are used to manufacture a liquid crystal display device. The active matrix substrate 11 is a simplified illustration of the active matrix substrate produced in the fifth to eighth embodiments. The counter substrate 12 is an active matrix substrate 11
This is a substrate provided to face.

A transparent conductive film is formed on the opposing substrate 12 and the active matrix substrate 11 as an indium tin oxide alloy (In ₂ O ₃ —SnO ₂ ; ITO),
An O film 17 and an ITO film 13 are formed. In the present embodiment, an ITO film is used for 17 and 13, but any one of 17 and 13 may be transparent and 17 and 13 may be conductive films.

When the liquid crystal display of the present invention is used for a simple matrix type liquid crystal display, the ITO film 1 provided on the opposing substrate 12 and the active matrix substrate 11
7 and the ITO film 13 are formed in a stripe shape so as to be orthogonal to each other.

When the liquid crystal display device of the present invention is used in an active matrix type liquid crystal display device, an ITO film 17 is formed so as to cover the pixel portion of the counter substrate 11, and the active matrix substrate 11 is patterned for each pixel. I
A TO film 13 is formed.

Next, an orientation film 14 is formed on the active matrix substrate 11 and the counter substrate 12, and sintering is performed. The alignment film 14 uses JALS-2021 (manufactured by JSR).
The alignment film 14 is printed on the substrate by flexographic printing.
The thickness of the alignment film 14 is set to be about 80 nm after firing. The orientation film was pre-baked on a hot plate at 80 ° C., and then 1.5 ° C. in a clean oven at 250 ° C.
Bake for hours.

In the present invention, uniform liquid crystal alignment can be obtained without a rubbing step. The rubbing step after forming the alignment film is not performed.

Next, a wall-shaped spacer 15 is formed on the active matrix substrate 11 and the opposing substrate 12 as a gap holding material for keeping a distance between the substrates. First, the wall-shaped spacer 15 is patterned into a predetermined shape and a predetermined position by a photolithography process. Active matrix substrate 1 so that patterning can be performed at a predetermined position.
Markers are provided inside the four corners of the counter substrate 1 and the counter substrate 12, respectively. NN700 (manufactured by JSR) of a material mainly composed of a photosensitive acrylic material as a gap holding material
I use. NN700 is formed on the entire surface of the substrate by a spinner. The film thickness is set to 4.2 μm.
After NN700 is applied and prebaked, exposure is performed with a mask aligner using a mask for patterning. Thereafter, development is performed with CD700 (manufactured by Fuji Film Reorin), and a baking process is performed on the dried substrate at 250 ° C. for 1 hour. As a result, the wall-shaped spacer 1 as shown in FIG.
5 is formed. SEM (Scanning electron microscop)
e) Observation revealed that this height was about 4 μm.

Thereafter, a sealing material (not shown) is provided on the opposite substrate 12 by using a dispense drawing method.

The width of the seal pattern (not shown) formed by the seal material is determined by
It is set to be 1.2 to 1.5 mm. An injection port (not shown) is provided in a part of the seal pattern,
Liquid crystal is injected from the injection port. After applying the sealing material, the sealing material is fired at 90 ° C. for about 0.5 hour.

The active matrix substrate 11 and the counter substrate 12 that have undergone the above steps are bonded together so that the markers provided on both substrates match. A pressure of 0.3 to 1.0 kgf / cm ² is applied to the pair of bonded substrates in a direction perpendicular to the plane of the substrate and over the entire surface of the substrate, and is simultaneously heated in a clean oven at 160 ° C. for about 2 hours by hot pressing. Adhere.

Then, after waiting for the pair of bonded substrates to cool, the scriber and the breaker separate the substrates.

Liquid crystal is injected by a vacuum injection method. The preparation was vacuum pumps panels after cutting into a vacuum vessel, after the inside of the vacuum container in a vacuum state of about 1.33 × 10 ^-5 from 1.33 × 10 ^-7 Pa, the inlet of the negative It is immersed in a liquid crystal dish on which liquid crystal MLC-2038 (manufactured by Merck) having dielectric anisotropy is provided. Liquid crystal MLC having negative dielectric anisotropy
The dielectric constant when the major axis of -2038 is oriented parallel to the electric field is 4.0, and the dielectric constant when the minor axis is oriented parallel to the electric field is 9.0.

Next, when the vacuum chamber in a vacuum state is gradually leaked with nitrogen and returned to the atmospheric pressure, the pressure difference between the atmospheric pressure in the panel and the atmospheric pressure and the action of the liquid crystal capillary action cause the liquid crystal panel to enter the vacuum chamber. The liquid crystal is injected, and the liquid crystal gradually advances from the injection port side to the opposite side to complete the injection step. As shown in FIG. 1, the liquid crystal 16 having a negative dielectric anisotropy has a constant pretilt angle because a wall-shaped spacer is used,
The orientation can be controlled substantially parallel to the inclined side surfaces of the wall-shaped spacer. In FIG. 1, black portions of the liquid crystal 16 having negative dielectric anisotropy indicate that the front ends (end portions) face the counter substrate 12.

When it is confirmed that the inside of the seal pattern on which the seal material is formed is filled with the liquid crystal, both sides of the liquid crystal panel are pressurized. After 15 minutes, excess liquid crystal is wiped off and the injection port ( (Not shown), an ultraviolet curable resin (not shown) is applied, and the pressure is reduced. At that time, the ultraviolet curing resin enters. In this state, UV irradiation (4 to 10 m
(W / cm ² , 120 seconds) to cure the ultraviolet curable resin and seal the injection port.

Next, the liquid crystal adhered to the surface and the end face of the liquid crystal panel is washed with an organic solvent, for example, acetone and ethanol. Thereafter, the liquid crystal is realigned at 130 ° C. for about 0.5 hour.

Thereafter, a flexible printed wiring board (Flexible Pri
nt Circuit (FPC). Next, polarizing plates are attached to both sides of the liquid crystal panel, and a liquid crystal display device is completed.

In the liquid crystal display device of the present embodiment, when no electric field is applied, the liquid crystal molecules are aligned substantially in parallel with the inclined side surface under the influence of the inclined side surface of the wall-shaped spacer. When a voltage is applied, first, liquid crystal molecules near the inclined side surface having a pretilt angle in a direction substantially parallel to the inclined side surface begin to be oriented in parallel with the substrate. And the liquid crystal molecules other than near the inclined side surface are also affected by these liquid crystal molecules,
Try to arrange in the same direction sequentially. Thus, the pixel (A
₁ -A ₁ ') A stable orientation is obtained over the whole. That is, the orientation of the entire display section is controlled by using the wall-shaped spacer.

Therefore, as shown in FIG. 1, since the liquid crystal alignment is symmetrical with respect to the wall-shaped spacer, a multi-domain vertical alignment type liquid crystal display device having a wide viewing angle display can be obtained. Further, by using the wall-shaped spacer, variations in the distance between the substrates, that is, unevenness in the cell gap is reduced.

In the present invention, the acrylic resin is used because the wall-shaped spacer is easily formed. However, the material is not particularly limited as long as the material has a smaller dielectric constant than the liquid crystal. The acrylic resin NN700 used in the present invention has a dielectric constant of 3.4. When the upper surface has a flat shape, the mechanical strength of the liquid crystal display device can be secured when the opposing substrates are overlapped. Further, when a spacer containing a substance having a light-shielding function such as a black resin is used in the normally white mode, light leakage from the spacer itself is eliminated, and the contrast is improved. In the wall-shaped spacer in this specification, the upper surface refers to one surface of a wall-shaped spacer farthest from a substrate surface (a surface on an active matrix substrate or a counter substrate) when the wall-shaped spacer is formed. On the other hand, the bottom surface described later refers to one surface of the wall-shaped spacer closest to the substrate surface (the surface on the active matrix substrate or the counter substrate) when the wall-shaped spacer is formed.

As a preliminary experiment, NN700 (thickness: 4 μm) was applied to two glass substrates on which an ITO film had been formed and rubbed, and then the two glass substrates were sealed with a sealing material so that the rubbing directions were antiparallel. Laminated and cut. Liquid crystal MLC-2038 having negative dielectric anisotropy
(Manufactured by Merck) was injected through the injection port, and the pretilt angle was measured to be 1.8 to 2.7 °. Therefore, NN
In the vicinity of the surface of 700, it was confirmed that there was an alignment regulating force acting so that the major axis direction of the liquid crystal molecules was substantially parallel to the surface.

The shape of the wall-shaped spacer 85 seen from the observer of this embodiment is shown in FIGS. 5A-1 and 5C-1. In FIG. 6A-1, the wall-shaped spacer 85-1 and the wall-shaped spacer 85-2 can divide the orientation into two. Further, in FIG. 6C-1, the wall-shaped spacer 8
5-1 and the wall-shaped spacer 85-2 have branches.
That is, since the light is branched, the orientation can be divided into two or more (multi-divided).

In this embodiment, the liquid crystal is aligned by controlling the pretilt angle of the liquid crystal only by the wall-shaped spacer. However, the combination of the wall-shaped spacer and the slit controls the pretilt angle of the liquid crystal and aligns the liquid crystal. You may.

In this embodiment, the wall-shaped spacers 15 are formed on the active matrix substrate 11 and the counter substrate 12, respectively. However, as shown in FIG. 1, the oblique sides of the wall-shaped spacers formed opposite to each other are substantially parallel. , A wall-shaped spacer may be formed on either the active matrix substrate 11 or the counter substrate 12.

In the present embodiment, the photolithography step is formed, but a step of exposing from the back side of the negative resin applied surface on the substrate may be used. A negative resin is a photosensitive material which is polymerized or cross-linked by irradiation with light or the like, becomes insoluble or hardly soluble in a developer, and remains on the surface of the substrate until after development. Further, even when a dry etching method or a plasma etching method is used, a wall-shaped spacer having the above-described shape can be formed.

In this embodiment, the wall-shaped spacer is used. However, the liquid crystal present around the column-shaped spacer may be multi-domain aligned using the columnar spacer.

In this embodiment, the sealing material is applied to the counter substrate 12 side, but the sealing material may be applied to the active matrix substrate 11 side.

In this embodiment, the alignment film JAL made by JSR is used.
Although S-2021 was used, there is no particular limitation as long as it is an alignment film for normal vertical alignment.

In the present embodiment, the dispensing method is used when applying the sealing material, but a screen printing method may be used.

In this embodiment, the immersion method is used as the liquid crystal injection method, but a drop injection method in which liquid crystal is injected from the injection port of the seal may be used. Alternatively, an ultraviolet-curing resin may be used as a seal, a liquid crystal may be applied between two substrates, and the substrates may be overlapped and sealed. This injection method is called a lamination method.

In the present embodiment, an epoxy resin containing ethyl cellosolve and a phenol curing agent are used as materials for the sealing material. However, the sealing resin is not particularly limited as long as it is an ultraviolet-curing or thermosetting sealing resin. .

The liquid crystal display device of the present invention is applicable to both an active matrix type liquid crystal display device and a simple matrix type liquid crystal display device.

[Embodiment 2] In the embodiment 1, the wall-shaped spacer is formed after the alignment film is applied. In the present embodiment, the wall-shaped spacer is formed and then the alignment film is applied. Such a liquid crystal display device is obtained.

An active matrix substrate 21 provided with an ITO film 23 and a counter substrate 2 provided with an ITO film 27
2 is a wall-shaped spacer 25 as a gap holding material.
To form After that, an alignment film 24 is applied to the active matrix substrate 21 and the counter substrate 22. In the present embodiment, the ITO films are used for 27 and 23, but any one of 27 and 23 may be transparent and 27 and 23 may be conductive films. After that, an alignment film 24 is applied to the active matrix substrate 21 and the counter substrate 22.

The alignment film 2 of the active matrix substrate 21
4 and the alignment film 24 of the counter substrate 22 are opposed to each other.
By filling a liquid crystal 26 having a negative dielectric anisotropy between a pair of substrates, a liquid crystal display device as shown in FIG. 2 is obtained. The alignment film 28 applied to the wall-shaped spacer 25 on the active matrix substrate 21 and the alignment film 28 applied to the wall-shaped spacer 25 on the counter substrate 22 form a liquid crystal 46 having a negative dielectric anisotropy. The orientation can be controlled.

In this embodiment, the wall-shaped spacer 25 is used.
Are formed on the active matrix substrate 21 and the opposing substrate 22, and the shape of the wall-like spacer 85 as viewed from the observer is preferably as shown in FIGS. FIG.
In (a) -1, the orientation can be divided into two by the wall-shaped spacer 85-1 and the wall-shaped spacer 85-2. Further, in FIG. 7C-1, since the wall-shaped spacer 85-1 and the wall-shaped spacer 85-2 have branches, that is _{, are} branched _{, the} orientation is divided into two or more (multi-division). ) Becomes possible.

In this liquid crystal display device, when no voltage is applied, if the alignment film 24 is present on the wall-shaped spacer 25, the liquid crystal molecules are aligned almost perpendicular to the alignment film. When a voltage is applied, first, liquid crystal molecules near the wall-shaped spacer begin to be oriented in parallel with the substrate. Then, liquid crystal molecules other than the vicinity of the inclined side surface are also affected by these liquid crystal molecules, and try to be sequentially arranged in the same direction. Thus, a stable alignment can be obtained over the entire pixel portion (A ₂ -A ₂ ′). That is, by using the wall-shaped spacer 25, the orientation of the entire display unit is controlled.

[Embodiment 3] A liquid crystal display device as shown in FIG. 3 is obtained in substantially the same manner as in Embodiment 1. In the present embodiment, the liquid crystal having negative dielectric anisotropy can be aligned in a certain direction by the alignment film applied on the inclined side surface of the wall-shaped spacer and the side surface of the source wiring (source electrode). .

As shown in FIG. 3, first, the active matrix substrate 3 provided with the ITO film 33 and the source wiring 38 is provided.
An alignment film 34 is formed on the counter substrate 32 provided with the first electrode 1 and the ITO electrode 33. In this embodiment, the ITO films are used for 37 and 33, but any one of 37 and 33 may be transparent and 37 and 33 may be conductive films. Further, a wall-shaped spacer 35 is formed as a gap holding material on the alignment film 34 applied on the ITO electrode 33 of the active matrix substrate 31.

The alignment film 3 of the active matrix substrate 31
4 and the alignment film 34 of the counter substrate 32 are opposed to each other.
By filling a liquid crystal 36 having a negative dielectric anisotropy between a pair of substrates, a liquid crystal display device as shown in FIG. 3 is obtained. The inclined side surface of the wall-shaped spacer 35 and the source wiring 3
The liquid crystal 36 having a negative dielectric anisotropy can be controlled in a certain direction by the alignment film applied to the side surface of No. 8.

The wall-like spacer 85 seen from the observer
FIG. 5D and FIG. 5E show an example of the shape of FIG. In FIG. 8D, the orientation can be divided into two by the source wiring 88 and the wall-shaped spacer 85-1. Since the liquid crystal molecules are symmetrically aligned with respect to the wall-shaped spacer, a viewing angle characteristic symmetrical with respect to the source line can be obtained. further,
In FIG. 8E, since the wall-shaped spacer 85-1 has a branch portion, that is, is branched, the orientation can be divided into two or more (multi-partition).

In the present embodiment, in order for the liquid crystal molecules to have a pretilt in a certain direction, it is desirable to form a wall-shaped spacer 35 on the active matrix substrate 31. When the wall-shaped spacer 35 is provided on the counter substrate 32, it is desirable that the bottom surface of the wall-shaped spacer be smaller than the upper surface by etching.

In the liquid crystal display device of the present embodiment, when no voltage is applied, the source wiring 38 and the wall of the source wiring 38 are affected by the inclined side surface of the wall-shaped spacer 35 and the alignment film 34 applied to the side surface of the source wiring 38. The liquid crystal molecules in the region sandwiched between the spacers 35 are inclined to the same side with respect to the normal direction of the substrate, although there is a difference in pretilt between the vicinity of the source wiring 38 and the vicinity of the wall-shaped spacer 35.

When a voltage is applied, first, the wall-shaped spacer 3
The liquid crystal molecules near the inclined side surface 5 and the liquid crystal molecules near the source wiring 38 begin to be aligned in parallel with the substrate. The liquid crystal molecules other than the vicinity of the inclined side surface of the wall-shaped spacer 35 are also affected by these liquid crystal molecules, and try to arrange them sequentially in the same direction. Thus, a stable liquid crystal alignment can be obtained over the entire pixel portion (A ₃ -A ₃ ′).

As described above, the liquid crystal 3 having a negative dielectric anisotropy is formed by the alignment film applied on the inclined side surface of the wall-shaped spacer 35 and the side surface of the convex portion formed by the source wiring 38.
6 can be oriented in a certain direction.

[Embodiment 4] In the embodiment 1, the adjacent wall-shaped spacers are arranged so that the top surface and the bottom surface are alternately arranged. However, as shown in FIG. A multi-domain vertical alignment type liquid crystal display device with a wide viewing angle display can be obtained even when the top and bottom portions are arranged so as to be adjacent to each other.

In FIG. 4, first, an alignment film 44 is formed on each of an active matrix substrate 41 provided with an ITO film 43 and a source wiring (source electrode) 48 and a counter substrate 42 provided with an ITO film 47. In this embodiment, the ITO films are used for 47 and 43, but any one of 47 and 43 may be transparent and 47 and 43 may be conductive films. Further, a wall-shaped spacer 45 is formed as a gap holding material on the alignment film 44 applied to the ITO electrode 43 and the source wiring 48. With the alignment film 44 of the active matrix substrate 41 and the alignment film 44 of the counter substrate 42 facing each other, a liquid crystal 4 having a negative dielectric anisotropy is provided between the pair of substrates.
By satisfying 6, the liquid crystal display device as shown in FIG. 4 is obtained. When no voltage is applied, the active matrix substrate 41
The orientation of the liquid crystal 46 having a negative dielectric anisotropy is controlled in a certain direction by the side surface of the wall-shaped spacer 45 formed thereon.

The wall-like spacer 85 seen from the observer
5 (a) -2, 5 (b), 9 (c)-
2 (unlike FIG. 5C-1, all wall-shaped spacers are 85-1). Fig. 9 (a) -2
In this case, it is possible to divide the orientation into two by the adjacent wall-shaped spacer 85-1. Further, in FIG. 9C-2,
Since the wall-shaped spacer 85-1 has a branch portion, that is, is branched, the orientation can be divided into two or more. Further, in FIG. 9B, the alignment can be divided into four parts. When the liquid crystal display device of the present embodiment is used, a boundary surface of the liquid crystal is generated between the wall-shaped spacers.

In particular, a laminate injection method is used for a liquid crystal display device having a wall-shaped spacer 85 having the shape shown in FIG. 5B. The wall-shaped spacer 85-1 having the shape shown in FIG.
Is an example in which the wall-shaped spacer having the shape shown in FIG. 5B is improved so that the immersion method can be used.

In the liquid crystal display device of the present embodiment, when no voltage is applied, the liquid crystal molecules on the wall-shaped spacer 45 are oriented substantially parallel to the wall-shaped spacer 45. When a voltage is applied, first, liquid crystal molecules near the wall-shaped spacer 45 begin to be oriented parallel to the substrate. Then, liquid crystal molecules other than the vicinity of the inclined side surface are also affected by these liquid crystal molecules, and try to be sequentially arranged in the same direction. Thus, the pixel portion (A ₄ -A ₄ ′)
A stable orientation is obtained throughout. That is, the orientation of the entire display unit is controlled by using the wall-shaped spacer 45.

In the present embodiment, the source wiring having the same height as the ITO film is selected as the place where the wall-shaped spacer is formed, but the present invention is not particularly limited to this.

In this embodiment, Embodiments 1 and 2
In comparison, the wall-shaped spacer 45 may be formed on either the active matrix substrate 41 or the counter substrate 42, so that the mask for the wall-shaped spacer can be reduced, and the process can be simplified.

[Embodiment 5] (Method of Manufacturing Liquid Crystal Display) A method of manufacturing a transmission type liquid crystal display used in the present invention is shown in FIG.
This will be described with reference to FIGS. 10 to 15
Are assigned the same reference numerals. A chain line CC ′ in FIG. 15 corresponds to a cross-sectional view cut along a chain line CC ′ in FIG. A dashed line DD ′ in FIG. 15 corresponds to a cross-sectional view taken along a dashed line DD ′ in FIG.

The arrangement of the wall-shaped spacers in this embodiment corresponds to that shown in FIG. Further, as shown in FIG. 1, after forming the alignment film, the wall-shaped spacer is formed.
Chain line A ₁ -A ₁ in Figure 14 'is a chain line A ₁ -A ₁ in Figure 1' corresponds with. FIG. 1 illustrates elements that affect the alignment of the liquid crystal.

As shown in FIG. 15 of a top view, the active matrix substrate has gate wirings arranged in the row direction,
It includes a source wiring 439 arranged in a column direction, a pixel portion having a pixel TFT near an intersection of a gate wiring and a source wiring, and a driver circuit having an n-channel TFT and a p-channel TFT. The gate wiring refers to a gate wiring 471 arranged in a row direction and gate electrodes 436 and 438 electrically connected by a contact hole.

In FIG. 15, a source wiring 439, a gate electrode 436, and a gate electrode 438 are formed in the same layer. The gate electrode 436 and the gate electrode 438 also serve as capacitance electrodes. Source wiring 439 and gate electrode 436,
A first interlayer insulating film (464 in FIG. 12) is formed in contact with gate electrode 438. A second interlayer insulating film (465 in FIG. 12) is formed on the first interlayer insulating film. Further, a gate wiring 47 is formed on the second interlayer insulating film.
1, a capacitor connection electrode 473, a drain electrode 472, and a source connection electrode 470 are formed.

For a transmission type liquid crystal display device, a pixel electrode 474 is formed so as to overlap with the drain electrode 472. The pixel electrode 474 is made of a transparent conductive film. The pixel electrode 474 is formed so as to overlap the capacitor connection electrode 473 and the drain electrode 472.

The gate wiring 471 is connected to the gate electrode 436,
The gate electrode 438 is provided via a first interlayer insulating film and a second interlayer insulating film. In the pixel structure in FIG. 15, the gate electrode 436 and the gate electrode 4
Reference numeral 38 denotes an island-shaped pattern, which not only serves as a gate electrode but also serves as one of electrodes constituting a storage capacitor of an adjacent pixel as described above.

That is, the storage capacitance of the pixel electrode 474 uses the insulating film covering the island-shaped semiconductor film 406 as a dielectric. The pixel electrode 474 and the capacitor connection electrode 473 are electrically connected. Further, the capacitance connection electrode 473 and the island-shaped semiconductor film 406 are electrically connected. Thus, the island-shaped semiconductor film 406 functions as a first capacitance electrode. The island-shaped gate electrodes 436 and 438 function as second capacitor electrodes.

Between the pixels, the edge of the pixel electrode 474 is mainly overlapped with the source wiring 439, so that light can be shielded.

The manufacturing process of the active matrix substrate of the present embodiment will be described with reference to the sectional views of FIGS.

As shown in FIG. 10A, a silicon oxide film is formed on a substrate 400 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass, or aluminoborosilicate glass. Then, a base film 401 and a base film 402 made of an insulating film such as a silicon nitride film or a silicon oxynitride film are formed. For example, SiH ₄ , NH ₃ , N ₂ by plasma CVD
The silicon oxynitride film 401 made of O
00 nm (preferably 50 to 100 nm).
A silicon oxynitride hydride film 402 made of iH ₄ and N ₂ O is formed to a thickness of 50 to 200 nm (preferably 100 to 150 nm).
(nm). In this embodiment, the base film is 2
Although shown as a layered structure, it may be formed as a single layer of the insulating film or a structure in which two or more layers are stacked.

The island-like semiconductor films 403 to 406 are formed of a crystalline semiconductor film formed by using a semiconductor film having an amorphous structure by a laser crystallization method or a known thermal crystallization method. The thickness of the island-shaped semiconductor films 403 to 406 is 25 to 80 nm.
(Preferably 30 to 60 nm). The material of the crystalline semiconductor film is not limited, but is preferably formed of silicon or a silicon germanium (SiGe) alloy.

In order to form a crystalline semiconductor film by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or a YVO ₄ laser is used.
In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The conditions for crystallization are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is set to 30 Hz, and the laser energy density is set to 100 to 400 mJ / cm ² (typically, 20 to 400 mJ / cm ² ).
0 to 300 mJ / cm ² ). When a YAG laser is used, its second harmonic is used and a pulse oscillation frequency of 1 is used.
-10kHz, laser energy density 300 ~
600 mJ / cm ² may (typically 350~500mJ / cm ²⁾ to. And a width of 100 to 1000 μm, for example 400
A laser beam condensed linearly in μm is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser beam at this time is set to 80 to 98%.

As another method for manufacturing a crystalline semiconductor film for forming an active layer of a TFT of an active matrix substrate, the crystalline semiconductor film is crystallized using a catalyst element disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652. There is a way to do that. Details of the crystallization method using a catalytic element will be described in Embodiment 8 with reference to FIG.

Next, a gate insulating film 407 covering the island-like semiconductor films 403 to 406 is formed. Gate insulating film 407
Uses a plasma CVD method or a sputtering method and has a thickness of 4
The insulating film containing silicon is formed to have a thickness of 0 to 150 nm. In this embodiment, the insulating film is formed using a 120-nm-thick silicon oxynitride film. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ are mixed by a plasma CVD method, the reaction pressure is 40 Pa, and the substrate temperature is 300 to 4.
00 ° C., high frequency (13.56 MHz) power density 0.5
It can be formed by discharging at 0.8 W / cm ² . The silicon oxide film thus manufactured is
Good characteristics as a gate insulating film can be obtained by thermal annealing at 0 to 500 ° C.

Then, a first conductive film 408 and a second conductive film 409 for forming a gate electrode are formed over the gate insulating film 407. In the present embodiment, the first conductive film 4
08 is formed of TaN to a thickness of 50 to 100 nm, and the second conductive film 409 is formed of W to a thickness of 100 to 300 nm.

When a W film is formed, it is formed by a sputtering method using W as a target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to lower the resistance in order to use it as a gate electrode.
It is desirable to set the resistance to Ωcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when the W film contains a large amount of impurity elements such as oxygen, crystallization is inhibited and the resistance is increased. Thus, in the case of using the sputtering method, a W target having a purity of 99.9999% is used, and further, the W film is formed with sufficient care so as not to mix impurities from the gas phase during film formation. 9-20μ
Ωcm can be realized.

In this embodiment, the first conductive film 40
8 was TaN and the second conductive film 409 was W, but each was formed of an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the above element as a main component. May be. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. As a combination other than this embodiment, the first conductive film is formed of tantalum nitride (TaN),
The second conductive film is formed of Al, the first conductive film is formed of tantalum nitride (TaN), and the second conductive film is formed of Cu.
And the like.

Next, resist masks 411 to 41 are used.
6, and a first etching process (FIG. 10B) for forming electrodes and wirings is performed. In the present embodiment, I
Using a CP (Inductively Coupled Plasma) etching method, CF ₄ and Cl ₂ are mixed as an etching gas, and 500 W is applied to a coil-type electrode at a pressure of 1 Pa.
Of RF (13.56 MHz) power to generate plasma. 100W RF (13.
56MHz) Power is applied and a substantially negative self-bias voltage is applied. When CF ₄ and Cl ₂ are mixed, both the W film and the Ta film are etched to the same extent.

Under the above-mentioned etching conditions, by making the shape of the resist mask suitable, the ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes a taper shape with an angle of 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased by about 10 to 20%. Since the selectivity of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the exposed surface of the silicon oxynitride film is etched by about 20 to 50 nm by the over-etching process. Thus, the first-shaped conductive layers 420 to 425 (first conductive layers 420 a to 425 a) including the first conductive layer and the second conductive layer are formed by the first etching process.
And second conductive layers 420b to 425b). 41
Reference numeral 8 denotes a gate insulating film, which is a first shape conductive layer 420 to
The region not covered with 425 is etched by about 20 to 50 nm to form a thinned region.

Then, a second etching process is performed as shown in FIG. Similarly, using an ICP etching method, CF ₄ , Cl ₂ and O ₂ are mixed in an etching gas,
RF power of 500 W (13.
(56 MHz) to generate plasma. An RF (13.56 MHz) power of 50 W is applied to the substrate side (sample stage), and a lower self-bias voltage is applied than in the first etching process. Under such conditions, the W film is anisotropically etched, and the first conductive layer, TaN, is anisotropically etched at a lower etching rate than the second conductive layers 434 to 439 (first conductive layer). Conductive layers 434a to 439
a and second conductive layers 434b to 439b). 4
Reference numeral 26 denotes a gate insulating film, which is a second shape conductive layer 434.
The region not covered by 439 is further etched by about 20 to 50 nm to form a thinned area.

Then, a first doping process is performed, and n
An impurity element for imparting a mold is added at a low concentration at an accelerated rate. The doping may be performed by an ion doping method or an ion implantation method. Elements belonging to Group 15 as impurity elements imparting n-type, typically phosphorus (P) or arsenic (A
s), but phosphorus (P) is used here. In this case, the conductive layers 434 to 438 serve as a mask for the impurity element imparting n-type, and the first impurity regions 428 to 432 are formed in a self-aligned manner. In this specification, the impurity regions covered with TaN, which are the first conductive layers (434a to 438a), are specified as first impurity regions (428 to 432), and the first conductive layers (434a to 438a) are specified. T
The impurity regions not covered by aN are specified as second impurity regions (441 to 445). First impurity region (4
28 to 432) is 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms /
made to be cm ^3.

As shown in FIG. 11A, using TaN as the first conductive layers (434a to 439a) as a mask,
The gate insulating film was etched. A region where the first conductive layer and the gate insulating film do not overlap is removed by etching. Thereafter, the resists 411 to 416 shown in FIG. 10B were stripped with a stripping solution containing NMP as a main component.

Then, as shown in FIG. 11B, resists 446 to 448 are formed, and a second doping process is performed. In this case, an impurity element imparting n-type is added to the island-shaped semiconductor film at a low concentration and at a high acceleration. Subsequently, an impurity element imparting n-type is added to the island-shaped semiconductor film at a high concentration and a low acceleration. At this time, the pixel TFT and the p-channel type TFT are covered with the resist mask. Thus, third impurity regions 450 to 458 are formed as new impurity regions outside the second impurity regions (441 to 445 shown in FIG. 10C) formed in the island-shaped semiconductor film. In the region to which the n-type impurity element is added via the gate insulating film, fourth impurity regions (466 to 467) having different impurity concentrations are formed.

At this stage, the first impurity region (428,
430, 432) is 2 × 10 ¹⁶~ 5 × 10¹⁹atom
s / cm^ThreeSo that The second impurity region (44
0, 441, 443, 445) is 1 × 10¹⁶~ 5
× 10¹⁸atoms / cm^ThreeSo that Third impurity area
The concentration of the n-type impurity in the region (450 to 458) is 1 × 10 ²⁰
~ 1 × 10^{twenty two}atoms / cm^ThreeSo that The fourth impurity
The concentration of the n-type impurity in the object region (466 to 467) is the third
Between the concentration of the impurity region and the concentration of the second impurity region.
You.

Then, as shown in FIG. 11C, after removing the resists 446 to 448, a resist 459 and a resist 460 are formed. Resist 459, Resist 460
Is used as a mask to perform a third doping process. Thus, the p-type impurity element is injected into the island-shaped semiconductor film to form a p-channel TFT. Island-like semiconductor film 40
Third, fifth impurity regions 460 to 461 and sixth impurity regions 462 to 463 are formed. At this time, the island-shaped semiconductor layers 404, 405, and 406 forming the n-channel TFT are formed.
Is coated over the entire surface using the resists 459 to 460 as a mask. The fifth impurity regions 460 to 461 and the sixth impurity regions 462 to 463 are doped with phosphorus at different concentrations. In this embodiment, an ion doping method using diborane (B ₂ H ₆ ) is used. The concentration of the impurity element imparting p-type is set to an amount sufficient to invert the n-channel TFT to the p-channel TFT. At this time, when the distance between the channel region and the fifth impurity regions 460 to 461 is about 0.2 μm, the impurity may be doped at a high concentration and at a low acceleration. When the distance between the channel region and the fifth impurity regions 460 to 461 is large, low-concentration high-acceleration impurity doping and high-concentration low-acceleration impurity doping may be used in combination.

Through the above steps, an impurity region is formed in each island-like semiconductor film. The conductive layers 434 to 436 and 438 overlapping with the island-shaped semiconductor film function as a gate electrode of the TFT. 439 functions as a source wiring and 437 functions as a capacitor wiring.

Next, as shown in FIG. 12A, a step of activating the impurity element added to each island-like semiconductor film is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, laser annealing method,
Alternatively, a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 1pp
The heat treatment is performed at 400 to 700 ° C., typically 500 to 600 ° C. in a nitrogen atmosphere of m or less, preferably 0.1 ppm or less. In this embodiment, the heat treatment is performed at 500 ° C. for 4 hours. However, when the wiring material used for 434 to 440 is weak to heat, it is preferable to activate after forming an interlayer insulating film (mainly containing silicon) to protect the wiring and the like.

Further, a heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the island-like semiconductor layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. As another means of hydrogenation,
Plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Then, as shown in FIG. 12B, a first interlayer insulating film 464 is formed on the gate electrode and the gate insulating film.
To form The first interlayer insulating film may be formed using a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a stacked film combining these. In any case, the first interlayer insulating film 464 is formed from an inorganic insulating material. The thickness of the first interlayer insulating film 464 is 100 to 200 nm.

Here, when a silicon oxide film is used, tetraethyl orthosilicate is formed by a plasma CVD method.
e: TEOS) and O ₂ were mixed, and the reaction pressure was 40 Pa,
A substrate temperature of 300 to 400 ° C. and a high frequency (176 MH)
z) It can be formed by discharging at a power density of 0.5 to 0.8 W / cm ² . In the case of using a silicon oxynitride film, a silicon oxynitride film formed from SiH ₄ , N ₂ O, and NH ₃ by a plasma CVD method, or SiH ₄ , N ₂ O
May be formed using a silicon oxynitride film formed from the above.
The manufacturing conditions in this case are a reaction pressure of 20 to 200 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (60 MHz) power density of 0.1 to 1.0 W / cm ² . Alternatively, a hydrogenated silicon oxynitride film formed from SiH ₄ , N ₂ O, and H ₂ may be used. Similarly, a silicon nitride film can be formed from SiH ₄ and NH ₃ by a plasma CVD method. In this embodiment, the first interlayer insulating film 464 is formed with a thickness of 100 to 200 nm from a silicon oxynitride film.

Thereafter, a second interlayer insulating film 465 made of an organic insulating material is formed with an average thickness of 1.0 to 2.0 μm. As the organic resin material, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. For example, in the case of using a polyimide that is thermally polymerized after being applied to a substrate, it is formed by firing at 300 ° C. in a clean oven. In the case of using acrylic, a two-component type is used, and after mixing the main material and the curing agent, the whole surface is applied using a spinner and then pre-heated at 80 ° C. for 60 seconds on a hot plate. And then 250 ° C in a clean oven
For 60 minutes.

As described above, the surface can be satisfactorily planarized by forming the second interlayer insulating film from the organic insulating material. In addition, since organic resin materials generally have a low dielectric constant, parasitic capacitance can be reduced. But,
Since it is hygroscopic and is not suitable as a protective film, it must be used in combination with a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like formed as the first interlayer insulating film 464 as in this embodiment.

Thereafter, a resist mask having a predetermined pattern is formed using a photomask, and a contact hole reaching a source region or a drain region formed in each of the island-shaped semiconductor films is formed. The formation of the contact hole is performed by a dry etching method. In this case, the second interlayer insulating film 465 made of organic resin material using a mixed gas of CF _4, O _2, He as an etching gas is first etched, then followed by a first etching gas as CF _4, O ₂ Is etched. Further, by switching the etching gas to CHF ₃ and etching the gate insulating film in order to increase the selectivity with respect to the island-shaped semiconductor layer, a contact hole can be formed favorably.

Then, a conductive metal film is formed by a sputtering method or a vacuum evaporation method, a pattern is formed using a resist as a mask by a photomask, and the source wiring 427, the source wiring 467, and the drain wiring 468 to 468 are formed by etching.
469, the drain electrode 472, and the source connection electrode 470
And a capacitor connection electrode 473 and a gate wiring 471 are formed.

Here, the drain electrode 472 functions by being electrically connected to a pixel electrode 474 described later.
The capacitor connection electrode 473 applies a potential to the island-shaped semiconductor layer 406 functioning as an electrode of the storage capacitor 504. Gate wiring 4
Reference numeral 71 has been described in detail with reference to FIG. 15 in a top view, and is electrically connected to the gate electrode 436 and the gate electrode 438 by a contact hole. Note that the storage capacitor 504 of this embodiment is in the same pixel as the pixel electrode 474.

In FIG. 12, a Ti film having a thickness of 50 to 150 nm is formed as a conductive metal film, and a contact is formed with a source region or a drain region of the island-like semiconductor film.
300-400 aluminum (Al) on the i-film
3 nm by forming a Ti film or a titanium nitride (TiN) film with a thickness of 100 to 200 nm.
It has a layer structure. With this configuration, a pixel electrode 4 described later is used.
74 comes into contact with only the Ti film forming the drain electrode 472 and the capacitance connection electrode 473. As a result, it is possible to prevent the reaction between the transparent conductive film and Al.

Thereafter, a transparent conductive film is formed on the entire surface, and a pixel electrode 474 is formed by a patterning process using a photomask and an etching process. Pixel electrode 474
Are formed on the interlayer insulating film 465 and the pixel TFT 503
Are provided so as to overlap with the drain electrode 472 and the capacitance connection electrode 473 to form a connection structure. Thus, the island-shaped semiconductor film 406 functioning as an electrode of the storage capacitor 504
Is supplied with a potential.

The material of the transparent conductive film is indium oxide (I
n ₂ O ₃ ) and indium tin oxide alloy (In ₂ O ₃ —S
nO ₂ ; ITO film) or the like can be formed by a sputtering method, a vacuum evaporation method, or the like. The etching of such a material is performed using a hydrochloric acid-based solution. But,
In particular, since etching of the ITO film easily generates residues,
In order to improve the etching processability, an alloy of indium oxide and zinc oxide (In ₂ O ₃ —ZnO) may be used. The indium oxide zinc oxide alloy has excellent surface smoothness and excellent thermal stability with respect to the ITO film.
Even when Al is used for the capacitor connection wiring 473 and the capacitor 2, a corrosion reaction with Al contacting on the surface can be prevented. Similarly, zinc oxide (ZnO) is a suitable material, and zinc oxide (ZnO: Ga) to which gallium (Ga) is added in order to increase the transmittance and conductivity of visible light can be used.

When hydrogenation is performed in this state, favorable results can be obtained for improving the characteristics of the TFT. For example, 3 ~
The heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 100% hydrogen, or a similar effect may be obtained by using a plasma hydrogenation method. It is desirable that the defect density in the island-shaped semiconductor films 403 to 406 be 10 ¹⁶ / cm ³ or less.
What was necessary was just to give about 1 atomic%.

As described above, the p-channel type TFT 5
01, a driver circuit portion having an n-channel TFT 502 and a pixel portion having a pixel TFT 503 and a storage capacitor 504 can be formed over the same substrate. In this specification, such a substrate is called an active matrix substrate.

The present embodiment is characterized in that the gate wiring 471 is formed by the second wiring, and is electrically connected to the gate electrodes 436 and 438 by the contact holes. That is, the first interlayer insulating film 464 and the second interlayer film 4 are formed on the source wiring 439, the gate electrode 436, and the gate electrode 438.
The pixel electrode 474 is formed with only 65 interposed therebetween.

This is because the pixel electrode 47 is formed on the source electrode 439.
4 can be overlapped.

According to the steps described in this embodiment, the number of photomasks required for manufacturing an active matrix substrate is reduced to seven.
(Island-shaped semiconductor layer pattern, first wiring pattern [gate electrode, source wiring, capacitor wiring], n-channel region mask pattern, p-channel region mask pattern, contact hole pattern, second wiring pattern [source electrode,
Drain electrode, capacitor connection electrode, and gate wiring],
Pixel electrode pattern).

Next, as shown in FIG.
7, an ITO film 508 having a thickness of 120 nm is formed as a transparent conductive film. In order to prevent parasitic capacitance, the ITO film on the drive circuit portion is removed by a patterning process using a photomask and an etching process. IT
The O film 508 functions as a counter electrode. In this specification, such a substrate is referred to as a counter substrate.

An alignment film 509 for vertical alignment and an alignment film 510 for vertical alignment are formed on the active matrix substrate and the counter substrate to a thickness of 80 nm. The alignment film for vertical alignment is SE
1211 (manufactured by Nissan Chemical Industries) is used.

Further, NN700 (manufactured by JSR) is provided on the opposite substrate.
Is applied in a thickness of 4.2 μm, applied and pre-baked, and then exposed with a mask aligner using a mask for patterning. Thereafter, development was performed with CD700 (manufactured by Fuji Film Reorin), and 250
A baking process is performed at 1 ° C. for 1 hour. As a result, a wall-shaped spacer 505 having a height of 4.0 μm is formed. The wall-shaped spacer 505 is formed above the source wiring 439. The top view of FIG. 14 shows the formation position of the wall-shaped spacer 505. FIG.
In FIG. 4, the same reference numerals are used for the portions corresponding to FIG.

Further, NN7 is provided on the active matrix substrate.
00 (manufactured by JSR) in a thickness of 4.2 μm,
After pre-baking, exposure and development are performed, and a baking process is performed on the dried substrate at 250 ° C. for 1 hour. As a result, a wall-shaped spacer 506 having a height of 4.0 μm is formed.
The wall-shaped spacer 506 is formed on the pixel electrode 474. Wall-shaped spacer 505 formed above the source wiring
And the distance between the wall-shaped spacer formed on the pixel electrode is made uniform. The wall-like spacer 5 is shown in the top view of FIG.
06 is shown. In FIG. 14, the same reference numerals are used for portions corresponding to FIG.

Thereafter, a sealing material (not shown) is provided on the opposite substrate by using a dispense drawing method. After applying the sealing material, the sealing material is fired at 90 ° C. for about 0.5 hour.

The active matrix substrate having undergone the above steps is bonded to the counter substrate. A pressure of 0.3 to 1.0 kgf / cm ² is applied to the pair of bonded substrates in a direction perpendicular to the plane of the substrate and over the entire surface of the substrate, and is simultaneously heated in a clean oven at 160 ° C. for about 2 hours by hot pressing. Adhere.

[0157] Then, after waiting for the pair of bonded substrates to cool, the scriber and the breaker separate the substrates.

The liquid crystal 511 is injected by a vacuum injection method. Prepare the cut panel in a vacuum vessel and use a vacuum pump.
1.33 × 10 ⁻⁵ to 1.33 × 10 ⁻⁷ P
After a vacuum state of about a is reached, the injection port is immersed in a liquid crystal dish on which liquid crystal MLC-2038 (manufactured by Merck) having negative dielectric anisotropy is provided.

Next, when the vacuum chamber in the vacuum state is gradually leaked with nitrogen and returned to the atmospheric pressure, the pressure difference between the atmospheric pressure in the panel and the atmospheric pressure and the action of the liquid crystal capillary phenomenon cause the liquid crystal panel to enter the vacuum chamber. The liquid crystal is injected, and the liquid crystal gradually advances from the injection port side to the opposite side to complete the injection step.

When it is confirmed that the inside (inside) of the seal pattern on which the sealing material is formed is filled with the liquid crystal, both sides of the liquid crystal panel are pressurized. After 15 minutes, excess liquid crystal is wiped off and the liquid crystal panel is pressed. An ultraviolet curable resin (not shown) is applied to an inlet (not shown), and the pressure is reduced. At that time, the ultraviolet curable resin enters. In this state, UV irradiation (4
(10 to 10 mW / cm ² , 120 seconds) to cure the ultraviolet curable resin and seal the injection port.

Next, the liquid crystal adhered to the substrate surface and the end surface was washed with an organic solvent, for example, acetone and ethanol. Thereafter, the liquid crystal is realigned at 130 ° C. for about 0.5 hour.

Then, a flexible printed wiring board (Flexible Pri
nt Circuit (FPC). Next, a polarizing plate is attached to the active matrix substrate and the counter substrate, and a liquid crystal display device is completed.

As shown in FIGS. 1 and 13, since the liquid crystal 511 uses a wall-shaped spacer, it is possible to control the orientation substantially parallel to the inclined side surface of the wall-shaped spacer. The inclined side surfaces of the opposing wall-shaped spacer 505 and wall-shaped spacer 506 are formed to be parallel. The black portions of the liquid crystal 16 having the negative dielectric anisotropy in FIG. 1 indicate that the tip is directed toward the counter substrate.

According to the present embodiment, it is possible to divide the alignment of the liquid crystal into two. Thus, a transmissive liquid crystal display device having symmetrical viewing characteristics is manufactured.

[Embodiment 6] (Method of manufacturing liquid crystal display device) A method of manufacturing a transmission type liquid crystal display device used in the present invention is shown in FIG.
This will be described with reference to FIGS. 16 to 18.
, The same reference numerals are used for corresponding parts. FIGS. 17 and 18 are top views of the pixel portion of this embodiment.
The chain line EE ′ in FIG. 16 corresponds to the chain line EE ′ in FIG. 17 and FIG.
It corresponds to the cross-sectional view cut at E '.

The liquid crystal display of this embodiment corresponds to the cross section shown in FIG. Further, as shown in FIG. 2, the alignment film is formed after the formation of the wall-shaped spacer. The chain line A ₂ − in FIG.
A ₂ ′ corresponds to the dashed line A ₂ -A ₂ ′ in FIG. FIG. 2 illustrates elements that affect the alignment of the liquid crystal.

Note that the manufacturing process of the active matrix substrate of this embodiment includes the process of activating the impurity and the process of hydrogenating the island-shaped semiconductor film (shown in FIGS. 10A to 12A).
Are the same as in the fifth embodiment and will not be described. The characteristic features of the omitted steps are as follows.

First, a gate electrode is formed in two layers, and when an n-type impurity is added to the island-shaped semiconductor layer due to a difference in film thickness of the gate electrode, the gate electrode is formed on the island-shaped semiconductor layer in a self-aligned manner. One impurity region and a second impurity region are provided (FIG. 10).
(B), FIG. 10 (C)). Thus, two types of impurity regions can be formed using one photomask.

Next, the gate insulating film is etched using the gate electrode as a mask (FIG. 11A).

Further, when the impurity element imparting n-type is added to the island-shaped semiconductor film, a resist is provided in the pixel TFT to serve as a doping mask, so that the third impurity region is added to the island-shaped semiconductor film. Is formed, and finally a first impurity region to a third impurity region are formed in the pixel TFT. At this time, the n-channel type TF
Regarding T, no resist is formed, and a third impurity region and a fourth impurity region are formed in the island-shaped semiconductor film. In this manner, the n-channel TFT and the pixel T
The impurity concentration of the island-like semiconductor film of the FT n-channel TFT is determined (FIG. 11B).

Next, a method for manufacturing an active matrix substrate corresponding to the transmission type liquid crystal display device of the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 16A, a first interlayer insulating film 601 is formed on a gate electrode and a gate insulating film. The first interlayer insulating film 601 is a silicon oxide film,
The insulating film may be formed using a silicon oxynitride film, a silicon nitride film, or a stacked film combining these. In any case, the first interlayer insulating film 601 is formed from an inorganic insulating material. The thickness of the first interlayer insulating film 601 is 100 to 200 n
m.

Here, when a silicon oxide film is used, tetraethyl orthosilicate is formed by a plasma CVD method.
e: TEOS) and O ₂ were mixed, and the reaction pressure was 40 Pa,
A substrate temperature of 300 to 400 ° C. and a high frequency (176 MH)
z) It can be formed by discharging at a power density of 0.5 to 0.8 W / cm ² . In the case of using a silicon oxynitride film, a silicon oxynitride film formed from SiH ₄ , N ₂ O, and NH ₃ by a plasma CVD method, or SiH ₄ , N ₂ O
May be formed using a silicon oxynitride film formed from the above.
The manufacturing conditions in this case are a reaction pressure of 20 to 200 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (60 MHz) power density of 0.1 to 1.0 W / cm ² . Alternatively, a hydrogenated silicon oxynitride film formed from SiH ₄ , N ₂ O, and H ₂ may be used. Similarly, a silicon nitride film can be formed from SiH ₄ and NH ₃ by a plasma CVD method. In this embodiment, the first interlayer insulating film 601 is formed with a thickness of 100 to 200 nm from a silicon oxynitride film.

Thereafter, a second interlayer insulating film 602 made of an organic insulating material is formed with an average thickness of 1.0 to 2.0 μm. As the organic resin material, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. For example, in the case of using a polyimide that is thermally polymerized after being applied to a substrate, it is formed by firing at 300 ° C. in a clean oven. In the case of using acrylic, a two-component type is used, and after mixing the main material and the curing agent, the whole surface is applied using a spinner and then pre-heated at 80 ° C. for 60 seconds on a hot plate. And then 250 ° C in a clean oven
For 60 minutes.

As described above, the surface can be satisfactorily planarized by forming the second interlayer insulating film with the organic insulating material. In addition, since organic resin materials generally have a low dielectric constant, parasitic capacitance can be reduced. But,
Since it is hygroscopic and is not suitable as a protective film, it must be used in combination with a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like formed as the first interlayer insulating film 601 as in this embodiment.

Thereafter, a resist mask having a predetermined pattern is formed using a photomask, and a contact hole reaching a source region or a drain region formed in each island-like semiconductor film is formed. The formation of the contact hole is performed by a dry etching method. In this case, the second interlayer insulating film 602 made of organic resin material using a mixed gas of CF _4, O _2, He as an etching gas is first etched, then followed by a first etching gas as CF _4, O ₂ Is etched. Furthermore, by switching the etching gas to CHF ₃ and etching the gate insulating film in order to increase the selectivity with respect to the island-shaped semiconductor film, a contact hole can be formed favorably.

Then, a conductive metal film is formed by sputtering or vacuum evaporation, a resist mask pattern is formed by a photomask, and the source wiring 60 is formed by etching.
3 to 604, drain electrodes 606 to 607, connection electrodes 605, and connection electrodes 608 are formed.

Here, the connection electrode 605 is connected to the source wiring 61.
0 and the island-shaped semiconductor film 611 are electrically connected.

The connection electrode 608 is electrically connected to the pixel electrode 609. In addition, the pixel electrode 609 and the island-shaped semiconductor film 609 are electrically connected to the island-shaped semiconductor film 609 functioning as a capacitor electrode of the storage capacitor 704 to have the same potential.

The pixel electrode 609 and the storage capacitor 704 are formed in different pixels.

In FIG. 16, Ti is used as the conductive metal film.
A film is formed to a thickness of 50 to 150 nm, a contact is formed with the semiconductor film forming the source or drain region of the island-shaped semiconductor layer, and aluminum (A) is superimposed on the Ti film.
l) is formed to a thickness of 300 to 400 nm, and
Film or titanium nitride (TiN) film of 100 to 200 nm
To form a three-layer structure.

Thereafter, a transparent conductive film is formed on the entire surface, and a pixel electrode 609 is formed by patterning and etching using a photomask. Pixel electrode 609
Are formed on the interlayer insulating film 602, and the pixel TFT 703
And a part thereof overlaps with the connection electrode 608 to form a connection structure.

The material of the transparent conductive film is indium oxide (I
n ₂ O ₃ ) and indium tin oxide alloy (In ₂ O ₃ —S
nO ₂ ; ITO film) or the like can be formed by a sputtering method, a vacuum evaporation method, or the like. The etching of such a material is performed using a hydrochloric acid-based solution. But,
In particular, since etching of the ITO film easily generates residues,
In order to improve the etching processability, an alloy of indium oxide and zinc oxide (In ₂ O ₃ —ZnO) may be used. Since the indium oxide zinc oxide alloy has excellent surface smoothness and excellent thermal stability with respect to the ITO film, even when Al is used for the connection electrode 608, a corrosion reaction with Al that contacts the surface can be prevented. Similarly, zinc oxide (ZnO) is a suitable material, and zinc oxide (ZnO: Ga) to which gallium (Ga) is added in order to increase the transmittance and conductivity of visible light can be used. In this embodiment, the indium zinc oxide alloy film is formed with a thickness of 120 nm.

When hydrogenation was performed in this state, favorable results were obtained for improving the characteristics of the TFT. For example, 3 ~
The heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 100% hydrogen, or a similar effect may be obtained by using a plasma hydrogenation method. It is desirable that the defect density in the island-shaped semiconductor films 403 to 406 be 10 ¹⁶ / cm ³ or less.
What was necessary was just to give about 1 atomic%.

As described above, the p-channel TFT 7
A driver circuit portion having a TFT 01 and an n-channel TFT 702 and a pixel portion having a pixel TFT 703 and a storage capacitor 704 can be formed over the same substrate. In this specification, such a substrate is called an active matrix substrate.

In the present embodiment, gate wirings 612 to 614, capacitance wiring 615 and source wiring 61 are used as first wirings.
0 is formed in the same layer, and the source wiring is electrically connected to the island-shaped semiconductor layer 611 by using the connection electrode 605 so that the gate wiring and the source wiring do not cross each other.

According to the steps described in this embodiment, the number of photomasks required for manufacturing an active matrix substrate is reduced to seven.
Sheets (island-shaped semiconductor layer pattern, first wiring pattern [gate wiring, source wiring, capacitance wiring], n-channel region mask pattern, p-channel region mask pattern, contact hole pattern, second wiring pattern [connection electrode], Pixel electrode pattern).

Referring to the top view, as shown in FIG. 17, a gate wiring 614 and a capacitor wiring 615 arranged in a row direction, a source wiring arranged in a column direction, and a gate wiring are formed on an active matrix substrate. There is a pixel portion having a pixel TFT near the intersection of the wiring 614 and the source wiring.

It should be noted that the source wiring in FIG. 17 is different from the island-shaped source wiring 610 arranged in the column direction with the connection electrode 6.
05 is connected. Note that the island-shaped source wiring 610 is connected to the gate wiring 614 (the gate electrode 612).
And the gate electrode 613) and the capacitor wiring 615 are formed below the gate insulating film (not shown).

A first interlayer insulating film is formed so as to be in contact with gate electrodes 612 to 613 and gate wiring 614. Further, a second interlayer insulating film is formed on the first interlayer insulating film. The connection electrode 60 is formed on the second interlayer insulating film.
5 and a connection electrode 608 are formed.

An island-shaped source wiring 610 and a connection electrode 605
Are electrically connected through contact holes 616-617. Further, the connection electrode 605 is electrically connected to the source region of the island-shaped semiconductor film 611. Thereby, the source wiring 61
0 and the source region of the island-shaped semiconductor film 611 are electrically connected.

The connection electrode 611 is provided in the contact hole 619.
This electrically connects to the drain region of the island-shaped semiconductor film 611. Further, the connection electrode 611 is formed in the contact hole 62.
0 electrically connects to the island-shaped semiconductor layer 609 functioning as a capacitor electrode. Since the connection electrode 611 is formed to overlap with a pixel electrode 609 described later, the island-shaped semiconductor layer 609 functioning as a capacitor electrode has the same potential as the pixel electrode 609.

A pixel electrode 609 made of a transparent conductive film is provided so as to directly overlap a part of the connection electrode 608 so as to prevent an electric short circuit with an adjacent pixel.

In this embodiment, the pixel electrode 609 and the gate wiring 614 are formed in a pattern that overlaps with an interlayer insulating film interposed therebetween. However, in order to reduce the parasitic capacitance generated between the pixel electrode and the gate electrode, the pixel electrode can be formed inside the gate wiring.

With such a structure, light can be shielded between pixels by mainly overlapping the edge of the pixel electrode 609 with the island-shaped source wiring 610 or the gate wiring 614.

Compared with the sixth embodiment, the pixel electrode 609 can overlap not only the island-shaped source wiring 610 but also the capacitance wiring 615 and the gate wiring 614, so that the area of the pixel electrode can be increased and the aperture ratio can be increased. Will be higher.

Next, as shown in FIG. 16 (2), an ITO film 521 as a transparent conductive film is
It is formed with a thickness of nm. In order to prevent parasitic capacitance, the ITO film on the drive circuit portion is removed by a patterning process using a photomask and an etching process. The ITO film 521 functions as a counter electrode. In this specification, such a substrate is referred to as a counter substrate.

Further, NN700 (manufactured by JSR) is provided on the opposite substrate.
Is applied in a thickness of 4.2 μm, applied, pre-baked, exposed, developed, and dried to a substrate of 250 μm.
A firing step is performed at a temperature of 1 ° C. for one hour. As a result, a wall-shaped spacer 512 having a height of 4.0 μm is formed. The wall-shaped spacer 512 is formed above the source wiring 610. The formation position of the wall-shaped spacer 512 is shown in the top view of FIG. The difference from the fifth embodiment is that in this embodiment, a wall-shaped spacer is formed before forming an alignment film. In FIG. 18, the same reference numerals are used for the portions corresponding to FIG.

Further, NN7 is provided on the active matrix substrate.
00 (manufactured by JSR) in a thickness of 4.2 μm,
After pre-baking, exposure and development are performed, and a baking process is performed on the dried substrate at 250 ° C. for 1 hour. As a result, a wall-shaped spacer 513 having a height of 4.0 μm is formed.
The wall-shaped spacer 506 is formed over the pixel electrode 609.

FIG. 18 is a top view showing the position where the wall-shaped spacer 506 is formed. The distance between the wall-shaped spacer 512 formed above the source wiring 610 and the wall-shaped spacer 513 formed on the pixel electrode is made uniform.

An alignment film 522 for vertical alignment and an alignment film 523 for vertical alignment are formed on the active matrix substrate and the counter substrate with a thickness of 80 nm. The alignment film for vertical alignment is SE
1211 (manufactured by Nissan Chemical Industries) is used.

Thereafter, a sealing material (not shown) is provided on the opposite substrate by using a dispense drawing method. After applying the sealing material, the sealing material is fired at 90 ° C. for about 0.5 hour.

The active matrix substrate having undergone the above steps is bonded to the counter substrate. A pressure of 0.3 to 1.0 kgf / cm ² is applied to the pair of bonded substrates in a direction perpendicular to the plane of the substrate and over the entire surface of the substrate, and is simultaneously heated in a clean oven at 160 ° C. for about 2 hours by hot pressing. Adhere.

Then, after waiting for the pair of bonded substrates to cool, the scriber and the breaker divide the substrate.

A liquid crystal is injected by a vacuum injection method. After preparing the panel after division in a vacuum container, the inside of the vacuum container is evacuated to about 1.33 × 10 ⁻⁵ to 1.33 × 10 ⁻⁷ Pa by a vacuum pump, and then the injection port is negative. It is immersed in a liquid crystal dish on which liquid crystal MLC-2038 (manufactured by Merck) having dielectric anisotropy is provided.

Next, when the vacuum chamber in a vacuum state is gradually leaked with nitrogen and returned to the atmospheric pressure, the pressure difference between the atmospheric pressure in the panel and the atmospheric pressure and the action of the liquid crystal capillary phenomenon cause the liquid crystal panel to enter from the inlet of the liquid crystal panel. The liquid crystal is injected, and the liquid crystal gradually advances from the injection port side to the opposite side to complete the injection step.

When it is confirmed that the inside (inside) of the seal pattern on which the sealing material is formed is filled with the liquid crystal 524, both sides of the liquid crystal panel are pressurized. After 15 minutes, excess liquid crystal is wiped off and the liquid crystal 524 is pressed. A UV curable resin (not shown) is applied to an injection port (not shown), and the pressure is reduced. At that time, the ultraviolet curable resin enters. In this state, the ultraviolet curable resin is cured by irradiation with ultraviolet rays (4 to 10 mW / cm ² , 120 seconds), and the injection port is sealed.

Next, the liquid crystal adhered to the surface and the end face of the liquid crystal panel is washed with an organic solvent, for example, acetone and ethanol. Thereafter, the liquid crystal is realigned at 130 ° C. for about 0.5 hour.

Then, a flexible printed wiring board (Flexible Pri
nt Circuit (FPC). Next, a polarizing plate is attached to the active matrix substrate and the counter substrate, and a liquid crystal display device is completed.

As shown in FIG. 2 and FIG. 16 (2), since the alignment film is formed on the wall-shaped spacer, the alignment of the liquid crystal is controlled almost perpendicularly to the inclined side surfaces of the wall-shaped spacer. Becomes possible. The inclined side surfaces of the opposing wall-shaped spacer 512 and wall-shaped spacer 513 in FIG. 16 (2) are formed to be parallel. The black portions of the liquid crystal 16 having negative dielectric anisotropy in FIG. 2 indicate that the tip is directed toward the counter substrate.

In this embodiment, the orientation of the liquid crystal is divided into two. Thus, a transmissive liquid crystal display device having symmetrical viewing characteristics is manufactured.

[Embodiment 7] (Method of Manufacturing Liquid Crystal Display Device) In this embodiment, a method of manufacturing an active matrix substrate corresponding to a transmission type liquid crystal display device used in the present invention will be described with reference to FIGS. C)) and FIG. 24.

[0213] A method for manufacturing an active matrix substrate when the present invention is used for a reflective liquid crystal display device will be described with reference to FIGS.

[0214] A method for manufacturing a transmissive liquid crystal display device using an active matrix substrate corresponding to the transmissive liquid crystal display device will be described with reference to FIGS.

The arrangement of the wall-shaped spacers in this embodiment corresponds to that shown in FIG. That is, the alignment direction of the liquid crystal is controlled by the inclined side surfaces of the wall-shaped spacer provided on the pixel electrode and the alignment film applied to the source wiring.

[0216] chain line A ₃ -A ₃ in FIG. 24 'is a chain line A ₃ in FIG. 3 -
A ₃ ′. FIG. 3 illustrates elements that influence the alignment of the liquid crystal.

FIG. 24 is a top view of a pixel portion of a transmission type liquid crystal display device manufactured in this embodiment. A chain line FF ′ in FIGS. 22 and 23 corresponds to a cross-sectional view taken along a chain line FF ′ in FIG.

The same reference numerals are used for the portions corresponding to FIGS.

First, a method for manufacturing an active matrix substrate will be described with reference to FIGS. Here, a method of simultaneously manufacturing a pixel TFT and a storage capacitor in a pixel portion and a TFT of a driver circuit provided around the pixel portion will be described in detail according to steps.

In FIG. 19A, a substrate 101 is made of a glass substrate such as barium borosilicate glass or aluminoborosilicate glass typified by Corning # 7059 glass or # 1737 glass, etc., and polyethylene terephthalate (PET). ), Polyethylene naphthalate (PEN), polyethersulfone (PES), and other plastic substrates having no optical anisotropy. When a glass substrate is used, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point.

Then, a table for forming the TFT of the substrate 101 is formed.
In order to prevent impurity diffusion from the substrate 101,
Silicon film, silicon nitride film or silicon oxynitride film
A base film 102 made of an insulating film such as an insulating film is formed. example
For example, SiH _Four, NH_Three, N_TwoMade from O
The manufactured silicon oxynitride film 102a is
(Preferably 50-100 nm), and likewise SiH_Four, N_TwoO
Hydrogenated silicon oxynitride film 102b formed from
0-200 nm (preferably 100-150 nm) thickness
To form a laminate.

Here, the base film 102 is shown as having a two-layer structure, but may be formed as a single-layer film of the insulating film or a laminate of two or more layers.

The silicon oxynitride film is a conventional parallel plate type.
It is formed by a plasma CVD method. Silicon oxynitride
The film 102a is made of SiH_FourTo 10 SCCM, NH_ThreeTo 100 SCC
M, N _TwoO was introduced into the reaction chamber at 20 SCCM, and the substrate temperature was 3
25 ° C, reaction pressure 40Pa, discharge power density 0.41W / c
m^TwoAnd the discharge frequency was 60 MHz. On the other hand, hydrogen oxynitride
The silicon film 102b is made of SiH_FourTo 5 SCCM, N_TwoO to 12
0 SCCM, H_TwoInto the reaction chamber as 125 SCCM
Temperature 400 ° C, reaction pressure 20Pa, discharge power density 0.41
W / cm^TwoAnd the discharge frequency was 60 MHz. These films are
Change the temperature and change the reaction gas
It can also be done.

The silicon oxynitride film 102a manufactured in this manner has a density of 9.28 × 10 ²² / cm ³ , 7.13% of ammonium hydrogen fluoride (NH ₄ HF ₂ ) and ammonium fluoride (NH ₄ HF ₂ ). 20% of a mixed solution containing 15.4% of NH ₄ F) (trade name: LAL500, manufactured by Stella Chemifa).
The etching rate at a temperature of ° C. is as low as about 63 nm / min, and the film is dense and hard. The use of such a film as a base film is effective in preventing an alkali metal element from a glass substrate from diffusing into a semiconductor layer formed thereover.

Next, 25 to 80 nm (preferably 30 to 80 nm)
Semiconductor layer 103 having a thickness of 60 nm and having an amorphous structure.
a is formed by a known method such as a plasma CVD method or a sputtering method. For example, an amorphous silicon film is formed to a thickness of 55 nm by a plasma CVD method. The semiconductor film having an amorphous structure includes an amorphous semiconductor layer and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used. Further, both the base film 102 and the amorphous semiconductor layer 103a can be formed continuously.

For example, as described above, after the silicon oxynitride film 102a and the silicon oxynitride hydride film 102b are successively formed by the plasma CVD method, the reaction gas is SiH ₄ , N _2.
By switching from O and H ₂ to only SiH ₄ and H ₂ or SiH ₄ , continuous formation can be achieved without once exposing to air.
As a result, contamination of the surface of the hydrogenated silicon oxynitride film 102b can be prevented, and variation in characteristics of a TFT to be manufactured and fluctuation in threshold voltage can be reduced.

Then, a crystallization step is performed to form a crystalline semiconductor layer 103b from the amorphous semiconductor layer 103a. Laser annealing, thermal annealing (solid phase growth), or rapid thermal annealing (RTA)
Law) can be applied. When a glass substrate or a plastic substrate having low heat resistance as described above is used, it is particularly preferable to apply a laser annealing method. RT
In the method A, an infrared lamp, a halogen lamp, a metal halide lamp, a xenon lamp, or the like is used as a light source. Alternatively, according to the technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652, the crystalline semiconductor layer 10 is formed by a crystallization method using a catalytic element.
3b can also be formed. First, in the crystallization process,
It is preferable to release the hydrogen contained in the amorphous semiconductor layer, and heat treatment is performed at 400 to 500 ° C. for about 1 hour to reduce the amount of hydrogen contained to 5 atom% or less. It is good because it can be prevented.

In the step of forming an amorphous silicon film by a plasma CVD method, SiH ₄ and argon (Ar) are used as reaction gases, and the substrate temperature during film formation is 400 to 450 ° C.
When formed, the hydrogen concentration in the amorphous silicon film can be reduced to 5 atomic% or less. In such a case, heat treatment for releasing hydrogen is unnecessary.

When the crystallization is performed by laser annealing, a pulse oscillation type or continuous emission type excimer laser or argon laser is used as the light source. When a pulse oscillation type excimer laser is used, laser annealing is performed by processing a laser beam into a linear shape. Laser annealing conditions are appropriately selected by the practitioner, for example,
The laser pulse oscillation frequency is 30 Hz, and the laser energy density is 100 to 500 mJ / cm ² (typically 300 to
４００400 mJ / cm ² ). Then, a linear beam is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear beam at this time is set to 80 to 98%. In this way, as shown in FIG.
03b can be obtained.

Then, using a first photomask (PM1), a resist pattern is formed on the crystalline semiconductor layer 103b by photolithography, and the crystalline semiconductor layer is divided into islands by dry etching. FIG.
As shown in FIG. 9C, island-shaped semiconductor layers 104 to 108 are formed. CF for dry etching of crystalline silicon film
A mixed gas of ₄ and O ₂ is used.

In order to control the threshold voltage (Vth) of the TFT, an impurity element imparting p-type is added to such an island-shaped semiconductor layer in an amount of about 1 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / cm ³ . The concentration may be added to the entire surface of the island-shaped semiconductor layer. The impurity element imparting p-type to the semiconductor includes boron (B),
Elements of the first group of the periodic table such as aluminum (Al) and gallium (Ga) are known. As the method, an ion implantation method or an ion doping method (or an ion shower doping method) can be used, but the ion doping method is suitable for treating a large-area substrate. In the ion doping method, diborane (B ₂ H ₆ ) is used as a source gas and boron (B) is added. The implantation of such an impurity element is not always necessary and may be omitted. However, it is a method preferably used for keeping the threshold voltage of the n-channel TFT within a predetermined range.

The gate insulating film 109 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by a plasma CVD method or a sputtering method. In this embodiment, 1
It is formed from a silicon oxynitride film with a thickness of 20 nm. In addition, a silicon oxynitride film formed by adding O ₂ to SiH ₄ and N ₂ O is a preferable material for this application because the fixed charge density in the film is reduced. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, tetraethyl orthosilicate (TEO) is formed by a plasma CVD method.
S) and O ₂ were mixed, the reaction pressure was 40 Pa, and the substrate temperature was 30.
It can be formed by discharging at a high-frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm ² at 0 to 400 ° C. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.

[0233] Then, as shown in FIG. 19D, a heat-resistant conductive layer for forming a gate electrode is formed over the gate insulating film 109. The heat-resistant conductive layer may be formed as a single layer, or may be formed as a multilayer structure including a plurality of layers such as two layers or three layers as necessary. For example, a structure in which such a heat-resistant conductive material is used for a gate electrode, and a conductive layer (A) 110 made of a conductive nitride metal film and a conductive layer (B) 111 made of a metal film are stacked. good. The conductive layer (B) 111 may be formed of an element selected from Ta, Ti, and W, an alloy containing the above elements, or an alloy film in which the above elements are combined. (TaN), tungsten nitride (WN), titanium nitride (TiN) film, or the like. Further, as the conductive layer (A) 110, tungsten silicide or titanium silicide may be used. It is preferable to reduce the concentration of impurities contained in the conductive layer (B) 111 in order to reduce the resistance. In particular, the oxygen concentration is preferably 30 ppm or less. For example, W can realize a specific resistance value of 20 μΩcm or less by setting the oxygen concentration to 30 ppm or less.

The conductive layer (A) 110 has a thickness of 10 to 50 nm (preferably 20 to 30 nm), and the conductive layer (B) 111 has a thickness of 200 to 400 nm (preferably 250 to 350 nm).
It is good. In the case of forming W as a gate electrode, an Ar gas and a nitrogen (N ₂ ) gas are introduced by a sputtering method using W as a target to form a conductive layer (A) 111 with a thickness of 50 nm using a WN film. The conductive layer (B) 110 is formed of a W film to a thickness of 250 nm. As another method, the W film can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, in order to use it as a gate electrode, it is necessary to reduce the resistance, and it is desirable that the resistivity of the W film be 20 μΩcm or less. W
The resistivity of the film can be reduced by enlarging the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is inhibited and the resistance is increased. Thus, in the case of using the sputtering method, a W target having a purity of 99.9999% is used, and further, the W film is formed with sufficient care so as not to mix impurities from the gas phase during film formation. 9 to 20 μΩcm can be realized.

On the other hand, a TaN film is formed on the conductive layer (A) 110,
When a Ta film is used for the conductive layer (B) 111, it can be formed by a sputtering method in the same manner. TaN film is T
The target film a is formed using a mixed gas of Ar and nitrogen as a sputtering gas, and the Ta film uses Ar as a sputtering gas. When an appropriate amount of Xe or Kr is added to these sputter gases, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used for a gate electrode, but the resistivity of the β-phase Ta film is about 180 μΩcm and is not suitable for a gate electrode. Since the TaN film has a crystal structure close to the α-phase, an α-phase Ta film was easily obtained by forming a Ta film thereon. Although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm under the conductive layer (A) 110. Thus, the adhesion of the conductive film formed thereover is improved and oxidation is prevented, and at the same time, a small amount of an alkali metal element contained in the conductive layer (A) 110 or the conductive layer (B) 111 is added to the gate insulating film 109. Spreading can be prevented. In any case, the conductive layer (B) 1
11 preferably has a resistivity in the range of 10 to 50 μΩcm.

In this embodiment, in order to form a gate electrode, the conductive layer (A) 110 is a WN film and the conductive layer (B) 11
1 was formed with a W film. Next, a second photomask (PM
Using 2), resist masks 112 to 117 are formed using a photolithography technique, and the conductive layer (A) 1
10 and the conductive layer (B) 111 are collectively etched to form gate electrodes 118 to 122 and a capacitor wiring 123.
In the gate electrodes 118 to 122 and the capacitor wiring 123, 118a to 122a made of a conductive layer (A) and 118b to 122b made of a conductive layer (B) are integrally formed (FIG. 20A).

At this time, at least the gate electrodes 118-1
Etching is performed so that a tapered portion is formed at the end of 22. This etching is performed by an ICP etching apparatus. As specific etching conditions, a discharge gas of 3.2 W / cm ² (13.56 MHz), a mixed gas of CF ₄ and Cl ₂ as an etching gas and a flow rate of 30 SCCM were used.
Bias power 224mW / cm ² (13.56 MHz), pressure 1.0P
Etching was performed with a. Under such etching conditions, a tapered portion whose thickness gradually increases inward from the end portion is formed at the end portion of the gate electrodes 118 to 122, and the angle is 5 to 35 °, preferably 10 °.
２５25 °. The angle of the tapered portion is the angle of the part shown as theta _1. This angle greatly affects the concentration gradient of the low-concentration n-type impurity region that forms the LDD region later. The angle θ ₁ of the tapered portion is determined by using the length (WG) of the tapered portion and the thickness (HG) of the tapered portion as Tan.
(Θ ₁ ) = HG / WG.

In order to perform etching without leaving a residue, over-etching is performed by increasing the etching time at a rate of about 10 to 20%. At this time, however, it is necessary to pay attention to the etching selectivity with the base. For example, as shown in Table 1, the selectivity of the silicon oxynitride film (gate insulating film 109) to the W film is 2 to 4 (typically 3). The exposed surface of the silicon film is etched to a thickness of about 20 to 50 nm to become substantially thinner, and a gate insulating film 130 having a new shape is formed.

Then, the n TFTs of the pixel TFT and the driving circuit are used.
In order to form an LDD region of a channel type TFT, an n-type
Step of adding an impurity element to be imparted (n^-Dope process)
U. The resist mask 112 used for forming the gate electrode
117 with a taper at the end
N-type in a self-aligned manner using
Is added by an ion doping method. This
Here, an impurity element imparting n-type is added to the end of the gate electrode.
Through the tapered part and the gate insulating film
Doping to reach the semiconductor layer located at
1 × 10 ¹³~ 5 × 10¹⁴atoms / cm^TwoAnd the accelerating power
The pressure is set to 80 to 160 keV. n-type
Elements belonging to Group 15 as pure elements, typically phosphorus
(P) or arsenic (As) is used.
(P) was used. Semiconducting by such ion doping method
Phosphorus (P) concentration in body layer is 1 × 10¹⁶~ 1 × 10¹⁹atoms
/cm^ThreeIn the concentration range of Thus, FIG.
As shown in (B), the island-shaped semiconductor layer has a low concentration n-type impurity region.
Regions 124 to 129 are formed.

In this step, at least the gate electrode 118 is formed in the low-concentration n-type impurity regions 124 to 128.
The concentration gradient of phosphorus (P) contained in the portion overlapping with the gate electrodes 122 to 122 reflects the change in the thickness of the tapered portions of the gate electrodes 118 to 122. That is, the low concentration n-type impurity regions 124 to 1
The concentration of phosphorus (P) added to 28 gradually increases toward the edge of the gate electrode in a region overlapping the gate electrode. This is because the concentration of phosphorus (P) reaching the semiconductor layer changes depending on the difference in the thickness of the tapered portion. In FIG. 20B, the low-concentration n-type impurity region 1
Although the end portions of 24 to 129 are shown obliquely, this does not directly indicate the region to which phosphorus (P) is added, but the change in the concentration of phosphorus causes the gate electrode 118 as described above.
It shows that it changes along the shape of the tapered portion of ~ 122.

Next, in the n-channel TFT, a high-concentration n-type impurity region functioning as a source region or a drain region was formed (n ⁺ doping step). The resist masks 112 to 117 are left.
In order to form a mask for shielding phosphorus (P), 8 to 122 are added at a low acceleration voltage of 10 to 30 keV in the ion doping method. Thus, high concentration n-type impurity regions 131 to 136 are formed. Since the gate insulating film 130 in this region has been over-etched during the processing of the gate electrode as described above, the gate insulating film 130 has a thickness of 70 to 100 nm, which is thinner than the initial thickness of 120 nm. Therefore, phosphorus (P) can be satisfactorily added even under such low acceleration voltage conditions. The concentration of phosphorus (P) in this region is 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / c.
The concentration is adjusted to be within the range of m ³ (FIG. 20C).

Then, high-concentration p-type impurity regions 140 and 141 serving as a source region and a drain region are formed in the island-like semiconductor layers 104 and 106 forming the p-channel TFT. Here, the gate electrode 118 and the gate electrode 120
Is used as a mask to add a p-type impurity element to form a high-concentration p-type impurity region in a self-aligned manner. At this time, the island-shaped semiconductor layer 10 forming the n-channel TFT is formed.
5. The island-shaped semiconductor layer 107 and the island-shaped semiconductor layer 108 are formed on the resist mask 13 using the third photomask (PM3).
7 to 139 are formed and the entire surface is covered. The impurity regions 140 and 141 formed here are formed by an ion doping method using diborane (B ₂ H ₆ ). Then, high-concentration p-type impurity regions 140a and 141a that do not overlap with the gate electrode
(B) concentration of 3 × 10 ^{20 to} 3 × 10 ²¹ atoms
/ Cm ³ . Further, the impurity regions 140b and 141b overlapping with the gate electrode are formed as substantially low-concentration p-type impurity regions because the impurity element is added through the gate insulating film and the tapered portion of the gate electrode. The concentration is set to × 10 ¹⁹ atoms / cm ³ or more.
Phosphorus (P) is added to the high-concentration p-type impurity regions 140a and 141a and the low-concentration p-type impurity regions 140b and 141b in the previous step. ²⁰ to 1 × 10 ²¹ at
oms / cm ³ , a low concentration p-type impurity region 140b,
41b contains 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atoms / cm ³ , but the concentration of boron (B) added in this step is 1.5 to 3 times the concentration of phosphorus (P). By doing so, there was no problem because it functions as the source and drain regions of the p-channel TFT.

Thereafter, as shown in FIG. 21A, the first interlayer insulating film 14 is formed on the gate electrode and the gate insulating film.
Form 2 The first interlayer insulating film may be formed using a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a stacked film combining these. In any case, the first interlayer insulating film 142 is formed from an inorganic insulating material.
The thickness of the first interlayer insulating film 142 is 100 to 200 nm. Here, when a silicon oxide film is used, TEOS and O ₂ are mixed by a plasma CVD method, and a reaction pressure of 4 is used.
0 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (13.
56 MHz) It can be formed by discharging at a power density of 0.5 to 0.8 W / cm ² . In the case of using a silicon oxynitride film, SiH ₄ , N ₂ O, NH
Silicon oxynitride film made from ₃ , or SiH ₄ ,
N ₂ O may be formed by a silicon oxynitride film made from. The production conditions in this case are a reaction pressure of 20 to 200 Pa,
Substrate temperature 300-400 ° C, high frequency (60MHz)
It can be formed at a power density of 0.1 to 1.0 W / cm ² . Alternatively, a hydrogenated silicon oxynitride film formed from SiH ₄ , N ₂ O, and H ₂ may be used. Similarly, a silicon nitride film can be formed from SiH ₄ and NH ₃ by a plasma CVD method.

Thereafter, a step of activating the impurity elements imparting n-type or p-type added at the respective concentrations is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 1 ppm or less,
Preferably in a nitrogen atmosphere of 0.1 ppm or less 400 ~
The heat treatment is performed at 700 ° C., typically 500 to 600 ° C. In this embodiment, the heat treatment is performed at 550 ° C. for 4 hours. When a plastic substrate having a low heat-resistant temperature is used as the substrate 101, a laser annealing method is preferably applied (FIG. 21B).

Following the activation step, the atmosphere gas was changed.
And in an atmosphere containing 3 to 100% hydrogen,
Heat treatment at 450 ° C. for 1 to 12 hours to form an island-shaped semiconductor layer
Is carried out. This process was thermally excited
10 in the island-like semiconductor layer due to hydrogen¹⁶-10¹⁸/cm^ThreeNo da
This is a step of terminating the ringing bond. Other hydrogenation
As a means, plasma hydrogenation (excited by plasma
Using hydrogen). In any case, the island
Defect density in the semiconductor layers 104 to 108 is 10 ¹⁶/cm^ThreeLess than
It is preferable to set the hydrogen content to 0.01 to
What is necessary is just to give about 0.1 atomic%.

When the activation and hydrogenation steps are completed,
The second interlayer insulating film 143 made of an organic insulating material is used for 1.
It is formed to have an average thickness of 0 to 2.0 μm. As the organic resin material, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. For example, in the case of using a polyimide that is thermally polymerized after being applied to a substrate, it is formed by firing at 300 ° C. in a clean oven. In the case of using acrylic, after using a two-pack type, mixing the main material and the curing agent, applying the entire surface of the substrate using a spinner, and preheating at 80 ° C. for 60 seconds on a hot plate. Then, it can be formed by firing in a clean oven at 250 ° C. for 60 minutes.

As described above, the surface can be satisfactorily planarized by forming the second interlayer insulating film with the organic insulating material. In addition, since organic resin materials generally have a low dielectric constant, parasitic capacitance can be reduced. But,
Since it is hygroscopic and not suitable as a protective film, it is preferable to use it in combination with a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like formed as the first interlayer insulating film 142 as in this embodiment.

Thereafter, using a fourth photomask (PM4), a resist mask having a predetermined pattern is formed, and a contact hole reaching a source region or a drain region formed in each island-shaped semiconductor layer is formed. The formation of the contact hole is performed by a dry etching method. In this case, the second interlayer insulating film 143 made of an organic resin material is first etched using a mixed gas of CF ₄ , O ₂ , and He as an etching gas.
The first interlayer insulating film 142 is etched as F ₄ and O ₂ . Furthermore, in order to increase the selectivity with the island-shaped semiconductor film,
Switching the etching gas to CHF ₃ to change the gate insulating film 1
By etching 30, a contact hole can be formed well.

Then, a conductive metal film is formed by a sputtering method or a vacuum evaporation method, a resist mask pattern is formed by using a fifth photomask (PM5), and the source wirings 144 to 148 and the drain wirings 149 to 1 are formed by etching.
53 is formed. The drain wiring 154 represents a pixel electrode belonging to an adjacent pixel.

As described above, the driving circuit includes the first p-channel TFT (A) 200a and the first n-channel TFT (A) 200a.
(A) 201a, second p-channel TFT (A) 20
2a, a second n-channel TFT (A) 203a, a pixel TFT 204 and a storage capacitor 205 are formed in the pixel portion. Thus, an active matrix substrate used for a reflective liquid crystal display device is manufactured.

Through the above steps, the active matrix substrate of the reflection type liquid crystal display device shown in FIG. 21C can be manufactured with five photomasks. In order to use the present invention for a direct-view reflective liquid crystal display device, it is necessary to optimize a polarizing plate and an optical film.

Next, a process of manufacturing an active matrix substrate of a transmission type liquid crystal display device through the process of FIG. 22 using the active matrix substrate manufactured by using the substrate of FIG. 21B will be described.

As shown in FIG. 22, first, a transparent conductive film is formed on the second interlayer insulating film 143, and the pixel electrode 258 and the pixel electrode
0 is formed. The pixel electrode 260 represents a pixel electrode belonging to an adjacent pixel.

Next, the drain electrode 259 and the source wiring 2
61 is formed. The drain wiring 259 is connected to the pixel electrode 258
Is formed by providing a portion that overlaps with The source wiring 261 and the drain electrode 259 are 500 nm from the upper surface of the pixel electrode.
Desirably, the film is formed to have a thickness of 800 nm or more. Drain electrode 259 and drain wiring 25
9, a Ti film is formed to a thickness of 50 to 150 nm, a contact is formed with the semiconductor film forming the source or drain region of the island-shaped semiconductor film, and an Al film is formed on the Ti film to a thickness of 300 to 400 nm. It is formed to have a thickness. With this configuration, the pixel electrode 258 comes into contact with only the Ti film forming the drain electrode 259. As a result, it is possible to reliably prevent the transparent conductive film from directly contacting and reacting with Al.

A drain electrode 2 is formed by anisotropic etching.
59 and the upper surface of the source wiring 261 are smaller than the bottom surface.

Indium oxide zinc oxide alloy (In ₂ O ₃ —ZnO) and zinc oxide (ZnO) are also suitable materials for the transparent conductive film, and gallium (Ga) is used to increase the transmittance and conductivity of visible light. ) -Added zinc oxide (ZnO: G)
a) can be preferably used.

As described above, an active matrix substrate having a convex shape in which the source wiring 261 is raised with respect to the pixel electrode 258 is manufactured. The source wiring 261 is electrically connected to the source region of the island-shaped semiconductor film 108 through the contact hole 230. The gate wiring 122 crosses the source wiring 261 with the insulating film interposed therebetween. Capacitance wiring 12
3 and the island-shaped semiconductor film 108 form a storage capacitor 205.

The active matrix substrate used in the transmission type liquid crystal display device shown in FIG.
Will be described with reference to the top view of FIG. Source wiring 261 (26
1-1, 261-2) are formed in the column direction. Gate wiring 122 is formed in the row direction.

There is an island-shaped semiconductor film. Gate wiring 1
22 and the capacitor wiring 123 are formed in the same layer. The pixel electrode 258 is formed so as to be in contact with the insulating film with the insulating film interposed therebetween. The source wiring 261 and the drain electrode 259 are formed to have a thickness of 500 nm, preferably 800 nm or more with respect to the upper surface of the pixel electrode. Therefore, the source wiring 261 and the drain electrode 2
59 form a raised portion with respect to the pixel electrode 258. The drain electrode 259 is formed so as to overlap with the pixel electrode 258. The source wiring 261 is connected to the source region of the island-shaped semiconductor film through the contact hole 230. The storage capacitor 205 is formed using the capacitor electrode and the island-shaped semiconductor film 108 as a capacitor electrode. Thus, an active matrix substrate used for a transmission type liquid crystal display device is manufactured.

Next, steps for manufacturing a transmission type liquid crystal display device will be described below.

As shown in FIG. 23, an ITO film 515 having a thickness of 120 nm is formed as a transparent conductive film on a transparent insulating substrate 514. In order to prevent parasitic capacitance, the ITO film on the drive circuit portion is removed by a patterning process using a photomask and an etching process. The ITO film 515 functions as a counter electrode. In this specification, such a substrate is referred to as a counter substrate.

An alignment film 522 for vertical alignment and an alignment film 523 for vertical alignment are formed on the active matrix substrate and the counter substrate with a thickness of 80 nm. The alignment film for vertical alignment is SE
1211 (manufactured by Nissan Chemical Industries) is used. As the active matrix substrate, the one manufactured in FIG. 22 is used.

Further, NN7 is provided on the active matrix substrate.
00 (manufactured by JSR) in a thickness of 4.2 μm,
After pre-baking, exposure and development are performed, and a baking process is performed on the dried substrate at 250 ° C. for 1 hour. As a result, a wall-shaped spacer 513 having a height of 4.0 μm is formed.
The wall-shaped spacer 519 is formed over the pixel electrode 258.

After that, a sealing material (not shown) is provided on the opposite substrate by using a dispense drawing method. After applying the sealing material, the sealing material is fired at 90 ° C. for about 0.5 hour.

The active matrix substrate having undergone the above steps is bonded to the counter substrate. A pressure of 0.3 to 1.0 kgf / cm ² is applied to the pair of bonded substrates in a direction perpendicular to the plane of the substrate and over the entire surface of the substrate, and is simultaneously heated in a clean oven at 160 ° C. for about 2 hours by hot pressing. Adhere.

Then, after waiting for the pair of bonded substrates to cool, the scriber and the breaker divide the substrate.

As shown in FIG. 23, a liquid crystal is injected by a vacuum injection method. The panel after division is prepared in a vacuum container, and the inside of the vacuum container is set to 1.33 × 10 ⁻⁵ to 1.33 × 1 by a vacuum pump.
After evacuating to a vacuum of about 0 ^-7 Pa, the injection port is immersed in a liquid crystal dish on which liquid crystal MLC-2038 (manufactured by Merck) having negative dielectric anisotropy is provided.

Next, when the vacuum chamber in the vacuum state is gradually leaked with nitrogen to return to the atmospheric pressure, the pressure difference between the atmospheric pressure in the panel and the atmospheric pressure and the action of the liquid crystal capillary phenomenon cause the liquid crystal panel to enter the vacuum chamber. The liquid crystal is injected, and the liquid crystal gradually advances from the injection port side to the opposite side to complete the injection step.

When it is confirmed that the inside (inside) of the seal pattern formed by the sealing material is filled with the liquid crystal 517, both sides of the liquid crystal panel are pressurized. After 15 minutes, excess liquid crystal is wiped off and the liquid crystal is pressed. A UV curable resin (not shown) is applied to an injection port (not shown), and the pressure is reduced.
At that time, the ultraviolet curable resin enters. In this state, by ultraviolet irradiation (4 to 10 mW / cm ² for 120 seconds)
The ultraviolet curing resin was cured, and the injection port was sealed.

Next, the liquid crystal adhered to the surface and the end face of the liquid crystal panel is washed with an organic solvent, for example, acetone and ethanol. Thereafter, the liquid crystal is realigned at 130 ° C. for about 0.5 hour.

Thereafter, a flexible printed wiring board (Flexible Pri
nt Circuit (FPC). Next, a polarizing plate is attached to the active matrix substrate and the counter substrate, and a liquid crystal display device is completed.

The top view of FIG. 24 shows the formation position of the wall-shaped spacer 519. Source wiring 261-1 and source wiring 2
A wall-shaped spacer 519 is formed at an equal distance from 61-2.

As shown in FIG. 23, the source wiring 261 is formed in a convex shape with respect to the pixel electrode 258. As a result, the liquid crystal is tilted in a certain direction as shown in FIG. 3 by the inclined side surfaces of the alignment film formed on the source wiring and the wall-shaped spacer. The same is shown in FIG. In the present embodiment, the orientation of the liquid crystal is divided into two in the pixel. Thus, a transmissive liquid crystal display device having symmetrical viewing characteristics is manufactured.

[Embodiment 8] In this embodiment, another manufacturing method of the crystalline semiconductor layer for forming the active layer of the TFT of the active matrix substrate shown in Embodiments 5 to 7 will be described. The crystalline semiconductor layer is formed by crystallizing an amorphous semiconductor layer by a thermal annealing method, a laser annealing method, an RTA method, or the like. In addition, a catalytic element disclosed in JP-A-7-130652 is used. A crystallization method can also be applied. FIGS. 25, 26, and 2 show examples of this case.
7 will be described.

As shown in FIG. 25A, the first embodiment
Similarly, a base film 1102 is formed on a glass substrate 1101.
a, 1102b, semiconductor layer 1103 having an amorphous structure
Is formed with a thickness of 25 to 80 nm. The amorphous semiconductor layer includes an amorphous silicon (a-Si) film, an amorphous silicon / germanium (a-SiGe) film, and an amorphous silicon carbide (a-Si) film.
An SiC) film, an amorphous silicon tin (a-SiSn) film, or the like can be used. These amorphous semiconductor layers are preferably formed so as to contain about 0.1 to 40 atomic% of hydrogen. For example, an amorphous silicon film is formed with a thickness of 55 nm. Then, a layer 1104 containing a catalyst element is formed by a spin coating method in which an aqueous solution containing a catalyst element of 10 ppm by weight is applied by rotating the substrate with a spinner.
Nickel (Ni), germanium (G
e), iron (Fe), palladium (Pd), tin (S
n), lead (Pb), cobalt (Co), platinum (Pt),
Copper (Cu), gold (Au), and the like. This catalyst element-containing layer 1104 is formed by forming the catalyst element layer to a thickness of 1 to 5 nm by a printing method, a spray method, a bar coater method, or a sputtering method or a vacuum evaporation method in addition to the spin coating method. Is also good.

Then, in the crystallization step shown in FIG. 25B, first, a heat treatment is performed at 400 to 500 ° C. for about 1 hour to reduce the hydrogen content of the amorphous silicon film to 5 atom% or less. If the hydrogen content of the amorphous silicon film has this value from the beginning after film formation, this heat treatment is not always necessary. Then, thermal annealing is performed in a nitrogen atmosphere at 550 to 600 ° C. for 1 to 8 hours using a furnace annealing furnace. Through the above steps, a crystalline semiconductor layer 1105 including a crystalline silicon film can be obtained (FIG. 25C). However, when the crystalline semiconductor layer 1105 formed by this thermal annealing is macroscopically observed with an optical microscope, it may be observed that an amorphous region locally remains in such a case. Similarly, in Raman spectroscopy, an amorphous component having a broad peak at 480 cm ^-1 is observed. Therefore, increasing the crystallinity by treating the crystalline semiconductor layer 1105 by the laser annealing method described in the first embodiment after the thermal annealing can be applied as an effective means.

FIG. 26A shows an embodiment of a crystallization method similarly using a catalytic element, in which a layer containing a catalytic element is formed by a sputtering method. First, a base film 1202a, a base film 1202b, and a semiconductor layer 1203 having an amorphous structure are formed with a thickness of 25 to 80 nm over a glass substrate 1201. Then, the semiconductor layer 1 having an amorphous structure
An oxide film (not shown) of about 0.5 to 5 nm is formed on the surface of the substrate 203. For the oxide film having such a thickness, a corresponding film may be positively formed by a plasma CVD method, a sputtering method, or the like. However, the oxide film may be formed in an oxygen atmosphere heated to 100 to 300 ° C. and turned into plasma. The surface of the semiconductor layer 1203 having a crystalline structure may be exposed, or a hydrogen peroxide solution (H
Semiconductor layer 120 having an amorphous structure in a solution containing ₂ O ₂ )
3 may be formed by exposing the surface. Alternatively, ozone is generated by irradiation with ultraviolet light in an atmosphere containing oxygen, and the semiconductor layer 1203 having an amorphous structure is formed in the ozone atmosphere.
It can also be formed by exposing.

As described above, the layer 1204 containing the catalyst element is formed on the semiconductor layer 1203 having a thin oxide film on the surface and having an amorphous structure by a sputtering method. The thickness of this layer is not limited, but may be about 10 to 100 nm. For example, with Ni as a target, Ni
Forming a film is an effective method. In the sputtering method, part of the high-energy particles composed of the catalyst element accelerated by an electric field also fly to the substrate side, and the oxide layer formed on or near the surface of the semiconductor layer 1203 having an amorphous structure is formed. Driven into the film. Although the ratio varies depending on the plasma generation conditions and the bias state of the substrate, it is preferable that the amount of the catalytic element implanted into the vicinity of the surface of the semiconductor layer 1203 having an amorphous structure or the oxide film be reduced to one.
It is preferable that the density be about 10 ¹¹ to 1 10 ¹⁴ atoms / cm ² .

After that, the layer 1204 containing the catalyst element is selectively removed. For example, when this layer is formed of a Ni film, it can be removed with a solution such as nitric acid, or can be removed by treating with an aqueous solution containing hydrofluoric acid.
The oxide film formed over the film and the semiconductor layer 1203 having an amorphous structure can be removed at the same time. In any case, the amount of the catalyst element near the surface of the semiconductor layer 1203 having an amorphous structure is set to be about 1 × 10 ¹¹ to 1 × 10 ¹⁴ atoms / cm ² . Then, as shown in FIG. 26B, FIG.
The crystallization step by thermal annealing is performed in the same manner as in FIG. 5B, whereby a crystalline semiconductor layer 1205 can be obtained (FIG. 26C).

If the island-shaped semiconductor layers 104 to 108 are formed from the crystalline semiconductor layer 1105 and the crystalline semiconductor layer 1205 manufactured in FIG. 25 or FIG. 26, an active matrix substrate is completed in the same manner as in Embodiments 5 to 7. Can be done. However, when a catalyst element that promotes crystallization of silicon is used in the crystallization step, a small amount (about 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ ) of a catalyst element remains in the island-shaped semiconductor layer. I do. Of course, even in such a state, the TFT
Can be completed, but it is more preferable to remove the remaining catalyst element from at least the channel formation region. One of the means for removing this catalytic element is phosphorus (P).
There is a means for utilizing the gettering action by

The gettering process using phosphorus (P) for this purpose can be performed simultaneously in the activation step described with reference to FIG. This situation will be described with reference to FIG. The concentration of phosphorus (P) necessary for gettering is high
The impurity concentration may be about the same as the impurity concentration of the p-type impurity region, and the thermal annealing in the activation step transfers the catalyst element from the channel formation region of the n-channel TFT and the p-channel TFT to the impurity region containing phosphorus (P) at that concentration. It can be segregated (in the direction of the arrow shown in FIG. 27). As a result, a catalyst element of about 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ segregated in the impurity region. The TFT thus manufactured has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and good characteristics can be achieved.

[Embodiment 9] (Manufacturing method of color filter) When a direct-view type liquid crystal display device is manufactured, a color filter may be formed on a counter substrate.

First, a black matrix 92 is formed as shown in FIG. Hereinafter, the black matrix 92 is referred to as BM
92. The metal thin film is sputtered on the substrate 91. In this embodiment, chromium is used as the metal. A positive resist is applied, exposed, developed using an aqueous alkali solution, and then baked. Using the positive resist as a mask, the chromium film is etched (using an aqueous solution of cerium nitrate ammonium and perchloric acid), and finally the positive resist is peeled off to form BM92.

A pigment-dispersed photosensitive acrylic resin in which a red pigment is dispersed in acrylic is applied to the substrate 91 on which the BM 92 has been applied, and dried. After that, when exposure is performed through the formed photomask, a portion irradiated with light is solidified. Next, after developing using an alkali developer and baking,
A colored layer 93a having a red pattern (indicated by R in FIG. 29) is obtained. Colored layer 93 having green pattern
b (shown by G in FIG. 29) and the pattern of the colored layer 93c (shown by B in FIG. 29) having a blue pattern,
A colored layer 93 having a color filter (RGB) pattern of three primary colors of blue and green is obtained.

The ITO film 94 is formed by a sputtering method. In this embodiment, the ITO film is used, but any transparent conductive film may be used.

[0286] An epoxy acrylate-based material is spin-coated and thermally cured at 200 to 250 ° C to form an overcoat layer 95.

Although chromium is used as the metal BM in this embodiment, a resin BM may be used. A patterning method can be used for the method of manufacturing the resin BM as in the case of the metal BM. When the liquid crystal display device of the present invention provided with the BM is applied to a normally white mode, light leakage is eliminated and contrast is improved.

In the present embodiment, the coloring layer (color filter) is formed by using the pigment dispersion method.
The electrodeposition method may be used.

In this embodiment, when a colored layer (color filter) is formed, an overcoat layer is formed to improve smoothness. However, in order to reduce costs, the overcoat layer is not formed. Is also good.

[Embodiment 10] A CMOS circuit and a pixel portion formed by carrying out the invention of this specification can be used for various liquid crystal display devices (active matrix type liquid crystal displays). That is, the invention of the present specification can be applied to all electronic devices in which the electro-optical device is incorporated in the display unit.

As such electronic equipment, a video camera, digital camera, projector (rear or front type), head mounted display (goggle type display), car navigation, car stereo,
A personal computer, a portable information terminal (a mobile computer, a mobile phone, an electronic book, or the like), a DVD player, an electronic game machine, and the like can be given. Examples of these are shown in FIGS. 30, 31 and 32.

FIG. 30A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like. The invention of this specification can be applied to the image input unit 2002, the display unit 2003, and other signal control circuits.

FIG. 30B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6 and so on. The invention of this specification can be applied to the display portion 2102 and other signal control circuits.

FIG. 30C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like. The present invention can be applied to the display portion 2205 and other signal control circuits.

FIG. 30D shows a goggle type display, which includes a main body 2301, a display portion 2302, and an arm portion 230.
3 and so on. The invention of this specification can be applied to the display portion 2302 and other signal control circuits.

FIG. 30E shows a player using a recording medium on which a program is recorded (hereinafter, referred to as a recording medium), and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The invention of this specification is based on the display 240
2 and other signal control circuits.

FIG. 30F shows a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, operation switches 2504, an image receiving portion (not shown), and the like. The invention of this specification can be applied to the display portion 2502 and other signal control circuits.

FIG. 31A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like. The invention of this specification can be applied to a liquid crystal display device 2808 described later and a signal control circuit which constitutes a part of the projection device 2601.

FIG. 31B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like. The invention of this specification relates to a liquid crystal display device 2808 forming a part of the projection device 2702.
And other signal control circuits.

FIG. 31 (C) shows the projection device 2601 and the projection device 2 in FIGS. 31 (A) and 31 (B).
702 is a diagram showing an example of the structure of FIG. Projection device 260
1. The projection device 2702 includes a light source optical system 2801, a mirror 2802, mirrors 2804 to 2806, a dichroic mirror 2803, a prism 2807, and a liquid crystal display device 28.
08, a phase difference plate 2809, and a projection optical system 2810. The projection optical system 2810 is configured by an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 31D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 31C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
It comprises a lens array 2814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 29D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical lens, a film having a polarizing function, a film for adjusting a phase difference,
An optical system such as an R film may be provided.

However, in the projector shown in FIG. 31, a case where a transmission type liquid crystal display device is used is shown, and an example of application to a reflection type liquid crystal display device is not shown.

FIG. 32A shows a mobile phone,
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on. The invention of this specification can be applied to the audio output unit 2902, the audio input unit 2903, the display unit 2904, and other signal control circuits.

FIG. 32B shows a portable book (electronic book), which includes a main body 3001, a display portion 3002, a display portion 3003,
Storage medium 3004, operation switch 3005, antenna 3
006 etc. The invention of this specification is based on the display units 3002,
003 and other signal circuits.

FIG. 32C shows a display, which includes a main body 3101, a support base 3102, a display portion 3103, and the like.
The invention of this specification can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and it can be applied to electronic devices in all fields.

[0307]

According to the present invention, a multi-domain vertical alignment type liquid crystal display with a wide viewing angle display characterized in that the variation in the substrate spacing is small (the cell gap is uniform) and the switching direction of the liquid crystal molecules is controlled. An apparatus can be provided.

In the case where the manufacturing process of the liquid crystal display device of the present invention is used, the rubbing step can be omitted (the rubbing-less process is realized), and at the same time, the spacer dispersing step can be omitted.

Further, when the liquid crystal display device of the present invention is used, a stable pretilt angle can be obtained. Therefore, a liquid crystal display which enlarges and displays an image of a liquid crystal light valve by several tens of times like a liquid crystal projector is used. It is possible to realize.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a liquid crystal display device according to a first embodiment and a diagram illustrating directors of liquid crystal molecules in sub-pixels.

FIGS. 2A and 2B are a cross-sectional view of a liquid crystal display device according to a second embodiment and a diagram illustrating directors of liquid crystal molecules in sub-pixels.

FIGS. 3A and 3B are a cross-sectional view of a liquid crystal display device according to a third embodiment and a diagram illustrating directors of liquid crystal molecules in sub-pixels. FIGS.

FIG. 4 is a cross-sectional view of a liquid crystal display device according to a fourth embodiment and a diagram showing directors of liquid crystal molecules in a sub-pixel.

FIG. 5 is a schematic top view of the liquid crystal display device according to the first to fourth embodiments.

FIG. 6 is a schematic top view of the pixel unit in FIG. 1;

FIG. 7 is a schematic top view of the pixel unit in FIG. 2;

FIG. 8 is a schematic top view of the pixel unit in FIG. 3;

FIG. 9 is a schematic top view of the pixel unit in FIG. 4;

FIG. 10 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 11 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 12 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 13 is a cross-sectional view illustrating a transmission type liquid crystal display device of the present invention.

FIG. 14 is a top view showing a transmission type liquid crystal display device of the present invention.

FIG. 15 is a top view illustrating a pixel TFT.

FIG. 16 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit, and a cross-sectional view illustrating a transmission-type liquid crystal display device of the present invention.

FIG. 17 is a top view illustrating a pixel TFT.

FIG. 18 is a top view showing a transmission type liquid crystal display device of the present invention.

FIG. 19 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 20 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 21 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 22 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 23 is a cross-sectional view illustrating a transmission type liquid crystal display device of the present invention.

FIG. 24 is a top view showing a transmission type liquid crystal display device of the present invention.

FIG. 25 is a cross-sectional view illustrating a manufacturing process of a crystalline semiconductor layer.

FIG 26 is a cross-sectional view illustrating a manufacturing process of a crystalline semiconductor layer.

FIG. 27 is a cross-sectional view illustrating a manufacturing process of a crystalline semiconductor layer.

FIG. 28 is a diagram showing a configuration of a counter substrate including a coloring layer (color filter) in Embodiment 9.

FIG. 29: Definition of the taper angle for a wall-shaped spacer in this specification.

FIG. 30 illustrates an example of a semiconductor device.

FIG. 31 illustrates a configuration of a projection type liquid crystal display device.

FIG. 32 illustrates an example of a portable information terminal.

FIG. 33 is a diagram showing a display mode of a conventional liquid crystal display device.

Claims (17)

[Claims] 1. A display comprising a pair of substrates, at least one of which is made of a transparent insulating substrate, formed with spacers for keeping a constant interval between the pair of substrates, and a liquid crystal sandwiched between the pair of substrates. A liquid crystal electro-optical device, wherein the liquid crystal is inclined from a normal direction of the substrate by an inclined side surface of the spacer formed on at least one of the pair of substrates. 2. A display comprising a pair of substrates, at least one of which is made of a transparent insulating substrate, formed with spacers for keeping a constant distance between the pair of substrates, and a liquid crystal sandwiched between the pair of substrates. An apparatus, wherein the inclined side surfaces of the spacer formed on at least one of the pair of substrates and the concave or convex shape of the surface provided on at least one of the substrates, from the normal direction of the substrates. A liquid crystal electro-optical device, wherein the liquid crystal is tilted. 3. A pair of substrates, at least one of which is a transparent insulating substrate, wherein at least one of the substrates has an alignment film and a spacer for keeping a distance between the pair of substrates constant, A display device in which liquid crystal is sandwiched between a pair of substrates, wherein the liquid crystal is inclined from a normal direction of the substrate by inclined side surfaces of the spacer formed on at least one of the pair of substrates. A liquid crystal electro-optical device, characterized in that: 4. A pair of substrates, at least one of which is made of a transparent insulating substrate, wherein at least one of the substrates has an alignment film and a spacer formed to keep a distance between the pair of substrates constant. A display device in which liquid crystal is sandwiched between the pair of substrates, wherein the inclined side surfaces of the spacers formed on at least one of the pair of substrates and a surface provided on at least one of the substrates; By the concave shape or the convex shape, from the normal direction of the substrate,
A liquid crystal electro-optical device, wherein the liquid crystal is tilted. 5. A liquid crystal electro-optical device according to claim 1, wherein said spacer has a constant side taper angle. 6. The method according to claim 1, wherein
A liquid crystal electro-optical device, wherein electrodes are provided on a pair of substrates at least one of which is made of a transparent insulating substrate, and the electrode sides are opposed to each other. 7. The method according to claim 1, wherein
A liquid crystal electro-optical device, wherein an electrode is provided on one of the transparent insulating substrates, and the electrode is not present on the opposite surface of the other substrate. 8. The liquid crystal display device according to claim 6, wherein the liquid crystal is tilted from a normal direction of the substrate by a side surface taper angle of the spacer and a concave or convex shape of an electrode provided on at least one substrate. Liquid crystal electro-optical device. 9. The method according to claim 7, wherein a pretilt angle of the liquid crystal is controlled by a taper angle of the side surface of the spacer and a concave shape or a convex shape of an electrode provided on at least one substrate to align the liquid crystal. Characteristic liquid crystal electro-optical device. 10. The liquid crystal electro-optical device according to claim 1, wherein the spacer is formed before forming the alignment film. 11. The spacer according to claim 1, wherein the side face taper angle of the spacer is 75.0 ° to 85.0 °.
9.9 °, preferably 82 ° to 87 °, a liquid crystal electro-optical device. 12. The liquid crystal electro-optical device according to claim 1, wherein a cross section of the spacer cut in parallel with the transparent insulating substrate has a stripe shape. 13. The liquid crystal electro-optical device according to claim 12, wherein the spacer is branched. 14. The spacer according to claim 1, wherein the spacer is an organic resin material containing at least one of acrylic, polyimide, polyimide amide, and epoxy, or silicon oxide. A liquid crystal electro-optical device, comprising a material selected from the group consisting of silicon, silicon nitride, and silicon oxynitride, or an inorganic material including a laminated film thereof. 15. The liquid crystal electro-optic device according to claim 1, wherein the major axis direction of the liquid crystal molecules is substantially parallel to the side surface near the inclined side surface of the spacer. apparatus. 16. A liquid crystal electro-optical device according to claim 1, wherein said liquid crystal has a negative dielectric anisotropy. 17. A personal computer, a video camera, a portable information terminal, wherein the liquid crystal electro-optical device according to claim 1 is used.
Digital camera, projector, head mounted display, car navigation, car stereo, DVD
Player or electronic play equipment.