JP2001024501A - Level shift circuit and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the noise resistance of a level shift circuit. SOLUTION: A level conversion circuit formed of 1st level shift part (Q1 to Q3) for converting 1st amplitude into 2nd amplitude and a 2nd level shift part (Q4 to Q7) for converting the 2nd amplitude obtained from the 1st level shift part (Q1 to Q3) into 3rd amplitude different from the 2nd amplitude is provided with a step-down means Q8 for stepping down operation power supply (Vdd2=3.3 V) to be supplied to the 2nd level shift part (Q4 to Q7) and supplying the step-down voltage to the 1st level shift part (Q1 to Q3) to improve noise resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift circuit for level shifting a signal and a semiconductor integrated circuit including the same.

[0002]

2. Description of the Related Art A plurality of input / output circuits for exchanging signals between the inside of a chip and the outside of the chip are provided at the periphery of the semiconductor integrated circuit. This input / output circuit includes an input circuit for taking in a signal from the outside of the chip to the inside of the chip, and conversely, an output circuit for outputting a signal inside the chip to the outside of the chip.

The output circuit is provided with an output buffer for driving an external signal line via an external pin. Further, in order to speed up the internal operation of the semiconductor integrated circuit, there is a case where the power supply voltage supplied from the outside is reduced to a lower value and then supplied to each logic circuit. Since the output buffer cannot be directly driven by the output level of the circuit, a level shift circuit for converting the signal amplitude is provided in a stage preceding the output buffer.

As an example of a document describing a level shift circuit, see “How to Use a CMOS Circuit (I) (No. 146)” issued by the Industrial Research Institute on March 1, 1994.
Pp.).

[0005]

The inventors of the present invention have studied the level shift circuit, and have found that the level shift circuit is susceptible to noise under certain conditions.

FIG. 6 shows a circuit to be compared with the level shift circuit according to the present invention. In this circuit and the circuit according to the present invention, it is assumed that the withstand voltage of the gate oxide film is 2.5 V due to process restrictions.

A p-channel MOS transistor Q61
And n-channel MOS transistor Q62 are connected in series with each other to form an inverter. Further, a p-channel MOS transistor Q6 is connected to this inverter.
3 are connected in series. The source electrode of the p-channel type MOS transistor Q61 has a high potential side power supply Vdd1 =
2.5V is supplied. The gate and drain electrodes of the p-channel MOS transistor Q63 are ground GN
D. p-channel type MOS transistor Q
When a low (L) level signal is input to the gate electrodes of the MOS transistor 61 and the n-channel MOS transistor Q62, p
A high (H) level signal is output from the serial connection node of the channel type MOS transistor Q61 and the n-channel type MOS transistor Q62.

Here, the p-channel MOS transistor Q63 is replaced by a p-channel MOS transistor Q61.
This is provided to regulate the low level of the series connection node of the P-channel MOS transistor Q62 and the n-channel MOS transistor Q62 to 0.8 V, and to protect the gate oxide film breakdown voltage of the next-stage p-channel MOS transistor Q64. Thereby, the p-channel type M
When a signal having an amplitude of 0.0 to 2.5 V is input to the gate electrodes of the OS transistor Q61 and the n-channel MOS transistor Q62, at the node of the p-channel MOS transistor Q61 and the n-channel MOS transistor Q62 connected in series, 0.8 V to 2.5 V amplitude is obtained.

The p-channel MOS transistor Q
An output signal from a series connection node of the transistor 61 and the n-channel MOS transistor Q62 is transmitted to the gate electrode of a p-channel MOS transistor Q64 arranged at the subsequent stage. A high-potential-side power supply Vdd2 = 3.3 V is supplied to the source electrode of the p-channel MOS transistor Q64. The above p-channel type MOS transistor Q65
Have an n-channel MOS transistor Q66 and p
A channel type MOS transistor Q67 is connected in series. The high-potential-side power supply Vdd1 = 2.5 V is supplied to the gate electrode of the n-channel MOS transistor Q65. An input signal having an amplitude of 0.0 to 2.5 V is transmitted to the gate electrode of n-channel MOS transistor Q66. The drain electrode and the gate electrode of p-channel type MOS transistor Q67 are coupled to ground GND. The p-channel MOS transistors Q64 and n
An output signal is obtained from a series connection node with channel type MOS transistor Q65. This output signal is obtained by inverting the logic of the signal input to the gate electrode of the p-channel MOS transistor Q64, and has an amplitude of 0.8 to 3.3V. The amplitude does not become 0.0 V because the p-channel MOS transistor Q67 is provided.

In the above configuration, the high potential side power supply Vdd
Let us consider a case where negative noise is mixed in 1 and positive noise is mixed in the high potential side power supply Vdd2. The negative noise mixed into the high-potential power supply Vdd1 is
d1 = 2.5 V is temporarily reduced, and the positive noise mixed into the high-potential power supply Vdd2 acts to temporarily increase the high-potential power supply Vdd2.

P-channel type MOS transistor Q61
When the above-mentioned noise condition is satisfied when the series connection node of the n-channel MOS transistor Q62 and the n-channel MOS transistor Q62 is at the high (H) level, the gate-source voltage Vgs of the p-channel MOS transistor Q64 is temporarily increased. As a result, the p-channel MOS transistor Q64, which has been in the off state, shifts to the on state, and the output signal, which should be low, is changed to high. Such a logical inversion causes a malfunction of the subsequent circuit.

An object of the present invention is to provide a technique for improving the noise resistance of a level shift circuit.

[0013]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, the first amplitude is changed to a second amplitude different from the first amplitude.
A first level shifter for converting the amplitude into an amplitude;
A second level shifter for converting the second amplitude from the level shifter into a third amplitude different from the second amplitude; and a step-down operation power supply supplied to the second level shifter, the first level shifter comprising: And a step-down means for supplying the voltage to the circuit.

According to the above-mentioned means, the step-down means steps down the operation power supplied to the second level shift unit and supplies it to the first level shift unit. Thereby, the voltage supplied to the first level shift unit is derived from the voltage supplied to the second level shift unit. Therefore, the second
When noise is included in the voltage supplied to the level shift unit, noise having the same polarity as the noise also appears in the first level shift unit. Therefore, the noise applied to the gate-source voltage of the transistor in the second level shift unit is reduced. Eliminate the effects. This achieves improved noise immunity.

At this time, the first level shifter is p
Channel type MOS transistor and n channel type MO
An inverter including an S transistor connected in series;
And a p-channel MOS transistor for raising the low-level output signal of the inverter from the ground level.

A first level shift unit for converting the first amplitude into a second amplitude and a third amplitude different from the first amplitude, and a signal having the second amplitude; An inverter for inverting, a second level shifter for obtaining a signal of a fourth amplitude based on the signal of the third amplitude and an output signal of the inverter, and the two of the two transistors cross-coupled to each other; A step-down means for stepping down and supplying an operation power supply to the second level shift unit as an operation power supply for a transistor series circuit including a transistor on the side outputting the signal of the third amplitude; A shift circuit can be formed.

At this time, in order to make the low-level potential of the third amplitude higher than the ground level, the signal of the first amplitude is applied between the transistor outputting the signal of the third amplitude and the ground. An operation-controlled p-channel MOS transistor can be provided.

Further, a p-channel MOS transistor in which a gate electrode and a drain electrode are coupled can be applied as the step-down means.

When a semiconductor integrated circuit includes an internal logic circuit and an input / output circuit that enables signals to be exchanged between the internal logic circuit and an external circuit, the input / output circuit includes: It can be configured to include the level shift circuit having the above configuration.

[0021]

FIG. 4 shows a configuration example of a semiconductor integrated circuit according to the present invention.

The semiconductor integrated circuit 31 shown in FIG. 4 is not particularly limited. However, the ASIC (Application Specification) formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.
fic IC). An internal logic circuit 32 having a predetermined logic function realized by a gate array method is provided.
Around such an internal logic circuit 32, a plurality of input / output circuits 33 for enabling various signals to be exchanged between the internal logic circuit and the outside are arranged. Each input / output circuit 33 includes an output circuit for externally outputting an output signal of the internal logic circuit and an input circuit for taking in a signal from the outside into the internal logic circuit.

FIG. 5 shows a configuration example of the output circuit.

The output circuit 50 shown in FIG. 5 has an internal amplitude of 0.0 to 1.8 V of 0.0 to 1.8 V, though not particularly limited.
0.0 to 2.5 for level shifting to 2.5V amplitude
V amplitude generation circuit 51; 0.8-3.3V amplitude generation circuit 52 for level-shifting the output signal of 0.0-2.5V amplitude generation circuit 51 to 0.8-3.3V amplitude; The output signal of the amplitude generation circuit 51 is set to 0.8
0.8 to 2. for level shifting to .about.2.5V amplitude.
A 5V amplitude generating circuit 53; a 0.0-2.5V amplitude generating circuit 54 for level-shifting the internal amplitude of 0.0-1.8V to a 0.0-2.5V amplitude;
Channel type MOS transistors Q51, Q52 and n
Channel type MOS transistors Q53 and Q54 are provided.

P-channel type MOS transistor Q51
Are coupled to the high potential side power supply Vdd2 = 3.3V.

P channel type MOS transistor Q51
The output signal of the 0.8 to 3.3 V amplitude generation circuit 52 is transmitted to the gate electrode of. The output signal of the 0.8 to 2.5 V amplitude generation circuit 53 is transmitted to the gate electrode of the p-channel MOS transistor Q52. n-channel type MO
The gate electrode of the S transistor Q53 has a high potential side power supply V
dd1 = 2.5V is supplied. n-channel type MOS
0.0 to 2.5 V is applied to the gate electrode of the transistor Q54.
An output signal of amplitude generation circuit 54 is transmitted. The source electrode of n-channel type MOS transistor Q54 is coupled to ground GND.

In the above configuration, the 0.0-1.8 V internal amplitude is converted to 0.0-2.5 V amplitude by the 0.0-2.5 V amplitude generation circuits 51 and 54, respectively. 0.
The output signal of the 0 to 2.5 V amplitude generation circuit 51 is 0.8 to
The voltage is converted to 0.8 to 3.3 V by the 3.3 V amplitude generation circuit 52 and then transmitted to the gate electrode of the p-channel MOS transistor Q51 in the subsequent stage. Also, 0.8-
The amplitude is converted to 0.8 to 2.5 V by the 2.5 V amplitude generation circuit 53, and then transmitted to the gate electrode of the subsequent p-channel MOS transistor Q52. In addition, 0.0
The output signal of the .about.2.5 V amplitude generating circuit 54 is transmitted to the subsequent n-channel MOS transistor Q54. Thereby, the p-channel MOS transistors Q52 and n
An output signal having an external amplitude of 0.0 to 3.3 V is obtained from a series connection node with the channel type MOS transistor Q53.

FIG. 1 shows an example of the configuration of the 0.8 to 3.3 V amplitude generation circuit 52.

P-channel type MOS transistor Q1
And n-channel MOS transistor Q2 are connected in series with each other to form an inverter. Further, a p-channel MOS transistor Q3 is connected in series to the inverter. The gate electrode and the drain electrode of the p-channel MOS transistor Q3 are connected to the ground GND.

The source electrode of the p-channel type MOS transistor Q1 is a p-channel type MOS transistor
Via the OS transistor Q8, the high-potential-side power supply Vdd2 =
Coupled to 3.3V. The gate electrode and the drain electrode of the p-channel MOS transistor Q8 are coupled, and the high potential side power supply Vdd2 = 3.3V is reduced to 2.5V by the p-channel MOS transistor Q1. And a p-channel MOS transistor Q
3 regulates the low level of the series connection node of the p-channel MOS transistor Q1 and the n-channel MOS transistor Q2 to 0.8V. Therefore, the signal amplitude at the series connection node of the p-channel MOS transistor Q1 and the n-channel MOS transistor Q2 is
It is set to 0.8-2.5V. The p-channel MOS transistor Q3 is a p-channel MOS transistor Q3.
It is provided to regulate the low level of the series connection node of the 1 and n-channel MOS transistor Q2 to 0.8V. Accordingly, when a signal having an amplitude of 0.0 to 2.5 V is input to the gate electrodes of the p-channel MOS transistor Q1 and the n-channel MOS transistor Q2, p
In the series connection node of the channel type MOS transistor Q1 and the n-channel type MOS transistor Q2,
0.8 V to 2.5 V amplitude is obtained. In this sense, the MOS transistors Q1 to Q3 form a first level shift unit.

Here, the output signal from the series connection node of the p-channel MOS transistor Q1 and the n-channel MOS transistor Q2 is transmitted to the gate electrode of the p-channel MOS transistor Q4 arranged at the subsequent stage. A high-potential-side power supply Vdd2 = 3.3 V is supplied to the source electrode of the p-channel MOS transistor Q4. An n-channel MOS transistor Q6 and an n-channel MOS transistor Q6 are connected in series to the p-channel MOS transistor Q5. The high-potential-side power supply Vdd1 = 2.5 V is supplied to the gate electrode of the n-channel MOS transistor Q5.
An input signal having an amplitude of 0.0 to 2.5 V is transmitted to the gate electrode of n-channel MOS transistor Q6. p
The drain electrode and the gate electrode of the channel type MOS transistor Q7 are connected to the ground GND. The p-channel MOS transistor Q4 and the n-channel type M
An output signal is obtained from a series connection node with the OS transistor Q5. This output signal is obtained by inverting the logic of the signal input to the gate electrode of the p-channel MOS transistor Q4, and has an amplitude of 0.8 to 3.3V. In this sense, the MOS transistors Q4 to Q7 form a second level shift unit.

The amplitude does not become 0.0 V because the p-channel MOS transistor Q7 is provided.

In the above configuration, the p-channel type MO
The S transistor Q8 reduces the operating voltage Vdd2 = 3.3V supplied to the p-channel type MOS transistor Q4 to 2.5V, and reduces the voltage to the first level shifter (Q1
To Q3). Thus, the voltage supplied to the p-channel MOS transistor Q12 is
It is derived from the voltage supplied to the channel type MOS transistor Q4. Therefore, when noise is included in the voltage supplied to the second level shift unit, noise of the same polarity also appears in the p-channel MOS transistor Q1, which is generated between the gate and the source of the p-channel MOS transistor Q4. Eliminate the effect on voltage Vgs. That is, when a noise such that Vdd2 = 3.3 V rises occurs, the same voltage change is caused by the MOS transistor Q8.
, The p-channel MOS transistor Q
4 does not cause an increase in the gate-source voltage Vgs. For this reason, undesirable logical inversion of the output signal due to the noise does not occur, and noise resistance can be improved.

FIG. 2 shows another example of the configuration of the amplitude generating circuit.

In the circuit shown in FIG. 2, 0.0 to 1.8
The signal of V amplitude is converted to 0.8 to 3.3 V amplitude.

In FIG. 2, components having the same functions as those shown in FIG. 1 are denoted by the same reference numerals.

A p-channel type MOS transistor Q10
And n-channel MOS transistor Q11 are connected in series, and p-channel MOS transistor Q12 and p
The channel type MOS transistor Q13 is connected in series. A series connection node of p-channel MOS transistor Q10 and n-channel MOS transistor Q11 is coupled to the gate electrode of p-channel MOS transistor Q12, and a series connection node of p-channel MOS transistors Q12 and Q13 is p-channel M transistor.
Coupled to the gate electrode of OS transistor Q10. n
A signal having an amplitude of 0.0 to 1.8 V is transmitted to the gate electrode of the channel type MOS transistor Q11 and the gate electrode of the p-channel type MOS transistor Q13. This circuit is a so-called cross-coupled latch circuit. The drain electrode of the n-channel MOS transistor Q11 is set to a node N2, from which a voltage of 0.0 to 2.5 V is applied.
An amplitude signal is obtained, which is transmitted to the gate electrode of n-channel MOS transistor Q6 via an inverter having p-channel MOS transistor Q14 and n-channel MOS transistor Q15 connected in series. Since Q13 is a p-channel MOS transistor, the low level of the source electrode of p-channel MOS transistor Q13 is 0.8V. The source electrode of the p-channel type MOS transistor Q13 is set to a node N3, from which a voltage of 0.8 to 2.5 V is applied.
A signal having an amplitude is obtained, which is a p-channel type M
It is taken into the gate electrode of the OS transistor Q4.

Here, the MOS transistors Q10 to Q1
3 form a first level shift unit, and the MOS transistors Q4 to Q7 form a second level shift unit.

As an example of the step-down means, there is provided a p-channel MOS transistor Q17 in which a gate electrode and a drain electrode are connected. The power supply for operation of the p-channel type MOS transistor Q12 is the p-channel type M transistor.
It is supplied via the OS transistor Q17. That is,
Vdd2 = 3.3 V is stepped down to 2.5 V by p-channel MOS transistor Q17 and
It is supplied to the OS transistor Q12. Thus, the voltage supplied to the p-channel MOS transistor Q12 is changed to the p-channel MOS transistor Q4.
Derived from the voltage supplied to the Therefore, p-channel type M
When noise is included in the voltage supplied to the OS transistor Q4, noise of the same polarity also appears in the p-channel MOS transistor Q12, so that the influence on the gate-source voltage of the p-channel MOS transistor Q4 is affected. Is eliminated, thereby improving noise immunity.

FIG. 3 shows another example of the configuration of the amplitude generation circuit.

The circuit shown in FIG. 3 is significantly different from the circuit shown in FIG. 2 in that the p-channel MOS transistors Q16, Q18, Q19 and the n-channel MOS
The point is that an S transistor Q19 is provided. The p-channel MOS transistor Q19 and the n-channel MOS transistor Q20 are connected in series to form an inverter. A signal having an amplitude of 0.0 to 1.8 V is directly input to the p-channel MOS transistor Q16.
A signal having an amplitude of 0.0 to 1.8 V is a p-channel MOS
The transistor Q19 and the n-channel MOS transistor Q20 are inverted by an inverter connected in series and then input. When the input signal having the amplitude of 0.0 to 1.8 V is shifted from the low level to the high level, the p-channel MOS transistor Q16 is quickly turned off, so that a through current flowing through Q10 and Q11 is blocked. Further, when the input signal having the amplitude of 0.0 to 1.8 V is shifted from the high level to the low level, the p-channel MOS transistor Q18 is quickly turned off, so that the through current flowing through Q12 and Q13 is blocked. Is done.

Also in the circuit shown in FIG. 3, the voltage supplied to the p-channel MOS transistor Q18 is reduced by the provision of the p-channel MOS transistor Q17 as a step-down means.
It is derived from the voltage supplied to S transistor Q12. Therefore, when noise is included in the voltage supplied to the p-channel MOS transistor Q4, noise of the same polarity also appears in the p-channel MOS transistor Q12. The effect on voltage is eliminated. As a result, noise resistance can be improved.

Although the invention made by the present inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

For example, a Zener diode or a resistor can be used as the step-down means in addition to a p-channel MOS transistor. And they can be located outside the semiconductor chip.

In the above description, the invention made mainly by the present inventor is described in terms of ASI, which is a field of application in which the background was used.
Although the description has been given of the case where the present invention is applied to C, the present invention is not limited thereto, and can be widely applied to various semiconductor integrated circuits.

The present invention can be applied on condition that at least signals having different amplitudes are handled.

[0047]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the operation power supply supplied to the second level shift unit is stepped down to form the operation power supply for the first level shift unit, so that the voltage supplied to the first level shift unit is: When the voltage supplied to the second level shift unit includes noise because the voltage is derived from the voltage supplied to the second level shift unit, noise of the same polarity also appears in the first level shift unit. Thereby, it is possible to eliminate the influence on the gate-source voltage of the transistor in the second level shift unit, and to improve the noise resistance.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration example of a main part in a semiconductor integrated circuit according to the present invention.

FIG. 2 is a circuit diagram illustrating another configuration example of a main part in the semiconductor integrated circuit.

FIG. 3 is a circuit diagram illustrating another configuration example of a main part in the semiconductor integrated circuit.

FIG. 4 is an explanatory diagram of an overall configuration example of the semiconductor integrated circuit.

FIG. 5 is a block diagram illustrating a configuration example of a main part in the semiconductor integrated circuit.

FIG. 6 is a circuit diagram of a configuration to be compared with a main part in the semiconductor integrated circuit.

[Explanation of symbols]

51, 54 0.0 to 2.5 V amplitude generation circuit 52 0.8 to 3.3 V amplitude generation circuit 53 0.8 to 2.5 V amplitude generation circuit 31 Semiconductor integrated circuit 32 Internal logic circuit 33 Input / output circuit Q1, Q3 , Q8, Q10, Q12, Q17 P-channel MOS transistor Q2 N-channel MOS transistor

Claims (6)

[Claims] A first level shifter for converting the first amplitude into a second amplitude different from the first amplitude; and a first level shifter for converting the second amplitude from the first level shifter into a third amplitude different therefrom. A level shift circuit comprising: a second level shift unit; and step-down means for stepping down an operation power supplied to the second level shift unit and supplying the operation power to the first level shift unit. 2. A p-channel MOS transistor and an n-channel MOS transistor
An inverter having a channel type MOS transistor connected in series; and a p-channel type MOS transistor for raising a low level output signal of the inverter from a ground level, and converting the first amplitude into a second amplitude different from the first amplitude. And a second level shifter for converting the second amplitude from the first level shifter into a third amplitude different from the first level shifter. Step-down means for stepping down an operation power supply and supplying the stepped-down power to the first level shift unit. 3. Two transistors cross-coupled to each other, wherein the first amplitude is different from the second amplitude and the third amplitude.
A first level shifter for converting the signal into an amplitude, an inverter for inverting the signal having the second amplitude, and a signal having a fourth amplitude based on the signal having the third amplitude and the output signal of the inverter. As a power supply for operating a transistor series circuit including a transistor that outputs the signal of the third amplitude out of the two transistors cross-coupled to each other. And a step-down means for stepping down and supplying the operation power to be supplied. 4. A p-channel MOS transistor whose operation is controlled by the signal of the first amplitude, between a transistor on the side outputting the signal of the third amplitude and ground of two transistors cross-coupled to each other. 4. The level shift circuit according to claim 3, further comprising: 5. The level shift circuit according to claim 1, wherein a p-channel MOS transistor having a gate electrode and a drain electrode coupled thereto is applied as said step-down means. 6. A semiconductor integrated circuit comprising: an internal logic circuit; and an input / output circuit that enables signals to be exchanged between the internal logic circuit and an external circuit. A semiconductor integrated circuit comprising the level shift circuit according to any one of claims 1 to 5.