JP2000122753A - Vrm mispackaging prevention circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the mispackaging of a voltage regulating module(VRM) for +5 V and a VRM for +12 V to be used only for a 'Pentium' (trademark) processor. SOLUTION: This VRM mispackaging prevention circuit 10 is provided with a sort ID output circuit 5 for outputting a signal expressing the sort of a VRM to be packaged, a VRM sort recognizing circuit 2 for recognizing the mispackaging of a VRM and means (2/6) for stopping the operation of a VRM when the VRM is mis-packaged and constituted so as to stop the operation of the VRM when the VRM is mispackaged. Since the circuit 10 is realized by using two input ports (a VID 4-0 port and an output enable signal input port) conventionally allocated to the VRM, it is unnecessary to change the arrangement of pins and the shape of a connector.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage regulation module for adjusting a reference voltage supplied to a central processing unit of a digital information processing device.
More specifically, the present invention relates to a circuit for preventing erroneous mounting of a VRM. The invention is particularly applicable to Intel's "Pent
VR used in the "ium"(trademark; the same applies hereinafter) processor
M relates to an erroneous mounting prevention circuit.

[0002]

2. Description of the Related Art In a digital information processing apparatus using an Intel "Pentium" processor, a reference voltage supplied to a central processing unit (CPU) is adjusted by a unique voltage adjustment module (VRM). In the VRM unique to “Pentium”, a 5-bit required voltage data signal “VID4-
0 ”sets the output voltage of the VRM.
The VRM for the "entium" processor is, as shown in FIG. 3, a request voltage data signal "VID" output from the CPU.
A “VID4-0” input port for inputting “4-0” and an output enable signal (OUTPUT EN) input port for inputting an output enable signal (OUTPUT EN) pulled up by a pull-up resistor.

The VRM recognizes the state of "VID4-0" by a voltage setting control circuit and sets a voltage value of a power supply output circuit. The power supply output is an output enable signal (OUTPU
ON / OFF control is performed by TEN. In FIG. 3, the output enable signal is pulled up, and VRM is always in an output state. Power supply output circuit is + 5V or +
Regulates 12V and outputs power.

[0004] VRMs compatible with the "Pentium" processor include those that use a +5 V power source for regulation and a +12 V power source for regulation. +5
Most of the power consumed by the VRM using the V power source as the source power is from the +5 V power source. At this time, + 12V is VR
Only operating the MOSFET inside M consumes little power compared to + 5V. On the other hand, most of the power consumed by the VRM using + 12V as the source power is + 12V.
V power supply. At this time, + 5V only operates the VRM internal IC, and power is hardly consumed compared to + 12V. Note that VRM using +5 V as a source power supply and +1
VRM “VID4-0” input port with 2V source power and output enable signal (OUTPUT E
N) The pin arrangement and connector shape of the input ports are the same.

[0005]

The conventional VRM corresponding to the "Pentium" processor has a VR corresponding to + 5V.
There are M and + 12V compatible VRMs, and there is a possibility of erroneous mounting. Because the VRM for + 5V and the VR for + 12V
This is because the pin arrangement and connector shape of the “VID4-0” input port and the output enable signal input port are the same for M and M. If the + 12V compatible VRM is erroneously mounted where the + 5V compatible VRM should be mounted, or vice versa, the following problems occur.

That is, in a device which is expected to mount a VRM compatible with +5 V, the +5 V power supply capacity is increased, but since the +12 V power supply is hardly consumed by the VRM, the +12 V power supply capacity is reduced. Also, + 5V
Is wide enough to allow the current consumed by the VRM to flow, but the +12 V pattern is not large enough to withstand large currents. Therefore, if a + 12V compatible VRM is mounted on a device that expects a + 5V compatible VRM, the device may go down due to exceeding the + 12V power supply capacity, or an unexpectedly large current flows in the + 12V pattern, causing heat generation and burning. There is fear.

Conversely, in a device which is expected to mount a VRM compatible with +12 V, the +12 V power supply capacity is increased, but the +5 V power supply capacity is reduced since VRM is hardly consumed. Further, the pattern width of +12 V is ensured to be large enough to allow the current consumed by VRM to flow, but the pattern of +5 V is not ensured to be large enough to withstand a large current. Therefore, this +1
If a + 5V compatible VRM is mounted on a device that expects a 2V compatible VRM, the device may go down due to exceeding the + 5V power supply capacity, or an unexpectedly large current may flow through the + 5V pattern, causing heat generation and burning.

The prior art method for preventing erroneous mounting of electronic components on a substrate is disclosed in, for example, Japanese Patent Application Laid-Open No. Hei 8-21310.
As described in No. 5, erroneous mounting is prevented by changing the pin arrangement of the interface between the electronic component and the board connector or by changing the pin shape. It is difficult to apply the prior art erroneous mounting prevention method to VRM. Because VRM "VID4
This is because the pin arrangement and the connector shape of the -0 "input port and the output enable signal input port must be changed.

An object of the present invention is to provide a VRM "VID4-
+5 without changing the pin arrangement and connector shape of the 0 "input port and the output enable signal input port.
An object of the present invention is to provide an erroneous mounting prevention circuit capable of preventing erroneous mounting of a VRM compatible with V and a VRM compatible with + 12V.

[0010]

SUMMARY OF THE INVENTION The present invention relates to "Penti
The "VID4-0" input port and the output enable signal input port conventionally assigned to the "UM" processor VRM realize the mis-mounting prevention circuit. Means for outputting a signal indicating the type of the mounted VRM; means for recognizing erroneous mounting of the VRM based on the signal; and means for stopping the operation of the VRM at the time of erroneous mounting. Is what you do.

According to the present invention, when a VRM of a type other than the expected VRM is mounted (for example, when a VRM compatible with +5 V is mounted on an apparatus expecting a VRM compatible with +12 V), the recognizing unit determines the VRM type. The erroneous mounting is recognized based on the signal of the output means, and the operation of the VRM is stopped. At this time, the power supply output circuit of the VRM does not output power. Therefore, erroneous mounting of the VRM is prevented.

In a preferred embodiment, the recognizing means outputs information when a VRM without a VRM erroneous mounting prevention function is mounted. By displaying this information on a monitor, etc., it is possible to warn about erroneous implementation of VRM,
Confirmation of the type of VRM can be prompted.

In another aspect, a VRM mis-mounting prevention circuit according to the present invention includes means for setting a type of a VRM mounted on an apparatus, and means for recognizing a VRM mis-mount based on a signal from the setting means. And means for stopping the operation of the VRM at the time of erroneous mounting.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG.
To explain the embodiment, the CPU 1 of the information processing apparatus is "Pe
A reference voltage to be applied to the CPU 1 is adjusted by a voltage adjustment module (VRM) 4 mounted on the information processing apparatus. The information processing apparatus incorporates a VRM erroneous mounting prevention circuit 10. The VRM erroneous mounting prevention circuit 10 includes a VRM type recognition circuit 2, an ID output circuit 3, and a type ID in the VRM 4.
An output circuit 5 and a voltage setting control circuit 6 are provided.

The ID output circuit 3 is connected to "VID4-
0 "output port, the VRM receives a 5-bit required voltage data signal representing a reference voltage to be applied to the CPU 1 from the CPU 1. The ID output circuit 3 functions as a buffer, and the VRM type recognition circuit 2 When the output enable signal (OUTPUT EN) from the CPU 1 is at a high level, the requested voltage data signal (VID4-
0) is output. The ID output circuit 3 becomes high impedance when the output enable signal (OUTPUT EN) is at a low level.

In the VRM type recognition circuit 2, whether the information processing apparatus expects a VRM corresponding to +5 V or a VRM corresponding to +12 V
Is set in advance. The VRM type recognition circuit 2 is connected to the ID output circuit 3, type ID output circuit 5, and voltage setting control circuit 6, and outputs an output enable signal (OUTPUT EN) to them. The type ID output circuit 5 is for notifying the VRM type recognition circuit 2 of information as to whether this VRM 4 is a +5 V compatible VRM or a +12 V compatible VRM.
The output circuit 5 has information (VRM type I) indicating whether the VRM 4 is a +5 V compatible VRM or a +12 V compatible VRM.
D) is set in advance. The type ID output circuit 5 outputs the VRM type ID indicating the type of VRM to the VRM type recognition circuit 2 via the signal line 8 when the output enable signal (OUTPUT EN) is at a low level. Type ID output circuit 5
Becomes high impedance when the output enable signal (OUTPUT EN) is at a high level.

The voltage setting control circuit 6 recognizes the state of the required voltage data signal (VID4-0) when the output enable signal (OUTPUT EN) is at a high level, and controls the power supply output circuit 7. When the output enable signal is at a low level, the power output of the power output circuit 7 is turned off. The power supply output circuit 7 is controlled by the voltage setting control circuit 6 and outputs power. The VRM type recognition circuit 2 recognizes the signal on the signal line 8 when outputting the output enable signal (OUTPUT EN) at a low level, and notifies the device of VRM information.

Next, the operation of the VRM erroneous mounting prevention circuit 10 shown in FIG. 1 will be described. When power is turned on, the VRM type recognition circuit 2 outputs a low-level output enable signal (OUTPU
TEN) is output. The CPU 1 outputs a 5-bit required voltage data signal (VID4-0).
An output enable signal (OUTP) from the M type recognition circuit 2
UT EN) is at a low level, the ID output circuit 3 is in a high impedance state, and the ID output circuit 3
Is the required voltage data signal (VID4-0) from CPU1
Is not output to the power supply setting control circuit 6.

Since the output enable signal (OUTPUT EN) from the VRM type recognition circuit 2 is at a low level,
The type ID output circuit 5 of the VRM 4 has a VRM type of +5.
A 5-bit VRM type ID for identifying whether the VRM is a VRM or a + 12V VRM is output. The type ID output circuit 5 is, for example, a VRM corresponding to + 5V.
In the case of, the VRM type ID “00001” is output, and +
In the case of a 12 V compatible VRM, the VRM type ID “0001”
The VRM type ID is sent to the VRM type recognition circuit 2 via the signal line 8.

The VRM type recognition circuit 2 monitors the state of the signal line 8 while outputting the low level output enable signal (OUTPUT EN), and recognizes the type of the VRM 4. As described above, in the VRM type recognition circuit 2, whether the information processing apparatus expects the VRM corresponding to + 5V or + 12V
Information on whether a corresponding VRM is expected is recorded. V
The RM type recognition circuit 2 is configured such that the information processing device is a + 5V compatible VR.
If M is expected, if VRM type ID is +
If it is “00001” meaning a VRM corresponding to 5 V, the output enable signal (OUTPUT EN) is set to a high level to enable the VRM 4.

More specifically, the VRM type recognition circuit 2
+ 5V compatible VRM that the mounted VRM4 expects of the device
Is confirmed, the output enable signal (OUT
PUT EN) to a high level output. The type ID output circuit 5 stops outputting because the output enable signal (OUTPUT EN) has become high level, and becomes high impedance. When the output enable signal (OUTPUT EN) of the VRM type recognition circuit 2 becomes high level,
The ID output circuit 3 outputs the required voltage data signal (VID4-0) from the CPU 1 to the power supply setting control circuit 6. In response, the power supply setting control circuit 6 sets the required voltage data (VID4-0) and outputs the output enable signal (OUT
(PUT EN) is checked, the voltage of the power supply output circuit 7 is set, and power supply output with the required voltage is started.

On the contrary, when the information processing apparatus expects a VRM corresponding to +5 V, the VRM type ID recorded in the type ID output circuit 5 is changed to the VRM corresponding to +12 V.
Is "00010", the VRM type recognition circuit 2 outputs the output enable signal (OUTPUT).
EN) remains low and VRM4 is not enabled. In this way, when the +12 V-compatible VRM is erroneously mounted on a device expected to mount the +5 V-compatible VRM, the power supply output circuit 7 does not output power.

It should be noted that a V having the function of preventing erroneous mounting according to the present invention.
When the conventional VRM without the erroneous mounting prevention function shown in FIG. 3 is mounted on the device instead of the RM 4, the signal output to the VRM type recognition circuit 2 is “11111” by the action of the pull-up resistor 9. Becomes As a result, the VRM type recognition circuit 2 recognizes that there is no output from the VRM, that is, the state in which the conventional VRM is mounted. In this case, the VRM type recognizing circuit 2 outputs VRM information to the device, and outputs a message for confirming incorrect mounting to a monitor or the like, thereby alerting the user of the incorrect mounting of the VRM,
It is possible to prompt confirmation of M types.

Next, the VRM of the present invention will be described with reference to FIG.
A second embodiment of the erroneous mounting prevention circuit will be described. The VRM erroneous mounting prevention circuit 20 includes an ID switching circuit 21, a VRM type setting circuit 22, a type recognition circuit 23, and a voltage setting circuit 6.
Having. In the VRM type setting circuit 22, whether the information processing apparatus expects a VRM corresponding to + 5V or a VRM corresponding to + 12V
Is expected in advance. When the power is turned on, the VRM type setting circuit 22 outputs the output enable signal (O
UTPUT EN) is driven low, and at the same time, the VRM identification ID is output. Requested voltage data (VID4-0) is also output from CPU1.

The ID switching circuit 21 outputs the required voltage data (VI) from the CPU 1 in accordance with the state of the output enable signal.
D4-0) and the signal from the VRM type setting circuit 22 are switched. When the output enable signal is low, I
The D switching circuit 21 outputs a signal from the VRM type setting circuit 8 to a signal line 25. The VRM type setting circuit 22 determines whether the device expects a VRM corresponding to +5 V,
Whether the RM is expected is output to the ID switching circuit 21. When the output enable signal is at a high level, the ID switching circuit 21 outputs the requested voltage data (VID4
−0) is output. For example, when the VRM 24 is a VRM corresponding to +5 V, the VRM type setting circuit 22
Outputs type ID "00001" and supports + 12V VRM
In this case, the VRM type ID “00010” is output.

The type recognition circuit 23 of the VRM 24 has a VRM
24 is + 5V compatible VRM or + 12V compatible VRM
(VRM type ID) is set in advance. The type recognition circuit 23 outputs an output enable signal (OUTP
UT EN) is at a low level during the VRM type setting circuit 8
, And checks whether or not it (VRM 24) is a VRM adapted to the device. The device is +5
If a VRM corresponding to V is expected and the VRM 24 itself is also a VRM corresponding to +5 V, the VRM type setting circuit 22 outputs the VRM type ID “00001” to the signal line 25, and the type recognizing circuit 23 outputs the VRM type ID. Since the types match, the power supply output circuit is enabled. If they do not match, the power supply output circuit 7 is not enabled.

The VRM type setting circuit 22 outputs the output enable signal (OUTPUTEN) at a low level for an appropriate period and then sets it at a high level. When the output enable signal goes high, the output from the ID switching circuit 21 is
And the required voltage data (VID4-0) is output. The voltage setting control circuit 6 outputs the required voltage data (VI
D4-0) is confirmed, and the power supply output circuit 7 is set. If the VRM types do not match, the power supply output circuit 7 is not enabled even after the voltage setting circuit 6 completes the setting.

[0028]

According to the present invention, since the VRM is enabled after recognizing the type of the VRM and confirming that the expected VRM is mounted, even if the VRM is erroneously mounted, the power supply capacity can be reduced. This can prevent accidents such as equipment down due to overheating, heat generation or burnout of patterns and components. Another advantage of the present invention is that the erroneous mounting prevention circuit is realized by using the “VID4-0” input port and the output enable signal input port conventionally assigned to the VRM, so that the pin arrangement and the connector shape are not changed. That is, erroneous mounting can be prevented. Also, VRM “VID4
Since the pin arrangement and connector of the -0 "input port and the output enable signal input port are the same as those of the conventional VRM, members can be shared with the conventional VRM, and the conventional VRM can be mounted. In addition, conventional V
Since it is also possible to recognize that the RM is RM, it is possible to alert a monitor or the like whether there is any erroneous mounting.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of a VRM erroneous mounting prevention circuit according to the present invention.

FIG. 2 is a block diagram of a second embodiment of a VRM erroneous mounting prevention circuit of the present invention.

FIG. 3 is a block diagram of a conventional VRM.

[Explanation of symbols]

 2: VRM type recognition circuit (erroneous mounting recognition means) 2/6, 7/23: VRM operation stop means 3: ID output circuit 4, 24: VRM 5: Type ID output circuit (VRM type signal output means) 6: Voltage Setting control circuit 7: Power supply output circuit 10, 20: VRM erroneous mounting prevention circuit 22: VRM type setting means 23: erroneous mounting recognition means

Claims (3)

[Claims] 1. A means for outputting a signal indicating a type of a VRM mounted on an apparatus, a means for recognizing erroneous mounting of a VRM based on the signal, and a means for stopping the operation of the VRM at the time of erroneous mounting. A VRM erroneous mounting prevention circuit, comprising: 2. The VRM erroneous mounting prevention circuit according to claim 1, wherein said recognizing means outputs information when a VRM without a VRM erroneous mounting prevention function is mounted. Means for setting the type of VRM mounted on the device, means for recognizing erroneous mounting of the VRM based on a signal from the setting means, means for stopping operation of the VRM at the time of erroneous mounting. VRM characterized by comprising:
Incorrect mounting prevention circuit.