JP2000056847A - Constant current driving circuit - Google Patents
Constant current driving circuitInfo
- Publication number
- JP2000056847A JP2000056847A JP10229650A JP22965098A JP2000056847A JP 2000056847 A JP2000056847 A JP 2000056847A JP 10229650 A JP10229650 A JP 10229650A JP 22965098 A JP22965098 A JP 22965098A JP 2000056847 A JP2000056847 A JP 2000056847A
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- Prior art keywords
- transistor
- gate
- constant current
- switching
- drain
- Prior art date
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はアクティブマトリク
ス方式の有機エレクトロルミネセント素子等に好適な定
電流駆動回路に関し、特に、内蔵されるカレントミラー
回路の整合性の向上を図った定電流駆動回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant current driving circuit suitable for an active matrix type organic electroluminescent device and the like, and more particularly to a constant current driving circuit for improving the matching of a built-in current mirror circuit. .
【０００２】[0002]
【従来の技術】従来、アクティブマトリックス方式の有
機エレクトロルミネセント（ＥＬ）素子等に定電流駆動
回路が使用されている。図７は従来の定電流駆動回路を
示す回路図である。2. Description of the Related Art Conventionally, a constant current drive circuit has been used for an active matrix type organic electroluminescent (EL) element or the like. FIG. 7 is a circuit diagram showing a conventional constant current drive circuit.
【０００３】従来の定電流駆動回路においては、入力端
子１０１に抵抗１０３が接続されている。また、抵抗１
０３にドレイン及びゲートが接続されたトランジスタ１
０４が設けられている。トランジスタ１０４のソースに
は、スイッチ用トランジスタ１０６のドレインが接続さ
れている。そして、スイッチ用トランジスタ１０６のゲ
ートには、スイッチ用トランジスタ１０６の導通／遮断
の制御を行うためのアドレス信号が入力される制御端子
１０２が接続され、スイッチ用トランジスタ１０６のソ
ースには、接地端子１１１が接続されている。In a conventional constant current drive circuit, a resistor 103 is connected to an input terminal 101. The resistance 1
Transistor 1 whose drain and gate are connected to 03
04 is provided. The drain of the switching transistor 106 is connected to the source of the transistor 104. The gate of the switching transistor 106 is connected to a control terminal 102 to which an address signal for controlling ON / OFF of the switching transistor 106 is input. The source of the switching transistor 106 is connected to a ground terminal 111. Is connected.
【０００４】また、トランジスタ１０４のドレイン及び
ゲートには、電荷保持容量素子１０７の一方の電極が接
続されている。電荷保持容量素子１０７の他方の電極
は、接地端子１１１に接続されている。更に、トランジ
スタ１０４のドレイン及びゲートにゲートが接続された
トランジスタ１０５が設けられている。トランジスタ１
０５のソースは接地端子１１１に接続されている。ま
た、トランジスタ１０５のドレインには、負荷１０８が
接続されている。負荷１０８は、例えば定電流駆動を要
する有機ＥＬ素子である。そして、負荷１０８には、電
源端子１１０が接続されている。このようにして構成さ
れた従来の定電流駆動回路には、トランジスタ１０４及
び１０５からなるカレントミラー回路が含まれている。[0004] One electrode of a charge storage capacitor 107 is connected to the drain and gate of the transistor 104. The other electrode of the charge storage capacitor 107 is connected to the ground terminal 111. Further, a transistor 105 whose gate is connected to the drain and the gate of the transistor 104 is provided. Transistor 1
The source of 05 is connected to the ground terminal 111. The load 108 is connected to the drain of the transistor 105. The load 108 is, for example, an organic EL element requiring constant current driving. The power supply terminal 110 is connected to the load 108. The conventional constant current drive circuit configured as described above includes a current mirror circuit including transistors 104 and 105.
【０００５】そして、入力端子１０１に入力された信号
の電圧に応じて抵抗１０３に電流が流れる。このとき、
スイッチ用トランジスタ１０６が導通状態であれば、ト
ランジスタ１０５に抵抗１０３に流れる電流に比例した
電流がドレイン電流として流れ、負荷１０８にも電流が
流れる。一方、スイッチ用トランジスタ１０６が遮断状
態であれば、トランジスタ１０５にはドレイン電流が流
れないので、負荷１０８にも電流は流れない。このよう
にして、負荷１０８に流れる定電流の導通／遮断が制御
される。Then, a current flows through the resistor 103 in accordance with the voltage of the signal input to the input terminal 101. At this time,
When the switching transistor 106 is on, a current proportional to the current flowing through the resistor 103 flows through the transistor 105 as a drain current, and the current also flows through the load 108. On the other hand, when the switching transistor 106 is in the cutoff state, no drain current flows through the transistor 105, and thus no current flows through the load 108. In this way, the conduction / interruption of the constant current flowing through the load 108 is controlled.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上述の
従来の定電流駆動回路においては、スイッチ用トランジ
スタ１０６のオン抵抗及びソース電流による電圧降下の
ためにカレントミラー回路の整合性が悪化し、負荷１０
８に入力端子１０１の信号レベルに応じた定電流が供給
されないという問題点がある。However, in the above-described conventional constant current drive circuit, the matching of the current mirror circuit deteriorates due to the voltage drop due to the on-resistance and the source current of the switching transistor 106, and the load 10
8 has a problem that a constant current corresponding to the signal level of the input terminal 101 is not supplied.
【０００７】また、これを防止するためにスイッチ用ト
ランジスタ１０６のサイズを大きくしてそのオン抵抗を
小さくすることが考えられるが、これを半導体集積回路
で構成しようとする場合、チップサイズが増大するた
め、コストの上昇につながる。また、例えば有機ＥＬ素
子の駆動回路として薄膜トランジスタ（ＴＦＴ）を使用
する場合、スイッチ用トランジスタに大きなサイズが必
要となるため、画素の占有率が減って開口率が低下して
輝度が低下してしまう。この場合には、輝度を通常使用
レベルまで上昇させるために定電流値を上げる等の対策
が必要となり、近時の省電力化に逆行するものとなる。In order to prevent this, it is conceivable to increase the size of the switching transistor 106 to reduce its on-resistance. However, when this is to be implemented by a semiconductor integrated circuit, the chip size increases. This leads to an increase in cost. In addition, for example, when a thin film transistor (TFT) is used as a driving circuit of an organic EL element, a large size is required for a switching transistor, so that the pixel occupancy is reduced, the aperture ratio is reduced, and the luminance is reduced. . In this case, it is necessary to take measures such as increasing the constant current value in order to raise the luminance to the normal use level, which is against the recent power saving.
【０００８】本発明はかかる問題点に鑑みてなされたも
のであって、コストを上昇させることなく入力された信
号に応じた定電流を供給することができる定電流駆動回
路を提供することを目的とする。The present invention has been made in view of the above problems, and has as its object to provide a constant current driving circuit capable of supplying a constant current corresponding to an input signal without increasing cost. And
【０００９】[0009]
【課題を解決するための手段】本発明に係る定電流駆動
回路は、入力端子と、この入力端子にドレインが接続さ
れ接地にソースが接続された第１のトランジスタと、こ
の第１のトランジスタのゲート及びドレインに接続され
たスイッチ用トランジスタと、このスイッチ用トランジ
スタのゲートに接続されこのスイッチ用トランジスタの
導通と非導通とを切替える信号が入力される制御端子
と、前記スイッチ用トランジスタにゲートが接続され接
地にソースが接続され前記第１のトランジスタと共にカ
レントミラー回路を構成する第２のトランジスタと、こ
の第２のトランジスタのゲートに一方の電極が接続され
接地に他方の電極が接続された容量素子と、を有するこ
とを特徴とする。A constant current drive circuit according to the present invention comprises an input terminal, a first transistor having a drain connected to the input terminal and a source connected to the ground, A switching transistor connected to the gate and the drain, a control terminal connected to the gate of the switching transistor, to which a signal for switching between conduction and non-conduction of the switching transistor is input, and a gate connected to the switching transistor A second transistor having a source connected to ground and forming a current mirror circuit together with the first transistor, and a capacitive element having one electrode connected to the gate of the second transistor and the other electrode connected to ground. And the following.
【００１０】なお、前記第１及び第２のトランジスタの
チャネルの導電型は、前記スイッチ用トランジスタのチ
ャネルの導電型と相違し、前記第１のトランジスタのソ
ースと接地との間に接続された第１のレベルシフト用ダ
イオードと、前記第２のトランジスタのソースと接地と
の間に接続された第２のレベルシフト用ダイオードと、
を有してもよい。The conductivity type of the channel of the first and second transistors is different from the conductivity type of the channel of the switching transistor, and the conductivity type of the channel connected between the source of the first transistor and ground is different. A first level shifting diode, a second level shifting diode connected between the source of the second transistor and ground,
May be provided.
【００１１】また、前記第１及び第２のトランジスタの
チャネルの導電型は、前記スイッチ用トランジスタのチ
ャネルの導電型と同じであってもよい。[0011] The conductivity type of the channel of the first and second transistors may be the same as the conductivity type of the channel of the switching transistor.
【００１２】本発明に係る他の定電流駆動回路は、入力
端子と、この入力端子にドレインが接続され接地にソー
スが接続された第１のトランジスタと、この第１のトラ
ンジスタのゲートとドレインとの間に接続されたスイッ
チ用トランジスタと、このスイッチ用トランジスタのゲ
ートに接続されこのスイッチ用トランジスタの導通と非
導通とを切替える信号が入力される制御端子と、前記第
１のトランジスタのゲートにゲートが接続され接地にソ
ースが接続され前記第１のトランジスタと共にカレント
ミラー回路を構成する第２のトランジスタと、この第２
のトランジスタのゲートに一方の電極が接続され接地に
他方の電極が接続された容量素子と、を有することを特
徴とする。Another constant current driving circuit according to the present invention comprises an input terminal, a first transistor having a drain connected to the input terminal and a source connected to ground, a gate and a drain of the first transistor. A control terminal connected to the gate of the switching transistor, to which a signal for switching between conduction and non-conduction of the switching transistor is input; and a gate connected to the gate of the first transistor. And a second transistor having a source connected to the ground and forming a current mirror circuit together with the first transistor;
And a capacitor in which one electrode is connected to the gate of the transistor and the other electrode is connected to the ground.
【００１３】なお、前記入力端子と前記第１のトランジ
スタのドレインとの間に接続された抵抗を有することが
できる。[0013] A resistor may be connected between the input terminal and the drain of the first transistor.
【００１４】また、前記入力端子と前記抵抗との間に接
続されたソースフォロワ用トランジスタを有することが
できる。[0014] The semiconductor device may further include a source follower transistor connected between the input terminal and the resistor.
【００１５】更に、前記第２のトランジスタのドレイン
は有機エレクトロルミネセント素子に接続されることが
できる。Further, the drain of the second transistor can be connected to an organic electroluminescent device.
【００１６】本発明においては、スイッチ用トランジス
タが非導通にされても、第２のトランジスタのゲートと
接地との間に設けられた容量素子に蓄積された電荷によ
って、定電流を供給し続けることができる。また、スイ
ッチ用トランジスタのオン抵抗による電圧降下は無視で
きるほど小さい。このため、カレントミラー回路の整合
性が著しく改善される。According to the present invention, even when the switching transistor is turned off, the constant current is continuously supplied by the electric charge accumulated in the capacitor provided between the gate of the second transistor and the ground. Can be. The voltage drop due to the on-resistance of the switching transistor is so small as to be negligible. Therefore, the matching of the current mirror circuit is significantly improved.
【００１７】[0017]
【発明の実施の形態】以下、本発明の実施例に係る定電
流駆動回路について、添付の図面を参照して具体的に説
明する。図１は本発明の第１の実施例に係る定電流駆動
回路を示す回路図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a constant current drive circuit according to an embodiment of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing a constant current drive circuit according to a first embodiment of the present invention.
【００１８】本実施例の定電流駆動回路においては、入
力端子１に抵抗３が接続されている。また、抵抗３にド
レイン及びゲートが接続されたＮチャネルＭＯＳトラン
ジスタ４が設けられている。トランジスタ４のソースに
は、接地端子１１が接続されている。また、トランジス
タ４のドレイン及びゲートに一端が接続されＰチャネル
ＭＯＳトランジスタであるスイッチ用トランジスタ６が
設けられている。そして、スイッチ用トランジスタ６の
ゲートには、スイッチ用トランジスタ６の導通／遮断
（非導通）の制御を行うためのアドレス信号が入力され
る制御端子２が接続されている。In the constant current drive circuit of the present embodiment, a resistor 3 is connected to the input terminal 1. Further, an N-channel MOS transistor 4 having a drain and a gate connected to the resistor 3 is provided. The ground terminal 11 is connected to the source of the transistor 4. Further, a switching transistor 6 which is a P-channel MOS transistor having one end connected to the drain and the gate of the transistor 4 is provided. The control terminal 2 to which an address signal for controlling conduction / interruption (non-conduction) of the switching transistor 6 is input is connected to the gate of the switching transistor 6.
【００１９】また、スイッチ用トランジスタ６の他端に
は、電荷保持手段として電荷保持容量素子７の一方の電
極が接続されている。電荷保持容量素子７の他方の電極
は、接地端子１１に接続されている。更に、スイッチ用
トランジスタ６の前記他端にゲートが接続されたＮチャ
ネルＭＯＳトランジスタ５が設けられている。トランジ
スタ５のソースは接地端子１１に接続されている。ま
た、トランジスタ５のドレインには、負荷８が接続され
ている。負荷８は、例えば定電流駆動を要するアクティ
ブマトリクス方式の有機エレクトロルミネセント（Ｅ
Ｌ：Electro-Luminescent）素子である。そして、負荷
８には、電源端子１０が接続されている。このようにし
て構成された本実施例の定電流駆動回路には、トランジ
スタ４及び５からなるカレントミラー回路が含まれてい
る。The other end of the switching transistor 6 is connected to one electrode of a charge holding capacitance element 7 as charge holding means. The other electrode of the charge storage capacitor 7 is connected to the ground terminal 11. Further, an N-channel MOS transistor 5 having a gate connected to the other end of the switching transistor 6 is provided. The source of the transistor 5 is connected to the ground terminal 11. A load 8 is connected to the drain of the transistor 5. The load 8 is, for example, an active matrix type organic electroluminescent (E) that requires constant current driving.
L: Electro-Luminescent element. The power supply terminal 10 is connected to the load 8. The constant current drive circuit according to the present embodiment thus configured includes a current mirror circuit including the transistors 4 and 5.
【００２０】次に、上述のように構成された本実施例の
定電流駆動回路の動作について説明する。Next, the operation of the constant current driving circuit of the present embodiment configured as described above will be described.
【００２１】入力端子１に画像信号等の入力信号が入力
されると、この信号の電圧に応じて抵抗３に電流が流れ
る。そして、抵抗３に流れる電流は、ドレイン及びソー
スが相互に接続されたトランジスタ４に流れ、トランジ
スタ４にゲート−ソース間電圧が発生する。When an input signal such as an image signal is input to the input terminal 1, a current flows through the resistor 3 according to the voltage of the signal. Then, the current flowing through the resistor 3 flows through the transistor 4 whose drain and source are connected to each other, and a gate-source voltage is generated in the transistor 4.
【００２２】そして、制御端子２に入力されたアドレス
信号がロウレベルでスイッチ用トランジスタ６が導通状
態の場合には、トランジスタ４に発生したゲート−ソー
ス間電圧は、スイッチ用トランジスタ６を介して電荷保
持容量素子７及びトランジスタ５のゲートに印加され
る。このとき、トランジスタ４及び５はカレントミラー
回路を構成しているため、抵抗３に流れる電流に比例し
た電流がトランジスタ５のドレイン電流として流れる。
即ち、トランジスタ４とトランジスタ５とのパターンサ
イズの比によって決定される電流、例えばトランジスタ
４及び５が同一パターンサイズで構成されている場合に
は、抵抗３に流れる電流と等しい電流がトランジスタ５
のドレインとソースとの間を流れる。これにより、負荷
８が駆動される。When the address signal input to the control terminal 2 is at a low level and the switching transistor 6 is conductive, the gate-source voltage generated in the transistor 4 is charged through the switching transistor 6. The voltage is applied to the capacitor 7 and the gate of the transistor 5. At this time, since the transistors 4 and 5 form a current mirror circuit, a current proportional to the current flowing through the resistor 3 flows as the drain current of the transistor 5.
In other words, a current determined by the pattern size ratio between the transistor 4 and the transistor 5, for example, when the transistors 4 and 5 are configured with the same pattern size, a current equal to the current flowing through the resistor 3 is equal to the transistor 5
Flows between the drain and the source of the device. As a result, the load 8 is driven.
【００２３】次に、制御端子２に入力されたアドレス信
号がハイレベルでスイッチ用トランジスタ６が遮断状態
となると、トランジスタ４及び５からなるカレントミラ
ー回路も遮断される。しかし、スイッチ用トランジスタ
６が導通状態の時に、入力端子１の信号電圧に応じた電
流がトランジスタ４に流れ、その電流に応じたトランジ
スタ４のゲート−ソース間電圧が電荷保持容量素子７に
印加されている。このため、スイッチ用トランジスタ６
が遮断された後にも、この電圧がトランジスタ５のゲー
トに印加されるので、このゲート電圧に応じた電流が負
荷８に供給される。即ち、スイッチ用トランジスタ６が
遮断状態でも、負荷８には入力端子１の信号電圧に応じ
た電流が供給され続ける。Next, when the address signal input to the control terminal 2 is at a high level and the switching transistor 6 is turned off, the current mirror circuit composed of the transistors 4 and 5 is also turned off. However, when the switching transistor 6 is conducting, a current corresponding to the signal voltage of the input terminal 1 flows through the transistor 4, and a gate-source voltage of the transistor 4 corresponding to the current is applied to the charge holding capacitor 7. ing. Therefore, the switching transistor 6
Since the voltage is applied to the gate of the transistor 5 even after the current is cut off, a current corresponding to the gate voltage is supplied to the load 8. That is, even when the switching transistor 6 is turned off, a current corresponding to the signal voltage of the input terminal 1 is continuously supplied to the load 8.
【００２４】従って、本実施例をアクティブマトリクス
方式の有機ＥＬ素子の駆動回路に適用した場合、入力端
子１には入力画像信号が入力され、その階調データによ
って発光輝度が変化する。また、制御端子２にはアドレ
ス信号が入力され、入力端子１からの画像信号に対応す
る画素が電荷保持容量素子７に選択的に読み込まれ、次
の新しい画像信号が入力されるまで電荷が保持され、画
素は発光し続ける。Therefore, when the present embodiment is applied to a drive circuit of an active matrix type organic EL element, an input image signal is input to the input terminal 1 and the emission luminance changes according to the gradation data. Further, an address signal is input to the control terminal 2, a pixel corresponding to the image signal from the input terminal 1 is selectively read into the charge holding capacitor 7, and the charge is held until the next new image signal is input. The pixel continues to emit light.
【００２５】このように、本実施例によれば、スイッチ
用トランジスタ６のオン抵抗による電圧降下を無視でき
るため、カレントミラー回路の整合性が改善される。As described above, according to the present embodiment, the voltage drop due to the on-resistance of the switching transistor 6 can be ignored, so that the matching of the current mirror circuit is improved.
【００２６】また、従来技術のように大電流経路にスイ
ッチ素子を設ける場合には、オン抵抗を低減するために
素子サイズを大きくする必要があったが、本実施例にお
いてスイッチ用トランジスタ６を流れる電流は無視でき
るほど小さいので、最小寸法のトランジスタにて構成す
ることができる。従って、半導体集積回路に適用する場
合にも、安価なものとなる。When a switching element is provided in a large current path as in the prior art, it is necessary to increase the element size in order to reduce the on-resistance. However, in this embodiment, the element flows through the switching transistor 6. Since the current is so small as to be negligible, it can be constituted by a transistor having a minimum size. Therefore, even when it is applied to a semiconductor integrated circuit, it is inexpensive.
【００２７】更に、有機ＥＬの駆動回路として薄膜トラ
ンジスタ（ＴＦＴ）を使用する場合にも、大きなスイッ
チ用トランジスタは不要であるため、画素の開口率の向
上をさせ有機ＥＬの輝度を向上させることが可能であ
る。また、薄膜トランジスタによりカレントミラー回路
を構成するトランジスタ４及び５を作製する場合、トラ
ンジスタ４及び５を相互に隣接して配置することができ
るため、製造に起因するトランジスタのパラメータのバ
ラツキを低く抑制することができる。従って、トランジ
スタ４及び５からなるカレントミラー回路の整合性が向
上する。Further, even when a thin film transistor (TFT) is used as a driving circuit of the organic EL, a large switching transistor is not required, so that it is possible to improve the aperture ratio of the pixel and the luminance of the organic EL. It is. In the case where the transistors 4 and 5 forming a current mirror circuit are formed using thin film transistors, the transistors 4 and 5 can be arranged adjacent to each other, so that variations in transistor parameters due to manufacturing are suppressed to a low level. Can be. Therefore, the matching of the current mirror circuit including the transistors 4 and 5 is improved.
【００２８】次に、本発明の第２の実施例について説明
する。本実施例には、レベルシフト用のダイオード構造
を有するトランジスタが配設されている。図２は本発明
の第２の実施例に係る定電流駆動回路を示す回路図であ
る。なお、図２に示す第２の実施例において図１に示す
第１の実施例と同一の構成要素には、同一の符号を付し
てその詳細な説明は省略する。Next, a second embodiment of the present invention will be described. In this embodiment, a transistor having a diode structure for level shifting is provided. FIG. 2 is a circuit diagram showing a constant current drive circuit according to a second embodiment of the present invention. In the second embodiment shown in FIG. 2, the same components as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.
【００２９】本実施例に係る定電流駆動回路には、トラ
ンジスタ４のソースにドレインが接続され接地端子１１
にソースが接続されダイオード構造を有するＮチャネル
ＭＯＳトランジスタ１２が設けられている。また、トラ
ンジスタ５のソースにドレインが接続され接地端子１１
にソースが接続されダイオード構造を有するＮチャネル
ＭＯＳトランジスタ１３が設けられている。In the constant current driving circuit according to the present embodiment, the drain is connected to the source of the transistor 4 and the ground terminal 11
An N-channel MOS transistor 12 having a diode structure with a source connected to the source is provided. Further, the drain is connected to the source of the transistor 5 and the ground terminal 11
Is provided with an N-channel MOS transistor 13 having a diode structure.
【００３０】第１の実施例においては、カレントミラー
回路が２個のＮチャネルＭＯＳトランジスタから構成さ
れ、スイッチ用トランジスタにＰチャネルＭＯＳトラン
ジスタが使用されているが、このような構成のもとでＰ
チャネルＭＯＳトランジスタのオン電圧がＮチャネルＭ
ＯＳトランジスタのオン電圧より大きい場合には、スイ
ッチ用トランジスタ６を導通させるためには、制御端子
２の電圧を接地端子１１の電圧以下にする必要がある。In the first embodiment, the current mirror circuit is composed of two N-channel MOS transistors, and the P-channel MOS transistor is used as the switching transistor.
The ON voltage of the channel MOS transistor is N channel M
When the ON voltage of the OS transistor is higher than that of the OS transistor, the voltage of the control terminal 2 needs to be lower than the voltage of the ground terminal 11 in order to make the switching transistor 6 conductive.
【００３１】第２の実施例においても、制御端子２の電
圧を接地端子１１の電圧以下にする必要があるが、レベ
ルシフト用にトランジスタ１２及び１３が設けられてい
るので、容易に適応することが可能である。In the second embodiment as well, the voltage of the control terminal 2 needs to be lower than the voltage of the ground terminal 11, but since the transistors 12 and 13 are provided for level shifting, it can be easily adapted. Is possible.
【００３２】なお、この場合、カレントミラー回路の整
合性を確保するため、トランジスタ１２及び１３は相互
に同一導伝形式、つまりチャネルの導電型が同じである
必要がある。本実施例においては、ＮチャネルＭＯＳト
ランジスタが使用されているが、ＰチャネルＭＯＳトラ
ンジスタを使用されても同様の効果が得られる。In this case, in order to ensure the matching of the current mirror circuit, the transistors 12 and 13 need to have the same conductivity type, that is, the same channel conductivity type. In the present embodiment, an N-channel MOS transistor is used, but the same effect can be obtained by using a P-channel MOS transistor.
【００３３】また、第１の実施例においても、Ｎチャネ
ルＭＯＳトランジスタとＰチャネルＭＯＳトランジスタ
とのオン電圧が等しければ何ら問題はない。Also in the first embodiment, there is no problem if the ON voltages of the N-channel MOS transistor and the P-channel MOS transistor are equal.
【００３４】次に、本発明の第３の実施例について説明
する。本実施例においては、スイッチ用トランジスタの
導伝形式がカレントミラー回路を構成するトランジスタ
のそれと同一のものとなっている。図３は本発明の第３
の実施例に係る定電流駆動回路を示す模式図である。な
お、図３に示す第３の実施例において図１に示す第１の
実施例と同一の構成要素には、同一の符号を付してその
詳細な説明は省略する。Next, a third embodiment of the present invention will be described. In the present embodiment, the conduction type of the switching transistor is the same as that of the transistor constituting the current mirror circuit. FIG. 3 shows a third embodiment of the present invention.
FIG. 4 is a schematic diagram showing a constant current drive circuit according to the example of FIG. In the third embodiment shown in FIG. 3, the same components as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and a detailed description thereof will be omitted.
【００３５】本実施例に係る定電流駆動回路において
は、トランジスタ４のゲートとトランジスタ５のゲート
との間にＮチャネルＭＯＳトランジスタであるスイッチ
用トランジスタ１６が接続されている。In the constant current driving circuit according to the present embodiment, a switching transistor 16 which is an N-channel MOS transistor is connected between the gate of the transistor 4 and the gate of the transistor 5.
【００３６】このように構成された本実施例において
は、スイッチ用トランジスタ１６とカレントミラー回路
を構成するトランジスタ４及び５とのオン電圧が相違し
ていても、制御端子２の電圧を接地端子１１の電圧以下
にする必要が無くなる。In this embodiment thus constructed, even if the on-voltages of the switching transistor 16 and the transistors 4 and 5 constituting the current mirror circuit are different, the voltage of the control terminal 2 is changed to the ground terminal 11. It is no longer necessary to set the voltage to or below.
【００３７】なお、第１の実施例においては、アドレス
信号がロウレベルのときにカレントミラー回路が動作状
態となるが、第３の実施例においては、アドレス信号が
ハイレベルのときにカレントミラー回路が動作状態とな
る。In the first embodiment, the current mirror circuit is activated when the address signal is at a low level. In the third embodiment, the current mirror circuit is activated when the address signal is at a high level. It is in the operating state.
【００３８】次に、本発明の第４の実施例について説明
する。本実施例においては、スイッチ用トランジスタ
は、カレントミラー回路を構成するトランジスタのゲー
ト間ではなく、入力端子側に接続されたトランジスタの
ゲートとドレインとの間に接続される。図４は本発明の
第４の実施例に係る定電流駆動回路を示す回路図であ
る。なお、図４に示す第４の実施例において図１に示す
第１の実施例と同一の構成要素には、同一の符号を付し
てその詳細な説明は省略する。Next, a fourth embodiment of the present invention will be described. In the present embodiment, the switching transistor is connected not between the gates of the transistors constituting the current mirror circuit but between the gate and the drain of the transistor connected to the input terminal side. FIG. 4 is a circuit diagram showing a constant current driving circuit according to a fourth embodiment of the present invention. In the fourth embodiment shown in FIG. 4, the same components as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.
【００３９】本実施例においては、トランジスタ４のゲ
ートとトランジスタ５のゲートとが直接接続されてい
る。また、ＮチャネルＭＯＳトランジスタであるスイッ
チ用トランジスタ２６がトランジスタ４のゲートとドレ
インとの間に接続されている。In this embodiment, the gate of the transistor 4 and the gate of the transistor 5 are directly connected. A switching transistor 26, which is an N-channel MOS transistor, is connected between the gate and the drain of the transistor 4.
【００４０】このように構成された本実施例において
は、スイッチ用トランジスタ２６は、カレントミラー回
路を構成するトランジスタ４及び５のゲート間ではな
く、トランジスタ４のゲートとドレインとの間に接続さ
れているので、スイッチ用トランジスタ２６のオン抵抗
による電圧降下のためにカレントミラー回路の整合性が
悪化するということは完全に防止される。In this embodiment, the switching transistor 26 is connected not between the gates of the transistors 4 and 5 constituting the current mirror circuit but between the gate and the drain of the transistor 4. Therefore, the deterioration of the matching of the current mirror circuit due to the voltage drop due to the on-resistance of the switching transistor 26 is completely prevented.
【００４１】また、第４の実施例においては、制御端子
２がロウレベルでカレントミラー回路が遮断状態になっ
たとき、スイッチ用トランジスタ２６は遮断される。従
って、入力端子１がハイレベルの状態でもトランジスタ
４は遮断されるため、抵抗３及びトランジスタ４の経路
には電流が流れなくなり、消費電力が低下する。従っ
て、本実施例を例えば有機ＥＬ素子等を使用した画像表
示装置の駆動回路に適用した場合、画像表示装置には複
数個の有機ＥＬ素子が縦横に配列されているので、著し
い省電力化が期待できる。In the fourth embodiment, when the control terminal 2 is at the low level and the current mirror circuit is turned off, the switching transistor 26 is turned off. Therefore, even when the input terminal 1 is at a high level, the transistor 4 is cut off, so that no current flows through the path between the resistor 3 and the transistor 4, and power consumption is reduced. Therefore, when the present embodiment is applied to, for example, a driving circuit of an image display device using an organic EL element or the like, since a plurality of organic EL elements are arranged vertically and horizontally in the image display device, remarkable power saving is achieved. Can be expected.
【００４２】次に、本発明の第５の実施例について説明
する。本実施例においては、入力端子と抵抗との間にソ
ースフォロワ用トランジスタが接続される。図５は本発
明の第５の実施例に係る定電流駆動回路を示す回路図で
ある。なお、図５に示す第５の実施例において図１に示
す第１の実施例と同一の構成要素には、同一の符号を付
してその詳細な説明は省略する。Next, a fifth embodiment of the present invention will be described. In this embodiment, a source follower transistor is connected between the input terminal and the resistor. FIG. 5 is a circuit diagram showing a constant current drive circuit according to a fifth embodiment of the present invention. In the fifth embodiment shown in FIG. 5, the same components as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.
【００４３】本実施例には、入力端子１にゲートが接続
されＮチャネルＭＯＳトランジスタであるソースフォロ
ワ用トランジスタ９が設けられており、その一端は抵抗
３に、その他端は電源端子１０に接続されている。ま
た、トランジスタ４及び５のゲート間には、スイッチ用
トランジスタ３６が接続されている。このスイッチ用ト
ランジスタ３６はＮチャネルＭＯＳトランジスタであっ
てもＰチャネルＭＯＳトランジスタであってもよい。In this embodiment, a source follower transistor 9 which is an N-channel MOS transistor whose gate is connected to the input terminal 1 is provided, one end of which is connected to the resistor 3 and the other end is connected to the power supply terminal 10. ing. A switching transistor 36 is connected between the gates of the transistors 4 and 5. The switching transistor 36 may be an N-channel MOS transistor or a P-channel MOS transistor.
【００４４】このように構成された本実施例において
は、ソースフォロワ用トランジスタ９により、入力端子
１側のインピーダンスが高くてもカレントミラー回路を
構成するトランジスタ４を十分に駆動させることが可能
である。In the present embodiment configured as described above, the transistor 4 constituting the current mirror circuit can be sufficiently driven by the source follower transistor 9 even if the impedance on the input terminal 1 side is high. .
【００４５】また、第１の実施例では、入力端子１がロ
ウレベルでありインピーダンスが低い場合には、電荷保
持容量素子７に蓄積されていた電荷がスイッチ用トラン
ジスタ６が遮断状態のときにスイッチ用トランジスタ６
のオフ抵抗と抵抗３との経路で放電することにより、電
荷保持の機能が十分ではなくなることがあるが、第５の
実施例にはトランジスタ９が設けられているので、電荷
の放電が防止される。In the first embodiment, when the input terminal 1 is at a low level and the impedance is low, the electric charge stored in the charge holding capacitor 7 is used when the switching transistor 6 is in the cut-off state. Transistor 6
In some cases, the function of retaining charges may not be sufficient due to the discharge through the path between the off-resistance and the resistance 3, but the fifth embodiment is provided with the transistor 9, so that the discharge of the charges is prevented. You.
【００４６】次に、本発明の第６の実施例について説明
する。本実施例は、第４の実施例と第５の実施例とを組
み合わせたものである。図６は本発明の第６の実施例に
係る定電流駆動回路を示す回路図である。なお、図６に
示す第６の実施例において図４に示す第４の実施例又は
図５に示す第５の実施例と同一の構成要素には、同一の
符号を付してその詳細な説明は省略する。Next, a sixth embodiment of the present invention will be described. This embodiment is a combination of the fourth embodiment and the fifth embodiment. FIG. 6 is a circuit diagram showing a constant current drive circuit according to a sixth embodiment of the present invention. In the sixth embodiment shown in FIG. 6, the same components as those in the fourth embodiment shown in FIG. 4 or the fifth embodiment shown in FIG. Is omitted.
【００４７】本実施例においては、トランジスタ４のゲ
ートとトランジスタ５のゲートとが直接接続されてい
る。また、ＮチャネルＭＯＳトランジスタであるスイッ
チ用トランジスタ２６がトランジスタ４のゲートとドレ
インとの間に接続されている。更に、本実施例には、入
力端子１にゲートが接続されＮチャネルＭＯＳトランジ
スタであるソースフォロワ用トランジスタ９が設けられ
ており、その一端は抵抗３に、その他端は電源端子１０
に接続されている。In this embodiment, the gate of the transistor 4 and the gate of the transistor 5 are directly connected. A switching transistor 26, which is an N-channel MOS transistor, is connected between the gate and the drain of the transistor 4. Further, in this embodiment, a source follower transistor 9 which is an N-channel MOS transistor having a gate connected to the input terminal 1 is provided, one end of which is connected to the resistor 3 and the other end is connected to the power supply terminal 10.
It is connected to the.
【００４８】このように構成された本実施例において
は、第４及び第５の実施例による双方の効果が得られ
る。即ち、レントミラー回路の整合性が改善される。ま
た、カレントミラー回路を構成するトランジスタ４の駆
動性及び電荷保持容量素子７の放電特性が改善される。
更に、入力端子１がハイレベル、制御端子２がロウレベ
ル、カレントミラー回路が遮断状態のときには、抵抗３
及びトランジスタ４の電流経路が遮断状態となるため、
省電力化の効果もある。In the present embodiment having such a configuration, both effects of the fourth and fifth embodiments can be obtained. That is, the consistency of the rent mirror circuit is improved. Further, the drivability of the transistor 4 constituting the current mirror circuit and the discharge characteristics of the charge storage capacitor 7 are improved.
Further, when the input terminal 1 is at the high level, the control terminal 2 is at the low level, and the current mirror circuit is in the cut-off state, the resistance 3
And the current path of the transistor 4 is cut off,
There is also a power saving effect.
【００４９】なお、前述の種々の実施例の組み合わせは
第６の実施例に示すものに限定されるものではない。例
えば、第５の実施例と第２又は第３の実施例とを組み合
わせてもよい。The combination of the various embodiments described above is not limited to the combination shown in the sixth embodiment. For example, the fifth embodiment may be combined with the second or third embodiment.
【００５０】[0050]
【発明の効果】以上詳述したように、本発明によれば、
スイッチ用トランジスタのオン抵抗による電圧降下を無
視できるため、カレントミラー回路の整合性を改善する
ことができる。また、スイッチ用トランジスタを流れる
電流は無視できるほど小さいくなるで、スイッチ用トラ
ンジスタを小型化することができ、半導体集積回路で構
成する場合にも、コストの上昇を抑制することができ
る。更に、種々のトランジスタを薄膜トランジスタと
し、有機エレクトロルミネセント素子の駆動回路に適用
する場合、大きなスイッチ用トランジスタは必要ないの
で、画素の開口率を向上させ輝度を向上させることがで
きる。As described in detail above, according to the present invention,
Since the voltage drop due to the on-resistance of the switching transistor can be neglected, the matching of the current mirror circuit can be improved. Further, the current flowing through the switching transistor becomes so small as to be negligible. Therefore, the size of the switching transistor can be reduced, and even when a semiconductor integrated circuit is used, an increase in cost can be suppressed. Furthermore, in the case where various transistors are thin film transistors and applied to a driving circuit of an organic electroluminescent element, a large switching transistor is not required, so that an aperture ratio of a pixel can be improved and luminance can be improved.
【図１】本発明の第１の実施例に係る定電流駆動回路を
示す回路図である。FIG. 1 is a circuit diagram showing a constant current drive circuit according to a first example of the present invention.
【図２】本発明の第２の実施例に係る定電流駆動回路を
示す回路図である。FIG. 2 is a circuit diagram showing a constant current drive circuit according to a second embodiment of the present invention.
【図３】本発明の第３の実施例に係る定電流駆動回路を
示す模式図である。FIG. 3 is a schematic diagram showing a constant current drive circuit according to a third embodiment of the present invention.
【図４】本発明の第４の実施例に係る定電流駆動回路を
示す回路図である。FIG. 4 is a circuit diagram showing a constant current drive circuit according to a fourth embodiment of the present invention.
【図５】本発明の第５の実施例に係る定電流駆動回路を
示す回路図である。FIG. 5 is a circuit diagram showing a constant current drive circuit according to a fifth embodiment of the present invention.
【図６】本発明の第６の実施例に係る定電流駆動回路を
示す回路図である。FIG. 6 is a circuit diagram showing a constant current drive circuit according to a sixth embodiment of the present invention.
【図７】従来の定電流駆動回路を示す回路図である。FIG. 7 is a circuit diagram showing a conventional constant current drive circuit.
１、１０１；入力端子 ２、１０２；制御端子 ３、１０３；抵抗 ４、５、６、９、１２、１３、１６、２６、３６、１０
４、１０５、１０６；トランジスタ ７、１０７；容量素子 ８、１０８；負荷 １０、１１０；電源端子 １１、１１１；接地端子1, 101; input terminal 2, 102; control terminal 3, 103; resistor 4, 5, 6, 9, 12, 13, 16, 26, 36, 10
4, 105, 106; transistors 7, 107; capacitive elements 8, 108; loads 10, 110; power supply terminals 11, 111;
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5H420 BB04 BB13 CC02 DD02 EA14 EA18 EA24 EA39 EB15 EB37 FF04 FF22 NA17 NA28 NB03 NB12 5J055 AX11 AX12 AX44 AX48 BX16 CX29 DX13 DX14 DX22 DX61 EX07 EY01 EY10 EY21 EZ04 EZ20 GX01 ──────────────────────────────────────────────────続 き Continued from the front page F term (reference)
Claims (7)
接続され接地にソースが接続された第１のトランジスタ
と、この第１のトランジスタのゲート及びドレインに接
続されたスイッチ用トランジスタと、このスイッチ用ト
ランジスタのゲートに接続されこのスイッチ用トランジ
スタの導通と非導通とを切替える信号が入力される制御
端子と、前記スイッチ用トランジスタにゲートが接続さ
れ接地にソースが接続され前記第１のトランジスタと共
にカレントミラー回路を構成する第２のトランジスタ
と、この第２のトランジスタのゲートに一方の電極が接
続され接地に他方の電極が接続された容量素子と、を有
することを特徴とする定電流駆動回路。1. An input terminal, a first transistor having a drain connected to the input terminal and a source connected to ground, a switching transistor connected to a gate and a drain of the first transistor, and a switch A control terminal connected to the gate of the switching transistor, to which a signal for switching between conduction and non-conduction of the switching transistor is inputted; and a gate connected to the switching transistor, a source connected to ground, and a current together with the first transistor. A constant current drive circuit, comprising: a second transistor forming a mirror circuit; and a capacitor having one electrode connected to the gate of the second transistor and the other electrode connected to the ground.
ネルの導電型は、前記スイッチ用トランジスタのチャネ
ルの導電型と相違し、前記第１のトランジスタのソース
と接地との間に接続された第１のレベルシフト用ダイオ
ードと、前記第２のトランジスタのソースと接地との間
に接続された第２のレベルシフト用ダイオードと、を有
することを特徴とする請求項１に記載の定電流駆動回
路。2. The channel of the first and second transistors has a conductivity type different from that of the channel of the switching transistor, and a channel connected between a source of the first transistor and ground. 2. The constant current drive circuit according to claim 1, further comprising: a first level shift diode; and a second level shift diode connected between a source of the second transistor and ground. .
ネルの導電型は、前記スイッチ用トランジスタのチャネ
ルの導電型と同じであることを特徴とする請求項１に記
載の定電流駆動回路。3. The constant current drive circuit according to claim 1, wherein the conductivity type of the channel of the first and second transistors is the same as the conductivity type of the channel of the switching transistor.
接続され接地にソースが接続された第１のトランジスタ
と、この第１のトランジスタのゲートとドレインとの間
に接続されたスイッチ用トランジスタと、このスイッチ
用トランジスタのゲートに接続されこのスイッチ用トラ
ンジスタの導通と非導通とを切替える信号が入力される
制御端子と、前記第１のトランジスタのゲートにゲート
が接続され接地にソースが接続され前記第１のトランジ
スタと共にカレントミラー回路を構成する第２のトラン
ジスタと、この第２のトランジスタのゲートに一方の電
極が接続され接地に他方の電極が接続された容量素子
と、を有することを特徴とする定電流駆動回路。4. An input terminal, a first transistor having a drain connected to the input terminal and a source connected to ground, and a switching transistor connected between a gate and a drain of the first transistor. A control terminal connected to the gate of the switching transistor, to which a signal for switching between conduction and non-conduction of the switching transistor is input; and a gate connected to the gate of the first transistor and a source connected to ground, A second transistor that forms a current mirror circuit together with the first transistor; and a capacitor having one electrode connected to the gate of the second transistor and the other electrode connected to ground. Constant current drive circuit.
のドレインとの間に接続された抵抗を有することを特徴
とする請求項１乃至４のいずれか１項に記載の定電流駆
動回路。5. The constant current drive circuit according to claim 1, further comprising a resistor connected between the input terminal and a drain of the first transistor.
れたソースフォロワ用トランジスタを有することを特徴
とする請求項５に記載の定電流駆動回路。6. The constant current drive circuit according to claim 5, further comprising a source follower transistor connected between said input terminal and said resistor.
機エレクトロルミネセント素子に接続されることを特徴
とする請求項１乃至６のいずれか１項に記載の定電流駆
動回路。7. The constant current drive circuit according to claim 1, wherein a drain of the second transistor is connected to an organic electroluminescent device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10229650A JP2953465B1 (en) | 1998-08-14 | 1998-08-14 | Constant current drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10229650A JP2953465B1 (en) | 1998-08-14 | 1998-08-14 | Constant current drive circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2953465B1 JP2953465B1 (en) | 1999-09-27 |
| JP2000056847A true JP2000056847A (en) | 2000-02-25 |
Family
ID=16895531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10229650A Expired - Lifetime JP2953465B1 (en) | 1998-08-14 | 1998-08-14 | Constant current drive circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2953465B1 (en) |
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| US10971078B2 (en) | 2018-02-12 | 2021-04-06 | Ignis Innovation Inc. | Pixel measurement through data line |
| US11847976B2 (en) | 2018-02-12 | 2023-12-19 | Ignis Innovation Inc. | Pixel measurement through data line |
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| JP2953465B1 (en) | 1999-09-27 |
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