CN111723022B

CN111723022B - Data storage method, memory storage device and memory control circuit unit

Info

Publication number: CN111723022B
Application number: CN201910212340.3A
Authority: CN
Inventors: 谢佾锠; 张哲玮
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2019-03-20
Filing date: 2019-03-20
Publication date: 2024-07-02
Anticipated expiration: 2039-03-20
Also published as: CN111723022A

Abstract

The invention provides a data storage method, a memory storage device and a memory control circuit unit. The method comprises the following steps: configuring a plurality of logical addresses to map to physical programming units of a plurality of physical erasing units; grouping logical addresses into a plurality of logical address groups; receiving a write command and data to be stored in the logic addresses; writing the data into the entity programming units respectively; recording the data writing time stamp of each entity erasing unit; recording the data spreading number of each logic address group; and if the data distribution number of the first logical address group is smaller than the data distribution threshold value and the data writing time stamp of the physical erasing unit for writing the data belonging to the first logical address group is smaller than the time stamp threshold value, identifying the data belonging to the first logical address group as cold data.

Description

Data storage method, memory storage device and memory control circuit unit

Technical Field

The present invention relates to a data storage method for a rewritable nonvolatile memory, and a memory storage device and a memory control circuit unit using the same.

Background

Digital cameras, mobile phones and MP3 players have grown very rapidly over the years, such that consumer demand for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable multimedia devices.

Generally, if cold data can be identified that is not updated from stored data, operations such as garbage collection can be performed more efficiently. Therefore, how to identify the cold data and the hot data in the rewritable nonvolatile memory module and effectively improve the access efficiency of the cold data is one of the subjects studied by the person skilled in the art.

Disclosure of Invention

The invention provides a data storage method, a memory storage device and a memory control circuit unit.

An exemplary embodiment of the invention provides a data storage method for a rewritable nonvolatile memory module having a plurality of physical erase units. The data storage method comprises the following steps: configuring a plurality of logical addresses to map to a plurality of physical programming units of the physical erase units; grouping the logical addresses into a plurality of logical address groups; receiving a plurality of write instructions and a plurality of data to be stored to the logic addresses from a host system respectively; the data are written into the physical programming units of the physical erasing units respectively. In addition, the data storage method further comprises the following steps: the data of the physical erasing units of the first logical address group in the logical address groups are identified as the first type data according to the data writing time stamp of each physical erasing unit and the data distribution number of the physical erasing units in each logical address group.

In an exemplary embodiment of the present invention, the data storage method further includes: if the data distribution number of the first logical address group in the logical address groups is smaller than the data distribution threshold value and the data writing time stamp of the physical erasing unit for writing the data belonging to the first logical address group is smaller than the time stamp threshold value, the data belonging to the first logical address group is identified as the first type data.

In an exemplary embodiment of the present invention, the data storage method further includes: recording the data writing time stamp of each entity erasing unit; recording the data distribution number of the entity erasing unit in each logic address group; and if the data distribution number of the first logical address group in the logical address groups is smaller than the data distribution threshold value and the data writing time stamp of at least one physical erasing unit written with the data belonging to the first logical address group in the physical erasing units is smaller than the time stamp threshold value, identifying the data of the physical erasing unit belonging to the first logical address group as the first type data.

In an exemplary embodiment of the present invention, the data storage method further includes: the data distribution number of each logical address group is set according to the number of the physical erasing units written with the data belonging to each logical address group, wherein the number of the physical erasing units written with the data belonging to the first logical address group is the data distribution number of the first logical address group.

In an exemplary embodiment of the present invention, the data storage method further includes: and establishing a logic address group bit map to record the physical erasing units for writing the data belonging to each logic address group, wherein each logic address group is provided with a plurality of writing marks, and the writing marks respectively correspond to the physical erasing units. When the data belonging to the corresponding logical address group in the logical address groups is written in the physical erasing units, the writing mark of the physical erasing units written in the data belonging to the corresponding logical address group is recorded as 1.

In an exemplary embodiment of the present invention, the step of recording the data distribution number of each logical address group includes: the write flag value of the physical erase unit for writing the data belonging to the corresponding logical address group is added up as the data distribution number of the corresponding logical address group.

In an exemplary embodiment of the present invention, the data storage method further includes: in the logical address group bit map, the write marks belonging to each logical address group and corresponding to the entity erasing units are ordered on a first axis according to the data distribution number of each logical address group, and in the logical address group bit map, the write marks belonging to each logical address group and corresponding to the entity erasing units are ordered on a second axis according to the data write time stamp of each entity erasing unit.

In an exemplary embodiment of the present invention, the data storage method further includes: if the data belonging to the first logical address group is identified as the first type data, extracting the target physical erasing unit from the idle area, and moving the data belonging to the first logical address group from at least one physical erasing unit to the target physical erasing unit.

In an exemplary embodiment of the present invention, the time stamp threshold is set to one half of the number of such physical erased cells, and the data distribution threshold is set to 7.

In an exemplary embodiment of the invention, the size of each logical address group is the same as the capacity of one physically erased cell.

An exemplary embodiment of the present invention provides a memory control circuit unit for a rewritable nonvolatile memory module. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is used for being electrically connected to the host system. The memory interface is electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical erasing units. The memory management circuit is electrically connected to the host interface and the memory interface. The memory management circuit is used for configuring a plurality of logic addresses to be mapped to a plurality of physical programming units of the physical erasing units and grouping the logic addresses into a plurality of logic address groups. In addition, the memory management circuit is used for respectively receiving a plurality of writing instructions and a plurality of data to be stored in the logic addresses from the host system, and respectively writing the data into the physical programming units of the physical erasing units. The memory management circuit is further configured to identify the data of the physical erase unit of the first logical address group of the logical address groups as the first type of data according to the data write time stamp of each of the physical erase units and the data distribution number of the physical erase unit in each of the logical address groups.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to record a data write time stamp of each physical erase unit, record a data distribution number of each logical address group, and identify that the data belonging to the first logical address group is the first type of data if the data distribution number of the first logical address group is smaller than a data distribution threshold value and the data write time stamp of the physical erase unit writing the data belonging to the first logical address group is smaller than a time stamp threshold value.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to set a data distribution number of each logical address group according to a number of physical erasing units writing data belonging to each logical address group, wherein the number of physical erasing units writing data belonging to the first logical address group is the data distribution number of the first logical address group.

In an exemplary embodiment of the invention, the memory management circuit is further configured to establish a logical address group bit map to record physical erase units for writing data belonging to each logical address group, wherein each logical address group has a plurality of write marks and the write marks respectively correspond to the physical erase units. When the physical erasing units write the data belonging to the corresponding logical address groups in the logical address groups, the memory management circuit is further used for recording the writing mark of the physical erasing units written with the data belonging to the corresponding logical address groups as 1.

In an exemplary embodiment of the present invention, in the operation of recording the data distribution number of each logical address group, the memory management circuit is further configured to sum up the values of the write marks of the physical erase units writing the data belonging to the corresponding logical address group as the data distribution number of the corresponding logical address group.

In an exemplary embodiment of the present invention, in the logic address group bit map, the memory management circuit is further configured to sort the write marks belonging to each logic address group and corresponding to the physical erase units on the first axis according to the data distribution number of each logic address group, and the memory management circuit is further configured to sort the write marks belonging to each logic address group and corresponding to the physical erase units on the second axis according to the data write time stamp of each physical erase unit.

In an exemplary embodiment of the present invention, if the data belonging to the first logical address group is identified as the first type data, the memory management circuit is further configured to extract the target physical erase unit from the idle area, and move the data belonging to the first logical address group from the at least one physical erase unit to the target physical erase unit.

An exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for being electrically connected to the host system. The rewritable nonvolatile memory module is provided with a plurality of physical erasing units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for configuring a plurality of logic addresses to be mapped to a plurality of physical programming units of the physical erasing units, grouping the logic addresses into a plurality of logic address groups, respectively receiving a plurality of writing instructions and a plurality of data to be stored in the logic addresses from the host system, and respectively writing the data into the physical programming units of the physical erasing units. In addition, the memory control circuit unit is further configured to identify that the data of the physical erasing unit of the first logical address group in the logical address groups is the first type data according to the data writing time stamp of each physical erasing unit and the data distribution number of the physical erasing unit in each logical address group.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to record a data write timestamp of each physical erase unit, record a data distribution number of each logical address group, and identify that the data belonging to the first logical address group is the first type of data if the data distribution number of the first logical address group is smaller than a data distribution threshold value and the data write timestamp of the physical erase unit writing the data belonging to the first logical address group is smaller than a timestamp threshold value.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to set a data distribution number of each logical address group according to a number of physical erasing units writing data belonging to each logical address group, wherein the number of physical erasing units writing data belonging to the first logical address group is the data distribution number of the first logical address group.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to establish a logical address group bit map to record physical erase units for writing data belonging to each logical address group, wherein each logical address group has a plurality of write marks and the write marks respectively correspond to the physical erase units. When the data belonging to the corresponding logical address group of the logical address groups is written into the physical erasing units, the memory control circuit unit is also used for respectively recording the writing mark of the physical erasing units written with the data belonging to the corresponding logical address group as 1.

In an exemplary embodiment of the present invention, in the operation of recording the data distribution number of each logical address group, the memory control circuit unit is further configured to sum up the values of the write marks of the physical erase units writing the data belonging to the corresponding logical address group as the data distribution number of the corresponding logical address group.

In an exemplary embodiment of the present invention, in the logic address group bit map, the memory control circuit unit is further configured to sort the write marks belonging to each logic address group and corresponding to the physical erase units on the first axis according to the data distribution number of each logic address group, and the memory control circuit unit is further configured to sort the write marks belonging to each logic address group and corresponding to the physical erase units on the second axis according to the data write time stamp of each physical erase unit.

In an exemplary embodiment of the present invention, if the data belonging to the first logical address group is identified as the first type data, the memory control circuit unit is further configured to extract the target physical erase unit from the idle area, and move the data belonging to the first logical address group from the at least one physical erase unit to the target physical erase unit.

Based on the above, the invention provides a data storage method, a memory storage device and a memory control circuit unit. The method identifies whether the stored data is the first type data according to the data distribution number of the logic address group and the data writing time stamp of the entity erasing unit, and starts the data reforming operation on the first type data so as to centralize the first type data, thereby accelerating the subsequent data reading operation and effectively improving the data access efficiency.

Drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention.

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another example embodiment of the invention.

FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention.

Fig. 7 is a diagram illustrating the creation of a logical address group bit map according to an exemplary embodiment of the present invention.

Fig. 8 is a diagram illustrating a reformatted logical address group bit map according to another exemplary embodiment of the present invention.

FIG. 9 is a schematic diagram illustrating a data reforming operation initiated on cold data according to an example embodiment of the present invention.

Fig. 10 is a flow chart illustrating the identification of cold data according to an exemplary embodiment of the present invention.

FIG. 11 is a flowchart illustrating a data reforming operation for cold data initiation according to an exemplary embodiment of the present invention.

[ Symbolic description ]

10: Memory storage device

11: Host system

110: System bus

111: Processor and method for controlling the same

112: Random access memory

113: Read-only memory

114: Data transmission interface

12: Input/output (I/O) device

20: Motherboard

201: USB flash disk

202: Memory card

203: Solid state disk

204: Wireless memory storage device

205: Global positioning system module

206: Network interface card

207: Wireless transmission device

208: Keyboard with keyboard body

209: Screen panel

210: Horn with horn body

32: SD card

33: CF card

34: Embedded memory device

341: Embedded multimedia card

342: Embedded multi-chip packaging storage device

402: Connection interface unit

404: Memory control circuit unit

406: Rewritable nonvolatile memory module

502: Memory management circuit

504: Host interface

506: Memory interface

508: Error checking and correcting circuit

510: Buffer memory

512: Power management circuit

601: Storage area

602: Idle zone

610 (0) To 610 (B): physical erasing unit

612 (0) To 612 (C): logic unit

TRG1, TRG2: target physical erasing unit

LG (0) -LG (B): logical address group

Bit sum: number of data spreads

S1001 to S1017: step (a)

S1101 to S1111: step (a)

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit unit). Memory storage devices are typically used with host systems so that the host system can write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 are electrically connected to a system bus 110.

In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 through the system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.

In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 can be electrically connected to the memory storage device 10 through a wired or wireless manner via the data transmission interface 114. The memory storage device 10 may be, for example, a usb flash disk 201, a memory card 202, a Solid state disk (Solid STATE DRIVE, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a Near Field Communication (NFC) memory storage, a wireless fax (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (iBeacon) based on a wide variety of wireless Communication technologies. In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

In an example embodiment, the host system referred to is any system that can cooperate with substantially a memory storage device to store data. Although the host system is described in the above exemplary embodiment as a computer system, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may be a system such as a Digital camera, a video camera, a communication device, an audio player, a video player or a tablet computer, and the memory storage device 30 may be a variety of nonvolatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33 or an embedded storage device 34. The embedded storage device 34 includes embedded storage devices of various types such as an embedded multimedia card (embedded Multi MEDIA CARD, EMMC) 341 and/or an embedded Multi-chip package (embedded Multi CHIP PACKAGE, EMCP) storage device 342, which directly electrically connects the memory module to the substrate of the host system.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404, and a rewritable nonvolatile memory module 406.

The connection interface unit 402 is used for electrically connecting the memory storage device 10 to the host system 11. In the present exemplary embodiment, connection interface unit 402 is compatible with the serial advanced technology attachment (SERIAL ADVANCED Technology Attachment, SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also be a standard compliant with a parallel advanced technology attachment (PARALLEL ADVANCED Technology Attachment, PATA) standard, an Institute of Electrical and Electronics Engineers (IEEE) ELECTRICAL AND Electronic Engineers standard, a high-speed peripheral component interconnect (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCI Express) standard, a universal serial bus (Universal Serial Bus, USB) standard, an SD interface standard, a Ultra-high-speed generation (Ultra HIGH SPEED-I, UHS-I) interface standard, a Ultra-high-speed second-generation (Ultra HIGH SPEED-II, UHS-II) interface standard, a Memory Stick (MS) interface standard, an MCP interface standard, an MMC interface standard, an eMMC interface standard, a universal flash Memory (Universal Flash Storage, UFS) interface standard, an eMCP interface standard, a CF interface standard, an integrated drive Electronics (INTEGRATED DEVICE Electronics, IDE) standard, or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in a single chip, or the connection interface unit 402 may be disposed off-chip with the memory control circuit unit 404.

The memory control circuit unit 404 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to the instructions of the host system 11.

The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a single-level memory cell (SINGLE LEVEL CELL, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a Multi-level memory cell (Multi LEVEL CELL, MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a complex-level memory cell (TRIPLE LEVEL CELL, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. By applying the read voltage, it can be determined which memory state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In the exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 form a plurality of physical program cells, and the physical program cells form a plurality of physical erase cells. Specifically, memory cells on the same word line constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be classified into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant Bit (LEAST SIGNIFICANT Bit, LSB) of a memory cell is that belonging to the lower physical programming cell, and the most significant Bit (Most Significant Bit, MSB) of a memory cell is that belonging to the upper physical programming cell. In general, in MLC NAND-type flash memory, the writing speed of the lower physical programming unit is greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.

In the present exemplary embodiment, the physical programming unit is the minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit is a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, the physical programming units typically include data bits and redundancy bits. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, 8, 16 or a greater or lesser number of physical fans may be included in the data bit zone, and the size of each physical fan may be greater or lesser. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased together. For example, the physical erased cells are physical blocks (blocks).

Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504 and a memory interface 506.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform writing, reading and erasing operations of data while the memory storage device 10 is operating. The operation of the memory management circuit 502 is described as follows, which is equivalent to the description of the operation of the memory control circuit unit 404.

In the present exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

In another example embodiment, the control instructions of the memory management circuit 502 may also be stored in program code form in a specific area of the rewritable non-volatile memory module 406 (e.g., a system area of the memory module dedicated to storing system data). In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (boot code), and when the memory control circuit 404 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.

Furthermore, in another example embodiment, the control instructions of the memory management circuit 502 may also be implemented in a hardware type. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read instruction sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erase circuit is configured to issue an erase command sequence to the rewritable nonvolatile memory module 406 to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, read command sequence, and erase command sequence may include one or more program codes or command codes, respectively, and are used to instruct the rewritable nonvolatile memory module 406 to perform the corresponding write, read, erase, etc. In an example embodiment, the memory management circuitry 502 may also issue other types of sequences of instructions to the rewritable non-volatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 504 is electrically connected to the memory management circuit 502 and is used for receiving and recognizing the commands and data transmitted by the host system 11. That is, the instructions and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the present exemplary embodiment, host interface 504 is compliant with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may also be compatible with PATA standards, IEEE 1394 standards, PCI Express standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.

The memory interface 506 is electrically connected to the memory management circuit 502 and is used to access the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format acceptable to the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 is to access the rewritable nonvolatile memory module 406, the memory interface 506 will transmit the corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). These sequences of instructions are, for example, generated by memory management circuitry 502 and transferred to rewritable non-volatile memory module 406 through memory interface 506. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code and a memory address.

In an example embodiment, the memory control circuit unit 404 further includes an error checking and correction circuit 508, a buffer memory 510, and a power management circuit 512.

The error checking and correcting circuit 508 is electrically connected to the memory management circuit 502 and is used for performing error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable nonvolatile memory module 406. Then, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are read at the same time, and the error check and correction circuit 508 performs an error check and correction operation on the read data according to the error correction code and/or the error check code.

The buffer memory 510 is electrically connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is electrically connected to the memory management circuit 502 and is used for controlling the power of the memory storage device 10.

It should be noted that in the following exemplary embodiments, the operation of the physical erase unit in terms of "select" and "group" is a logical concept in describing the management of the physical erase unit of the rewritable nonvolatile memory module 406. That is, the physical locations of the physical erased cells of the rewritable nonvolatile memory module 406 are not changed, but the physical erased cells of the rewritable nonvolatile memory module 406 are logically operated.

Referring to FIG. 6, the memory management circuit 502 groups the physical erase units 610 (0) -610 (B) of the rewritable nonvolatile memory module 406 into a memory area 601 and a spare (spare) area 602. For example, physical erase units 610 (0) through 610 (A) belong to the memory area 601, and physical erase units 610 (A+1) through 610 (B) belong to the spare area 602. In the present exemplary embodiment, a physically erased cell refers to a physically erased cell. However, in another exemplary embodiment, one physical erase unit may also include a plurality of physical erase units. In addition, the memory management circuit 502 may associate a physical erase unit to one of the memory area 601 and the spare area 602 by using a tag.

During operation of the memory device 10, the association of a physical erase unit with the memory area 601 or the spare area 602 may dynamically change. For example, when write data is received from the host system 11, the memory management circuit 502 selects a physical erase unit from the spare area 602 to store at least a portion of the write data and associates the physical erase unit to the memory area 601. In addition, after erasing a physical erased cell belonging to the memory area 601 to erase data therein, the memory management circuit 502 associates the erased physical erased cell to the spare area 602.

In the present exemplary embodiment, the physical erased cells belonging to the spare area 602 are also referred to as spare physical erased cells, and the physical erased cells belonging to the storage area 601 are also referred to as non-spare (non-spare) physical erased cells. Each physical erased cell belonging to the spare area 602 is an erased physical erased cell and does not store any data, and each physical erased cell belonging to the storage area 601 stores data. Furthermore, each physical erase unit belonging to the spare area 602 may not store any valid data, and each physical erase unit belonging to the storage area 601 may store valid data and/or invalid data.

In an example embodiment, memory management circuit 502 configures logic units 612 (0) -612 (C) to map physically erased cells in memory region 601. In the exemplary embodiment, the host system 11 accesses the physical erase unit belonging to the memory area 601 by a Logical Address (LA). Thus, each of the logic units 612 (0) -612 (C) refers to a logical address. However, in another exemplary embodiment, each of the logic units 612 (0) -612 (C) may also refer to a logic program unit, a logic erase unit, or be composed of a plurality of consecutive or non-consecutive logic addresses. In addition, each of logic cells 612 (0) -612 (C) may be mapped to one or more physical erase cells.

In the exemplary embodiment, the memory management circuit 502 records a mapping relationship (also referred to as a logical-to-physical mapping relationship) between logical units and physical erase units in at least one logical-to-physical mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can perform data access to the memory storage device 10 according to the logical-to-physical mapping table.

In the present exemplary embodiment, valid data is the latest data belonging to a certain logical unit, and invalid data is not the latest data belonging to any logical unit. For example, if the host system 11 stores a new data in a logical unit and overwrites old data originally stored in the logical unit (i.e., updates data belonging to the logical unit), the new data stored in the storage area 601 is the latest data belonging to the logical unit and is marked as valid, and the overwrites old data may still be stored in the storage area 601 but marked as invalid. In the exemplary embodiment, if the data belonging to a certain logical unit is updated, the mapping relationship between the logical unit and the physical erase unit storing the old data belonging to the logical unit is removed, and the mapping relationship between the logical unit and the physical erase unit storing the latest data belonging to the logical unit is established.

Referring to FIG. 7, in an exemplary embodiment, the memory management circuit 502 configures a plurality of logical addresses to map to physical program units of the physical erase units 610 (0) to 610 (B) of the rewritable nonvolatile memory module 406, and groups the logical addresses into logical address groups LG (0), LG (1), LG (2) … LG (B), wherein the size of each of the logical address groups LG (0) to LG (B) is the same as the capacity of one physical erase unit. For example, if the capacity of a physical erase unit is 72MB, then logical addresses 0-72MB belong to logical address group LG (0), logical addresses 72MB-144MB belong to logical address group LG (1), logical addresses 144MB-216MB belong to logical address group LG (2), and so on.

The memory management circuit 502 receives a plurality of write commands and a plurality of data to be stored in the logical addresses from the host system 11, and writes the data into a plurality of physical program units of the physical erase unit 610 (0) to the physical erase unit 610 (B), respectively.

The memory management circuit 502 records the data write time stamps of each of the physical erasing units 610 (0) to 610 (B), and the memory management circuit 502 records the data distribution number of each of the logical address groups. The memory management circuit 502 calculates the number of physical erase units that write data belonging to each of the logical address groups, and sets the number of physical erase units that write data belonging to each of the logical address groups as the data distribution number of each of the logical address groups. In an exemplary embodiment, the number of at least one physical erasing unit for writing data belonging to the logical address group LG (0) is the data distribution number of the logical address group LG (0), wherein the number of physical erasing units for writing data belonging to the logical address group LG (0) is 4, and the data distribution number of the logical address group LG (0) is 4.

In an exemplary embodiment, when each of the physical erasing units 610 (0) to 610 (B) writes data belonging to a corresponding logical address group among the logical address groups, a write flag of at least one physical erasing unit to which the data belonging to the corresponding logical address group is written is recorded as 1.

For example, when writing data belonging to the logical address groups LG (2) and LG (7) in the physical erasing unit 610 (0), the memory management circuit 502 records the write flag of the physical erasing unit 610 (0) in which data belonging to the logical address groups LG (2) and LG (7) are written as 1, respectively. That is, the data written to the physical erase unit 610 (0) is written to the logical addresses 144MB-216MB and the logical addresses 503MB-576 MB. Here, the memory management circuit 502 records a write flag of 0 for writing the physical erasing unit 610 (0) belonging to the logical address group other than the logical address groups LG (2) and LG (7).

For another example, when writing data belonging to the logical address groups LG (1), LG (3), and LG (500) in the physical erasing unit 610 (2), the memory management circuit 502 records the write flag of the physical erasing unit 610 (2) in which data belonging to the logical address groups LG (1), LG (3), and LG (500) is written as 1, respectively. That is, the data written into the physical erasing unit 610 (2) is written into the logical addresses 72MB-144MB, the logical addresses 216MB-288MB and the logical addresses 72X 500 MB-72X 501MB. Here, the memory management circuit 502 records a write flag of 0 for the physical erasing unit 610 (2) which is written with logical address groups other than the logical address groups LG (1), LG (3) and LG (500).

Similarly, when writing data belonging to the logical address groups LG (0) to LG (B) in the physical erasing units 610 (0) to 610 (B), the memory management circuit 502 records the write marks of the physical erasing units writing data belonging to the logical address groups LG (0) to LG (B), respectively. To build a logical address group bit map as shown in fig. 7. In particular, according to the logical address group bit map shown in fig. 7, the write marks of the physical erasing units writing the data belonging to the logical address groups LG (0) to LG (B) in the physical erasing units 610 (0) to 610 (B), respectively, can be known.

In an example embodiment, the memory management circuit 502 sums the values of the write marks of at least one physical erase unit that writes data belonging to the corresponding logical address group as the data scatter number (bit sum) of the corresponding logical address group. Taking as an example the physical erase unit that sums up the data written in the logical address group LG (1). The memory management circuit 502 records the write marks of the physical erasing units 610 (2) and 610 (7) writing the data belonging to the logical address group LG (1) as 1, and sums the values of the write marks of the physical erasing units 610 (2) and 610 (7) writing the data belonging to the logical address group LG (1) as the data distribution number of the logical address group LG (1), respectively. Therefore, the data distribution number of the logical address group LG (1) is 2. That is, the data distribution indicates that the data written into the logical address group LG (1) is distributed on the physical erasing units 610 (2) and 610 (7).

Similarly, the physical erasing unit for adding up the data written in the logical address group LG (4) is taken as an example. The memory management circuit 502 records the write flag of the physical erasing unit 610 (6) writing the data belonging to the logical address group LG (4) as 1, and sums the values of the write flags of the physical erasing unit 610 (6) writing the data belonging to the logical address group LG (4) as the data distribution number of the logical address group LG (4). Therefore, the data distribution number of the logical address group LG (4) is 1. That is, the data distribution indicates that the data written into the logical address group LG (4) is distributed only on the physical erasing units 610 (6). By analogy, the memory management circuit 502 sums the values of the write marks of at least one physical erase unit writing data belonging to the corresponding logical address group as the data distribution number of the corresponding logical address group.

Referring to FIG. 8, in the logical address group bit map, the memory management circuit 502 sorts the write marks belonging to each of the logical address groups and corresponding to the physical erase units on the first axis according to the data distribution number of each of the logical address groups. The memory management circuit 502 also sorts the write marks belonging to each of the logical address groups and corresponding to the physical erasing units on the second axis according to the data write time stamp of each of the physical erasing units. In an example embodiment, the first axis is set to the X-axis and the second axis is set to the Y-axis.

In an exemplary embodiment, the memory management circuit 502 sorts the write marks belonging to each of the logical address groups and corresponding to the physical erase units in order from small to large according to the data distribution number of each of the logical address groups in the X-axis direction.

In addition, the memory management circuit 502 also sorts the write marks belonging to each logical address group and corresponding to the physical erasing units in the Y-axis direction according to the sequence of the data write time stamps of the physical erasing units. That is, the write marks belonging to each logical address group and corresponding to the physical erase unit of the previous (old) data write timestamp are arranged in the lower half of the Y-axis, and the write marks belonging to each logical address group and corresponding to the physical erase unit of the next (new) data write timestamp are arranged in the upper half of the Y-axis.

Thus, the memory management circuit 502 sorts the write marks corresponding to the physical erase units belonging to each logical address group according to the data distribution number of each logical address group and the data write time stamp of each physical erase unit, so as to reform the bit map of the logical address group. In the reformed logical address group bit map, the data written in the same logical address group with the previous (old) data scattered in fewer physical erase units (i.e. fewer data scattered in each logical address group) is identified as the first type of data, which in the present exemplary embodiment is cold data (old and cold data). In contrast, the memory management circuit 502 identifies the data that is later in the data write time stamp (i.e., newer in the data write time stamp) and that is written to the same logical address group as non-cold data as data that is scattered in more physical erased cells (i.e., more data is scattered for each of the logical address groups). The memory management circuit 502 can divide the non-cold data into new cold data (new and cold data) belonging to the second type of data, new hot data (new and hot data) belonging to the third type of data, and old hot data (old and hot data) belonging to the fourth type of data according to the data distribution number of each logical address group and the data writing time stamp of each physical erasing unit, but the invention is not limited thereto.

In an exemplary embodiment, the memory management circuit 502 identifies the data belonging to the logical address group LG (1) as cold data if the data distribution number of the logical address group LG (1) is less than the data distribution threshold and the data write timestamp of at least one of the physical erase units writing the data belonging to the logical address group LG (1) is less than the timestamp threshold. In the present exemplary embodiment, the data distribution threshold may be set to 7 and the time stamp threshold may be set to one half of the number of physically erased cells. When the memory management circuit 502 determines that the data distribution number of the logical address group LG (1) is 2 and the data distribution number is less than the data distribution threshold, and the data writing time stamp of the physical erasing units 610 (2) and 610 (7) is less than the time stamp threshold, the memory management circuit 502 identifies the data belonging to the logical address group LG (1) as cold data, and the memory management circuit 502 starts the data reforming operation for the cold data.

Please refer to fig. 9. In an exemplary embodiment, when the memory management circuit 502 identifies that the data belonging to the logical address group LG (1) belongs to cold data, the memory management circuit 502 extracts the target physical erase unit TRG1 from the idle area 602 and moves the data belonging to the logical address group LG (1) from the physical erase unit 610 (2) and the physical erase unit 610 (7) to the target physical erase unit TRG1.

In another example embodiment, the memory management circuit 502 extracts the target physical erase cell TRG2 from the inactive area 602, and moves data not belonging to the logical address group LG (1) from the physical erase cells 610 (2) and 610 (7) to the target physical erase cell TRG2. The target physical erase units TRG1 and TRG2 are empty physical erase units extracted from the free area 602 for rotation.

Please refer to fig. 10. In step S1001, the memory management circuit 502 configures a plurality of logical addresses to map to a plurality of physical program units in a plurality of physical erase units.

In step S1003, the memory management circuit 502 groups the logical addresses into a plurality of logical address groups. In an exemplary embodiment, the memory management circuit 502 groups the logical addresses into logical address groups LG (0), LG (1), LG (2) … LG (B), wherein the size of each logical address group is the same as the capacity of one physical erase unit.

In step S1005, the memory management circuit 502 receives a plurality of write commands and a plurality of data to be stored at the logical addresses from the host system 11, respectively.

In step S1007, the memory management circuit 502 writes the data into the physical programming units of the physical erasing units 610 (0) to 610 (B), respectively.

In step S1009, the memory management circuit 502 records the data write time stamp of each of the physical erase units.

In step S1011, the memory management circuit 502 records the data distribution number of each of the logical address groups. In an exemplary embodiment, the memory management circuit 502 calculates the number of physical erase units written with data belonging to each logical address group, and sets the number of physical erase units written with data belonging to each logical address group to the data distribution number of each logical address group.

In step S1013, the memory management circuit 502 determines whether the data distribution number of the first logical address group of the logical address groups is smaller than the data distribution threshold value and whether the data write time stamp of the physical erase unit writing the data belonging to the first logical address group is smaller than the time stamp threshold value. In an exemplary embodiment, the time stamp threshold is set to one half the number of physically erased cells.

In step S1015, if the data distribution number of the first logical address group is smaller than the data distribution threshold value and the data writing time stamp of the physical erasing unit for writing the data belonging to the first logical address group is smaller than the time stamp threshold value, the memory management circuit 502 identifies the data belonging to the first logical address group as cold data.

In step S1017, if the data distribution number of the first logical address group is not less than the data distribution threshold and the data writing time stamp of the physical erasing unit for writing the data belonging to the first logical address group is not less than the time stamp threshold, the memory management circuit 502 identifies the data belonging to the first logical address group as non-cold data.

Referring to FIG. 11, in step S1101, when data belonging to a corresponding logical address group among the logical address groups is written in the physical erase unit, the memory management circuit 502 records the write flag of the physical erase unit written with the data belonging to the corresponding logical address group as 1.

In step S1103, the memory management circuit 502 sums up the values of the write marks of the physical erase units writing the data belonging to the corresponding logical address group as the data distribution number of the corresponding logical address group.

In step S1105, in the logical address group bit map, the memory management circuit 502 sorts the write marks belonging to each logical address group and corresponding to the physical erase unit on the first axis according to the data distribution number of each logical address group.

In step S1107, in the logical address group bit map, the memory management circuit 502 sorts the write marks belonging to each logical address group and corresponding to the physical erase units on the second axis according to the data write time stamps of the physical erase units.

In step S1109, when the memory management circuit 502 identifies the data belonging to the first logical address group as cold data, the target physical erase unit is extracted from the idle area 602, and the data belonging to the first logical address group is moved from the physical erase unit to the target physical erase unit.

In step S1111, the memory management circuit 502 continues to extract another target physical erase unit from the spare area 602, and moves data not belonging to the first logical address group from the physical erase unit to the target physical erase unit. Thus, the cold data can be read from a physical erasing unit in the subsequent data processing process, thereby improving the access speed.

In summary, the present invention provides a data storage method, a memory storage device and a memory control circuit unit. The method identifies whether the data is cold data according to the data distribution number of the logical address group and the data writing time stamp of the entity erasing unit for writing the data belonging to the logical address group, and starts the data reforming operation on the cold data so as to move the cold data to one entity erasing unit, thereby being capable of directly reading the cold data on the entity erasing unit in the subsequent data processing process and effectively improving the access efficiency of the cold data.

Although the invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather may be modified and practiced by those skilled in the art without departing from the spirit and scope of the present invention.

Claims

1. A data storage method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical erase units, the data storage method comprising:

configuring a plurality of logical addresses to map to a plurality of physical programming units of the plurality of physical erase units;

grouping the plurality of logical addresses into a plurality of logical address groups;

Receiving a plurality of write instructions and a plurality of data to be stored to the plurality of logical addresses from a host system respectively;

writing the plurality of data into the physical programming units of the plurality of physical erasing units respectively; and

Identifying that the data of the entity erasing units of a first logic address group in the plurality of logic address groups is first type data according to the data writing time stamp of each entity erasing unit and the data distribution number of the entity erasing units in each logic address group, wherein the first type data is cold data;

The step of recording the data distribution number of each of the plurality of logical address groups includes:

The value of the write flag of at least one physical erase unit for writing data belonging to each of the plurality of logical address groups is summed as the data distribution number of each of the plurality of logical address groups.

2. The data storage method of claim 1, further comprising:

recording the data writing time stamp of each entity erasing unit; and

And if the data distribution number of the first logical address group in the plurality of logical address groups is smaller than a data distribution threshold value and the data writing time stamp of at least one entity erasing unit which writes the data belonging to the first logical address group in the plurality of entity erasing units is smaller than a time stamp threshold value, identifying the data of the entity erasing unit belonging to the first logical address group as the first type data.

3. The data storage method of claim 1, further comprising:

setting the data distribution number of each of the plurality of logical address groups according to the number of physical erasing units for writing data belonging to each of the plurality of logical address groups,

Wherein the number of physical erase units for writing data belonging to the first logical address group is the data distribution number of the first logical address group.

4. A data storage method according to claim 3, further comprising:

Establishing a logic address group bit map to record entity erasing units for writing data belonging to a plurality of logic address groups, wherein each logic address group is provided with a plurality of writing marks, and the writing marks respectively correspond to the entity erasing units; and

When the data belonging to the corresponding logical address group in the plurality of logical address groups is written in the plurality of physical erasing units, the writing mark of at least one physical erasing unit written in the data belonging to the corresponding logical address group is recorded as 1.

5. The data storage method of claim 4, further comprising:

In the logical address group bit map, according to the data distribution number of each of the plurality of logical address groups, the writing marks belonging to each of the plurality of logical address groups and corresponding to the plurality of entity erasing units are ordered on a first axis; and

And ordering the writing marks belonging to the plurality of logical address groups and corresponding to the plurality of physical erasing units on a second axis according to the data writing time stamp of the plurality of physical erasing units.

6. The data storage method of claim 5, further comprising:

And if the data belonging to the first logical address group is identified as the first type data, extracting a target entity erasing unit from the idle area, and moving the data belonging to the first logical address group from the at least one entity erasing unit to the target entity erasing unit.

7. The data storage method of claim 2, wherein the time stamp threshold is set to one half of the number of the plurality of physically erased cells, the data distribution threshold is set to 7.

8. The data storage method of claim 1, wherein each of the plurality of logical address groups has a size equal to a capacity of one physical erase unit.

9. A memory control circuit unit for a rewritable non-volatile memory module, the memory control circuit unit comprising:

the host interface is used for being electrically connected to a host system;

The memory interface is used for being electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of entity erasing units; and

A memory management circuit electrically connected to the host interface and the memory interface,

Wherein the memory management circuit is configured to configure a plurality of logical addresses for mapping to a plurality of physical program units of the plurality of physical erase units,

Wherein the memory management circuitry is to group the plurality of logical addresses into a plurality of logical address groups,

Wherein the memory management circuit is used for respectively receiving a plurality of write instructions and a plurality of data to be stored to the plurality of logical addresses from the host system,

Wherein the memory management circuit is used for writing the plurality of data into the physical programming units of the plurality of physical erasing units respectively, and

Wherein the memory management circuit is configured to identify the data of the physical erase unit of a first logical address group of the plurality of logical address groups as a first type of data based on the data write time stamp of each of the plurality of physical erase units and the data distribution number of the physical erase unit in each of the plurality of logical address groups, wherein the first type of data is cold data,

Wherein the memory management circuitry is to record the data distribution number for each of the plurality of logical address groups, the operation of the memory management circuitry to record the data distribution number for each of the plurality of logical address groups comprising:

The memory management circuit is also configured to sum up a value of a write flag of at least one physical erase unit writing data belonging to each of the plurality of logical address groups as the data distribution number of each of the plurality of logical address groups.

10. The memory control circuit unit of claim 9, wherein,

The memory management circuit is also used for recording the data writing time stamp of each of the plurality of physical erasing units, and

The memory management circuit is further configured to identify that the data of the physical erase unit belonging to the first logical address group is the first type data if the data distribution number of the first logical address group is less than a data distribution threshold and the data write time stamp of at least one physical erase unit of the plurality of physical erase units to which the data belonging to the first logical address group is written is less than a time stamp threshold.

11. The memory control circuit unit of claim 9, wherein,

The memory management circuit is further configured to set a data distribution number of each of the plurality of logical address groups according to a number of physical erase units writing data belonging to each of the plurality of logical address groups,

12. The memory control circuit unit of claim 11, wherein,

The memory management circuit is further configured to establish a bit map of a plurality of logical address groups to record physical erase units for writing data belonging to each of the plurality of logical address groups, wherein each of the plurality of logical address groups has a plurality of write marks and the plurality of write marks respectively correspond to the plurality of physical erase units,

When the data belonging to the corresponding logical address group in the logical address groups is written in the physical erasing units, the memory management circuit is further used for recording the writing mark of at least one physical erasing unit written in the data belonging to the corresponding logical address group as 1.

13. The memory control circuit unit of claim 12, wherein,

In the logical address group bit map, the memory management circuit is further configured to sort write marks belonging to each of the plurality of logical address groups and corresponding to the plurality of physical erase units on a first axis according to data distribution numbers of each of the plurality of logical address groups, and

The memory management circuit is further configured to sort write marks belonging to each of the plurality of logical address groups and corresponding to the plurality of physical erase units on a second axis according to data write time stamps of the plurality of physical erase units.

14. The memory control circuit unit of claim 13, wherein,

If the data belonging to the first logical address group is identified as the first type data, the memory management circuit is further configured to extract a target physical erase unit from the idle area, and move the data belonging to the first logical address group from the at least one physical erase unit to the target physical erase unit.

15. A memory storage device, comprising:

The connection interface unit is used for being electrically connected to the host system;

A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical erase units; and

A memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module,

Wherein the memory control circuit unit is used for configuring a plurality of logic addresses to be mapped to a plurality of physical programming units of the plurality of physical erasing units,

Wherein the memory control circuit unit is configured to group the plurality of logical addresses into a plurality of logical address groups,

Wherein the memory control circuit unit is used for respectively receiving a plurality of write instructions and a plurality of data to be stored to the plurality of logic addresses from the host system,

Wherein the memory control circuit unit is used for writing the data into the physical programming units of the physical erasing units respectively,

Wherein the memory control circuit unit is used for identifying the data of the entity erasing units of the first logic address group in the plurality of logic address groups as first type data according to the data writing time stamp of each entity erasing unit and the data distribution number of the entity erasing units in each logic address group, the first type data is cold data,

Wherein the memory control circuit unit is configured to record the data distribution number of each of the plurality of logical address groups, the operation of the memory control circuit unit to record the data distribution number of each of the plurality of logical address groups comprises:

The memory control circuit unit is also used for summing the value of the write mark of at least one entity erasing unit for writing the data belonging to each of the plurality of logic address groups as the data distribution number of each of the plurality of logic address groups.

16. The memory storage device of claim 15, further comprising:

wherein the memory control circuit unit is further configured to record a data write time stamp of each of the plurality of physical erase units,

The memory control circuit unit is further configured to identify that the data belonging to the first logical address group is the first type of data if the data distribution number of the first logical address group is less than a data distribution threshold and the data write timestamp of at least one physical erase unit of the plurality of physical erase units to which the data belonging to the first logical address group is written is less than a timestamp threshold.

17. The memory storage device of claim 15, further comprising:

The memory control circuit unit is further configured to set a data distribution number of each of the plurality of logical address groups according to a number of physical erasing units writing data belonging to each of the plurality of logical address groups,

18. The memory storage device of claim 17, further comprising:

The memory control circuit unit is further configured to establish a logical address group bit map to record physical erase units for writing data belonging to each of the plurality of logical address groups, wherein each of the plurality of logical address groups has a plurality of write marks and the plurality of write marks respectively correspond to the plurality of physical erase units,

When the data belonging to the corresponding logical address group in the logical address groups is written in the physical erasing units, the memory control circuit unit is further configured to record the writing mark of at least one physical erasing unit written with the data belonging to the corresponding logical address group as 1.

19. The memory storage device of claim 18, further comprising:

in the logical address group bit map, the memory control circuit unit is further configured to sort write marks belonging to each of the plurality of logical address groups and corresponding to the plurality of physical erase units on a first axis according to the data distribution number of each of the plurality of logical address groups, and

The memory control circuit unit is further configured to sort write marks belonging to each of the plurality of logical address groups and corresponding to the plurality of physical erase units on a second axis according to data write time stamps of the plurality of physical erase units.

20. The memory storage device of claim 19, further comprising:

if the data belonging to the first logical address group is identified as the first type data, the memory control circuit unit is further configured to extract a target physical erase unit from the idle area, and move the data belonging to the first logical address group from the at least one physical erase unit to the target physical erase unit.