CN110109848B - DSP hardware abstraction layer and DSP processor - Google Patents
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Abstract
The application relates to a DSP hardware abstraction layer and a DSP processor, wherein the DSP hardware abstraction layer comprises an initialization module, a parameter configuration module, a data receiving and sending module and a message routing distribution module, the parameter configuration module acquires an LD-PD mapping parameter and an LD-callback function mapping parameter in the hardware abstraction layer according to a waveform scheme corresponding to an external DSP waveform component, the data receiving and sending module provides a standard data receiving and sending interface for the external DSP waveform component to coordinate and manage the data receiving and sending process of the whole DSP hardware abstraction layer, and the message routing distribution module encapsulates a hardware abstraction layer message and carries out routing distribution on the hardware abstraction layer message according to a built-in LD-PD mapping table and a built-in LD-callback function mapping table. The whole DSP hardware abstraction layer is provided with a uniform interface interacting with the external DSP waveform components, supports communication among different DSP waveform components, and can remarkably improve the portability of the DSP waveform components.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a DSP (Digital Signal Processing) hardware abstraction layer and a DSP processor.
Background
With the rapid development of wireless communication technology, software radio technology is mature day by day and is widely applied to the fields of military communication, personal mobile communication and the like, a software radio system mainly comprises a standardized, generalized and modularized general hardware platform and a software platform, and the core idea is to realize various wireless communication functions by loading software modules with different functions on the general hardware platform.
DSPs have now become an important component in wireless communications. In wireless communication, the bottom layer interface driver of the DSP processor has large difference and complexity, and for different bottom layer interface drivers and DSP waveform components, a user-defined communication interface is adopted for data communication between the two components, so that the DSP waveform component has the problem of poor portability.
Disclosure of Invention
Therefore, it is necessary to provide a new DSP hardware abstraction layer and a new DSP processor to significantly improve the portability of the DSP waveform component.
A DSP hardware abstraction layer comprises an initialization module, a parameter configuration module, a data receiving and transmitting module and a message routing distribution module;
the initialization module is used for initializing hardware drive and initializing the inside of a hardware abstraction layer;
the parameter configuration module is used for acquiring configuration parameters of a hardware abstraction layer according to a waveform scheme corresponding to an external DSP waveform component, and the configuration parameters comprise LD-PD mapping parameters and LD-callback function mapping parameters;
the data transceiver module is used for providing a standard data transceiver interface for the external DSP waveform component;
the message routing distribution module is used for packaging hardware abstraction layer messages and performing routing distribution on the hardware abstraction layer messages according to a built-in LD-PD mapping table and an LD-callback function mapping table, wherein the LD-PD mapping table is configured by the LD-PD mapping parameters, and the LD-callback function mapping table is configured by the LD-callback function mapping parameters.
In one embodiment, an mhalInit function used for calling the external DSP waveform component is built in the initialization module, and the initialization module is further configured to initialize a bottom hardware interface in the DSP and create a monitoring thread and a related synchronous semaphore inside a DSP hardware abstraction layer, so as to receive a hardware abstraction layer message driven by bottom hardware in the DSP.
In one embodiment, the parameter configuration module is internally provided with a configLDMap function and a registerlockld function, and the external DSP waveform component calls the configLDMap function and the registerlockld function and writes the LD-PD mapping parameters and the LD-callback function mapping parameters.
In one embodiment, the parameter configuration module is further configured to call a configLDMap function to read waveform design scheme data written in the external DSP waveform component, obtain a parameter LD value and a parameter PD value, determine whether there is an LD-PD mapping parameter corresponding to the parameter LD value, update the parameter LD value and the parameter PD value to the LD-PD mapping parameter if yes, add an entry for storing the parameter LD value and the parameter PD value if no, and update an added entry to the LD-PD mapping parameter.
In one embodiment, the parameter configuration module is further configured to call a configLDMap function to read waveform design scheme data written in the external DSP waveform component, call the register localld function to obtain a parameter LD value and a callback function, determine whether there is an LD-callback function mapping parameter corresponding to the parameter LD value, if so, update the parameter LD value and the callback function to the LD-callback function mapping parameter, otherwise, add an entry for storing the parameter LD value and the callback function, and update the added entry to the LD-callback function mapping parameter.
In one embodiment, the data transceiver module calls a built-in mhalWrite function to obtain parameters transmitted by the external DSP waveform component, where the transmitted parameters include a message to be transmitted and a logical address of a destination component, and the data transceiver module transmits the transmitted parameters to the message routing and distribution module; the message routing distribution module inquires a built-in LD-PD mapping table, judges whether a PD corresponding to the logic address of the target component exists in the LD-PD mapping table, if so, writes the message to be sent into the corresponding PD, if not, inquires a built-in LD-callback function mapping table, and calls the corresponding callback function to send the message to be sent when the callback function corresponding to the logic address of the target component exists in the LD-callback function mapping table.
In one embodiment, the data transceiver module is further configured to perform validity verification on the incoming parameter, and when the verification is passed, send the incoming parameter to the message route analysis module; the message routing distribution module is also used for carrying out hardware abstraction layer encapsulation on the transmitted parameters.
In one embodiment, the message routing and distributing module is configured to receive a hardware abstraction layer message, parse the hardware abstraction layer message, extract logical address information and data, query a built-in LD-callback function mapping table, determine whether a function corresponding to the extracted logical address information exists in the LD-callback function mapping table, call the callback function to send the data if the function exists, query the built-in LD-PD mapping table if the function does not exist, and write the data into the corresponding PD when a PD corresponding to the extracted logical address information exists in the LD-PD mapping table.
In one embodiment, the initialization module is further configured to create a monitoring thread inside a DSP hardware abstraction layer, read a packet header when data is read through the monitoring thread, determine a length of a hardware abstraction layer packet, read a complete hardware abstraction layer packet according to the length of the hardware abstraction layer packet, and send the complete hardware abstraction layer packet to the packet routing distribution module.
The DSP hardware abstraction layer comprises an initialization module, a parameter configuration module, a data receiving and sending module and a message routing distribution module, wherein the initialization module is used for hardware drive initialization and hardware abstraction layer internal initialization; the parameter configuration module acquires LD-PD mapping parameters and LD-callback function mapping parameters in a hardware abstraction layer according to a waveform scheme corresponding to an external DSP waveform component, the data transceiving module provides a standard data transceiving interface for the external DSP waveform component to coordinate and manage the data transceiving process of the whole DSP hardware abstraction layer, and the message routing distribution module encapsulates a hardware abstraction layer message and performs routing distribution on the hardware abstraction layer message according to a built-in LD-PD mapping table and an LD-callback function mapping table. The whole DSP hardware abstraction layer is provided with a uniform interface interacting with an external DSP waveform component, accurate receiving and sending of messages of the hardware abstraction layer can be achieved based on an LD-PD mapping table and an LD-callback function mapping table, communication among different DSP waveform components is supported, and transportability of the DSP waveform components can be remarkably improved.
In addition, this application still provides a DSP treater, including DSP waveform component DSP hardware abstraction layer and bottom hardware drive, DSP waveform component with DSP hardware abstraction layer is connected, DSP hardware abstraction layer with bottom hardware drive is connected.
The DSP processor comprises a DSP waveform component, a DSP hardware abstraction layer and a bottom hardware driver, wherein the hardware abstraction layer is provided with a uniform interface interacting with an external DSP waveform component, can realize accurate receiving and sending of messages of the hardware abstraction layer based on an LD-PD mapping table and an LD-callback function mapping table, and supports communication among different DSP waveform components.
Drawings
FIG. 1 is a diagram illustrating a comparison of application scenarios of a conventional DSP hardware abstraction layer and a DSP hardware abstraction layer of the present application;
FIG. 2 is a diagram illustrating an embodiment of a DSP hardware abstraction layer architecture;
FIG. 3 is a flow diagram that illustrates the processing of the parameter configuration module in one embodiment;
FIG. 4 is a diagram illustrating an embodiment of a process for sending messages in a DSP hardware abstraction layer;
fig. 5 is a schematic diagram illustrating a message receiving process of a DSP hardware abstraction layer according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
To further elaborate the technical solution and effect of the DSP hardware abstraction layer of the present application, some conventional techniques in the art will be described below.
Conventional DSP waveform component interaction in the art as shown on the left side of fig. 1, waveform component 1 and waveform component 2 communicate through a custom interface between the two that is only applicable to waveform component 1 and waveform component 2, and cannot support communication when replaced with other waveform components. As shown in the right side of fig. 1, the DSP hardware abstraction layer of the present application provides a uniform and standard interface for data interaction with waveform components, provides a routing function, supports communication between different waveform components, and significantly improves the portability of the DSP waveform components.
As shown in fig. 2, the present application specifically provides a hardware abstraction layer of a DSP, which includes an initialization module 100, a parameter configuration module 200, a data transceiver module 300, and a message routing distribution module 400.
The initialization module 100 is configured to perform hardware driver initialization and hardware abstraction layer internal initialization; the parameter configuration module 200 is configured to obtain configuration parameters of a hardware abstraction layer according to a waveform scheme corresponding to an external DSP waveform component, where the configuration parameters include LD-PD mapping parameters and LD-callback function mapping parameters; the data transceiver module 300 is used for providing a standard data transceiver interface for an external DSP waveform component; the message routing and distributing module 400 is configured to encapsulate the hardware abstraction layer message and perform routing and distribution on the hardware abstraction layer message according to a built-in LD-PD mapping table configured by LD-PD mapping parameters and an LD-callback function mapping table configured by LD-callback function mapping parameters.
The initialization module 100, as a supporting module, is not directly connected to other modules, and the process of performing hardware driver initialization and hardware abstraction layer internal initialization specifically includes: and externally providing an mhalInit function for calling the waveform component, initializing a hardware driver for initializing a bottom layer transmission hardware interface, and establishing a monitoring thread and related synchronous semaphore inside a DSP hardware abstraction layer for internal initialization of the hardware abstraction layer, wherein the internal initialization of the hardware abstraction layer is used for receiving a hardware abstraction layer message from the bottom layer driver.
The parameter configuration module 200 is connected to the external DSP waveform component and the message route distribution module 400, and receives the waveform scheme written by the external DSP waveform component, and obtains data including LD-PD mapping parameters and LD-callback function mapping parameters from the waveform scheme through a built-in function, and updates and writes the obtained LD-PD mapping parameters and LD-callback function mapping parameters into the message route distribution module 400. Specifically, the parameter configuration module 200 is configured to flexibly configure hardware abstraction layer parameters, which mainly include LD-PD mapping parameters and LD-callback function mapping parameters. In practical application, the parameter configuration module 200 provides a configLDMap function and a registerlockld function to the outside, and the DSP waveform component calls the configLDMap function and the registerlockld function respectively according to the current running waveform scheme to implement writing and configuration of the LD-PD mapping parameters and the LD-callback function mapping table parameters.
The data transceiver module 300 is connected to the DSP waveform component and the message data transceiver module 300, and functions to provide a standard interface for data transceiving to the DSP waveform component, thereby shielding a specific data transmission process. Specifically, the data transceiver module 300 may have an mhalWrite function built therein, and when the DSP waveform component needs to send data, the DSP waveform component only needs to call the mhalWrite function and transfer specified parameters to complete the data sending function; meanwhile, when the hardware abstraction layer receives the external component data, the function of receiving the data can be completed only by calling the corresponding callback function.
The message routing and distributing module 400 is connected with the parameter configuration module 200, the data transceiver module 300 and the bottom hardware driver in the DSP. The message routing and distributing module 400 mainly implements hardware abstraction layer message encapsulation and is internally maintained with an LD-PD mapping table and an LD-callback function mapping table, thereby implementing a routing and distributing function of the hardware abstraction layer message.
The above mentioned 4 functions are further explained here. The 4 functions include a mhalInit function, a mhalWrite function, a configLDMap function, and a register locald function. mhalInit function: the function completes the basic initialization function of the hardware abstraction layer, the syntax of the function adopts int mhalInit (), no parameter exists, the mark is failed when the return value is-1, and the success is represented when the return value is 0. mhalWrite function: the function is called by an upper waveform component to realize the data sending function of a DSP hardware abstraction layer, the syntax of the function is void mhalWrite (signed short remote, MhalByte msgBuf), and the function comprises a remote logical address, a destination component logical address and msgBuf: storing address parameters of data to be sent without return values; configLDMap function: this function maps logical addresses to waveform shared memory, and the waveform component knows which part of the memory map is allocated to the waveform, with the syntax of void-configured ldmap (signaled short moved, signaled int moved pd), including moved: remote component logical address and remotePD: the shared memory address corresponding to the remote component has no return value; register LocalLD function: this function maps the logical address of the local waveform component to a callback function, and registers this mapping relationship to the hardware abstraction layer, which syntax is void register locald (signed short locald, mhalfenptr callbackFnx), including locald: and the local component logical address and the callback Fnx are callback function pointer parameters corresponding to the local component logical address and have no return value.
The DSP hardware abstraction layer includes an initialization module 100, a parameter configuration module 200, a data transceiver module 300, and a message routing distribution module 400, where the initialization module 100 performs hardware driver initialization and hardware abstraction layer internal initialization; the parameter configuration module 200 obtains LD-PD mapping parameters and LD-callback function mapping parameters in the hardware abstraction layer according to a waveform scheme corresponding to an external DSP waveform component, the data transceiving module 300 provides a standard data transceiving interface for the external DSP waveform component to coordinate and manage the whole data transceiving process of the DSP hardware abstraction layer, and the message routing distribution module 400 encapsulates a hardware abstraction layer message and performs routing distribution of the hardware abstraction layer message according to a built-in LD-PD mapping table and a LD-callback function mapping table. The whole DSP hardware abstraction layer is provided with a uniform interface interacting with an external DSP waveform component, accurate receiving and sending of messages of the hardware abstraction layer can be achieved based on an LD-PD mapping table and an LD-callback function mapping table, communication among different DSP waveform components is supported, and transportability of the DSP waveform components can be remarkably improved.
In one embodiment, the parameter configuration module 200 is further configured to call a configLDMap function to read waveform design scheme data written in an external DSP waveform component, obtain a parameter LD value and a parameter PD value, determine whether there is an LD-PD mapping parameter corresponding to the parameter LD value, if yes, update the parameter LD value and the parameter PD value to the LD-PD mapping parameter, if no, add an entry for storing the parameter LD value and the parameter PD value, and update the added entry to the LD-PD mapping parameter.
Fig. 3 is a process of configuring parameters of a DSP hardware abstraction layer by a parameter configuration module 200, where the parameters refer to additional information required by the hardware abstraction layer to complete one data transmission, such as LD values and PD values, a waveform component developer determines multiple LD values and PD values and their corresponding relationships in advance according to a waveform design scheme, the parameter configuration module 200 calls a configLDMap interface to read parameter LD values and parameter PD values in waveform design scheme data written by the DSP waveform component, determines whether there is an LD-PD mapping parameter corresponding to the parameter LD value in a history record, and if so, indicates that only a mapping table entry needs to be updated currently, updating the LD value and PD value of the parameter to the LD-PD mapping parameter, if not, indicating that a mapping table item needs to be added at present, then, the table entry for storing the parameter LD value and the parameter PD value is newly added, and the newly added table entry is updated to the LD-PD mapping parameter. The parameter configuration module 200 imports the updated LD-PD mapping parameter into the message routing distribution module 400, so as to update the LD-PD mapping table in the message routing distribution module 400. It should be noted that the updated LD-PD mapping parameter may be directly a complete LD-PD mapping table, and the parameter configuration module 200 directly replaces the original LD-PD mapping table in the message routing distribution module 400 with the complete LD-PD mapping table, so as to implement parameter configuration.
In one embodiment, the parameter configuration module 200 is further configured to call a configLDMap function to read waveform design scheme data written in by an external DSP waveform component, call a register locald function to obtain a parameter LD value and a callback function, determine whether there is an LD-callback function mapping parameter corresponding to the parameter LD value, if so, update the parameter LD value and the callback function to the LD-callback function mapping parameter, otherwise, newly add an entry for storing the parameter LD value and the callback function, and update the newly added entry to the LD-callback function mapping parameter.
The updating of the LD-callback function mapping parameters and the corresponding updating to the LD-callback function mapping table in the packet routing and distributing module 400 are similar to the processing of the LD-PD mapping table, and are not described herein again.
In one embodiment, the data transceiver module 300 calls a built-in mhalWrite function to obtain parameters transmitted by an external DSP waveform component, where the transmitted parameters include a message to be transmitted and a logical address of a target component, and the data transceiver module 300 transmits the transmitted parameters to the message route distribution module 400; the message routing and distributing module 400 queries the built-in LD-PD mapping table, determines whether there is a PD corresponding to the logical address of the destination component in the LD-PD mapping table, if so, writes the message to be sent into the corresponding PD, if not, queries the built-in LD-callback function mapping table, and calls the corresponding callback function to send the message to be sent when there is a callback function corresponding to the logical address of the destination component in the LD-callback function mapping table.
The process of sending a message by a DSP hardware abstraction layer is specifically shown in fig. 4, a mhalWrite function is built in a data transceiving module 300, a parameter transmitted by an external DSP waveform component is obtained, the parameter includes a message to be sent and a logical address of a destination component, the data transceiving module 300 sends the transmitted parameter to a message routing distribution module 400, the message routing distribution module 400 can perform a hardware abstraction layer message encapsulation operation, the message routing distribution module 400 firstly queries a built-in LD-PD mapping table, determines whether a PD corresponding to the logical address of the destination component exists, if so, it indicates that the message to be sent is sent to a remote waveform component, calls a drive write interface in a DSP bottom layer hardware drive to write the message to be sent into the corresponding PD, if not, it continues to query the built-in LD-PD-function mapping table, determines whether a callback function corresponding to the logical address of the destination component exists, if the message to be sent is sent to the local component, the corresponding callback function can be directly called to send the message to be sent to the local component, if the message to be sent is not sent to the local component, the query is not successful for two times, the message to be sent is indicated to be an invalid message, and the message to be sent is discarded.
In one embodiment, the data transceiver module 300 is further configured to perform validity verification on the incoming parameters, and when the verification is passed, send the incoming parameters to the message route analysis module; the message routing distribution module 400 is further configured to perform hardware abstraction layer encapsulation on the incoming parameters.
In this embodiment, the data transceiver module 300 further performs validity verification to ensure that the valid data enters subsequent processing.
In one embodiment, the message routing and distributing module 400 is configured to receive a hardware abstraction layer message, analyze the hardware abstraction layer message, extract logical address information and data, query a built-in LD-callback function mapping table, determine whether a function corresponding to the extracted logical address information exists in the LD-callback function mapping table, call the callback function to send data if the function exists, query the built-in LD-PD mapping table if the function does not exist, and write the data into a corresponding PD when the PD corresponding to the extracted logical address information exists in the LD-PD mapping table.
In one embodiment, the initialization module 100 is further configured to create a monitoring thread inside the DSP hardware abstraction layer, and when data is read through the monitoring thread, read a packet header, determine the length of the hardware abstraction layer packet, read a complete hardware abstraction layer packet according to the length of the hardware abstraction layer packet, and send the complete hardware abstraction layer packet to the packet routing distribution module 400.
As shown in fig. 5, in the process of receiving a message at a hardware abstraction layer of a DSP in fig. 5, the initialization module 100 creates a monitoring thread (see fig. 2), when data is read through the monitoring thread, first reads a header of the message at the hardware abstraction layer, determines a length of the message at the hardware abstraction layer, reads a complete message at the hardware abstraction layer according to the length of the message at the hardware abstraction layer, and sends the complete message at the hardware abstraction layer to the message routing distribution module 400. The message routing and distributing module 400 parses the message at the hardware abstraction layer, extracts the LD information and data of the logical address, queries the built-in LD-callback function mapping table, determines whether a function corresponding to the extracted logical address information exists in the LD-callback function mapping table, if so, indicates that the data is sent to the local component, calls the callback function to send the data to the local component, if not, queries the built-in LD-PD mapping table, determines whether a PD corresponding to the extracted logical address information exists in the LD-PD mapping table, if so, indicates that the message is a message that needs the DSP hardware abstraction layer to forward to other processors, directly writes a physical address corresponding to the PD, and if not, indicates that the received message is invalid, and discards the received message.
In addition, the application also provides a DSP processor, which comprises a DSP waveform component, a DSP hardware abstraction layer and a bottom hardware driver, wherein the DSP waveform component is connected with the DSP hardware abstraction layer, and the DSP hardware abstraction layer is connected with the bottom hardware driver.
The DSP processor comprises a DSP waveform component, a DSP hardware abstraction layer and a bottom hardware driver, wherein the hardware abstraction layer is provided with a uniform interface interacting with an external DSP waveform component, can realize accurate receiving and sending of messages of the hardware abstraction layer based on an LD-PD mapping table and an LD-callback function mapping table, and supports communication among different DSP waveform components.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (7)
1. A system containing a DSP hardware abstraction layer is characterized by comprising an initialization module, a parameter configuration module, a data receiving and sending module and a message routing distribution module;
the initialization module is used for initializing hardware drive and initializing the inside of a hardware abstraction layer;
the parameter configuration module is used for acquiring configuration parameters of a hardware abstraction layer according to a waveform scheme corresponding to an external DSP waveform component, and the configuration parameters comprise LD-PD mapping parameters and LD-callback function mapping parameters;
the data transceiver module is used for providing a standard data transceiver interface for the external DSP waveform component;
the message routing distribution module is used for packaging a hardware abstraction layer message and carrying out routing distribution on the hardware abstraction layer message according to a built-in LD-PD mapping table and an LD-callback function mapping table, wherein the LD-PD mapping table is configured by the LD-PD mapping parameters, and the LD-callback function mapping table is configured by the LD-callback function mapping parameters; the initialization module is internally provided with an mhalInit function used for calling the external DSP waveform component, and is also used for initializing a bottom hardware interface in the DSP and creating a monitoring thread and related synchronous semaphore inside a DSP hardware abstraction layer so as to receive a hardware abstraction layer message driven by bottom hardware in the DSP; the initialization module is not directly connected with the parameter configuration module, the data receiving and transmitting module and the message routing distribution module; the parameter configuration module is internally provided with a configLDMap function and a register LocalLD function, and the external DSP waveform component calls the configLDMap function and the register LocalLD function and writes the LD-PD mapping parameters and the LD-callback function mapping parameters;
the message routing and distributing module is used for receiving a hardware abstraction layer message, analyzing the hardware abstraction layer message, extracting logic address information and data, inquiring a built-in LD-callback function mapping table, judging whether a function corresponding to the extracted logic address information exists in the LD-callback function mapping table or not, if so, calling the callback function to send the data, otherwise, inquiring the built-in LD-PD mapping table, and writing the data into the corresponding PD when the PD corresponding to the extracted logic address information exists in the LD-PD mapping table.
2. The system of claim 1, wherein the parameter configuration module is further configured to call a configLDMap function to read waveform design scheme data written in the external DSP waveform component, obtain a parameter LD value and a parameter PD value, determine whether there is an LD-PD mapping parameter corresponding to the parameter LD value, if yes, update the parameter LD value and the parameter PD value to the LD-PD mapping parameter, if no, add an entry for storing the parameter LD value and the parameter PD value, and update a newly added entry to the LD-PD mapping parameter.
3. The system according to claim 1, wherein the parameter configuration module is further configured to call a configLDMap function to read waveform design scheme data written in the external DSP waveform component, call the register localld function to obtain a parameter LD value and a callback function, determine whether there is an LD-callback function mapping parameter corresponding to the parameter LD value, if so, update the parameter LD value and the callback function to the LD-callback function mapping parameter, if not, add an entry for storing the parameter LD value and the callback function, and update an added entry to the LD-callback function mapping parameter.
4. The system according to claim 1, wherein the data transceiver module calls a built-in mhalWrite function to obtain incoming parameters of the external DSP waveform component, where the incoming parameters include a message to be sent and a logical address of a destination component, and the data transceiver module sends the incoming parameters to the message routing and distribution module; the message routing distribution module inquires a built-in LD-PD mapping table, judges whether a PD corresponding to the logic address of the target component exists in the LD-PD mapping table, if so, writes the message to be sent into the corresponding PD, if not, inquires a built-in LD-callback function mapping table, and calls the corresponding callback function to send the message to be sent when the callback function corresponding to the logic address of the target component exists in the LD-callback function mapping table.
5. The system according to claim 4, wherein the data transceiver module is further configured to validate the incoming parameters, and when validation is passed, send the incoming parameters to the message route analysis module; the message routing distribution module is also used for carrying out hardware abstraction layer encapsulation on the transmitted parameters.
6. The system according to claim 1, wherein the initialization module is further configured to create a monitoring thread inside a DSP hardware abstraction system, and when data is read through the monitoring thread, read a packet header, determine a length of a hardware abstraction layer packet, read a complete hardware abstraction layer packet according to the length of the hardware abstraction layer packet, and send the complete hardware abstraction layer packet to the packet routing distribution module.
7. A DSP processor comprising a DSP waveform component, the system comprising a DSP hardware abstraction layer of any one of claims 1-6 above, and an underlying hardware driver, the DSP waveform component being coupled to the system comprising the DSP hardware abstraction layer, the system comprising the DSP hardware abstraction layer being coupled to the underlying hardware driver.
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| CN108984324B (en) * | 2018-07-18 | 2021-05-11 | 湖南理工学院 | FPGA hardware abstraction layer |
| CN109558367B (en) * | 2019-01-10 | 2022-10-28 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Multi-bus processor MHAL routing method |
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