CN106887483A - Silicon substrate heterojunction solar cell and preparation method thereof - Google Patents
Silicon substrate heterojunction solar cell and preparation method thereof Download PDFInfo
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- CN106887483A CN106887483A CN201510931989.2A CN201510931989A CN106887483A CN 106887483 A CN106887483 A CN 106887483A CN 201510931989 A CN201510931989 A CN 201510931989A CN 106887483 A CN106887483 A CN 106887483A
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- 239000000758 substrate Substances 0.000 title claims abstract description 109
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 77
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 77
- 239000010703 silicon Substances 0.000 title claims abstract description 77
- 238000002360 preparation method Methods 0.000 title claims abstract description 51
- 238000000576 coating method Methods 0.000 claims abstract description 175
- 239000011248 coating agent Substances 0.000 claims abstract description 169
- 238000010891 electric arc Methods 0.000 claims abstract description 34
- 239000004065 semiconductor Substances 0.000 claims description 93
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 86
- 239000011787 zinc oxide Substances 0.000 claims description 43
- 239000001257 hydrogen Substances 0.000 claims description 36
- 229910052739 hydrogen Inorganic materials 0.000 claims description 33
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 29
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 28
- 229910003437 indium oxide Inorganic materials 0.000 claims description 27
- 238000007747 plating Methods 0.000 claims description 18
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 14
- 230000003746 surface roughness Effects 0.000 claims description 12
- 239000011701 zinc Substances 0.000 claims description 12
- 229910052796 boron Inorganic materials 0.000 claims description 11
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 9
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052733 gallium Inorganic materials 0.000 claims description 7
- 229910052725 zinc Inorganic materials 0.000 claims description 6
- 230000008021 deposition Effects 0.000 abstract description 19
- 230000009466 transformation Effects 0.000 abstract description 8
- 239000007789 gas Substances 0.000 description 47
- 229910021417 amorphous silicon Inorganic materials 0.000 description 39
- 239000000463 material Substances 0.000 description 27
- 238000000151 deposition Methods 0.000 description 24
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 20
- 229910000077 silane Inorganic materials 0.000 description 20
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 18
- 239000000126 substance Substances 0.000 description 15
- 230000000694 effects Effects 0.000 description 14
- 239000000203 mixture Substances 0.000 description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 11
- 239000001301 oxygen Substances 0.000 description 11
- 229910052760 oxygen Inorganic materials 0.000 description 11
- 125000004429 atom Chemical group 0.000 description 10
- 239000010408 film Substances 0.000 description 10
- 229910052786 argon Inorganic materials 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 9
- 229910021419 crystalline silicon Inorganic materials 0.000 description 9
- 238000000034 method Methods 0.000 description 9
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 9
- 238000004062 sedimentation Methods 0.000 description 9
- 238000004050 hot filament vapor deposition Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000004544 sputter deposition Methods 0.000 description 8
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 8
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 229910052709 silver Inorganic materials 0.000 description 6
- 239000004332 silver Substances 0.000 description 6
- 229910001887 tin oxide Inorganic materials 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 239000002159 nanocrystal Substances 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 229910000078 germane Inorganic materials 0.000 description 4
- -1 hydrogen Chemical class 0.000 description 4
- 150000002431 hydrogen Chemical class 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 150000003377 silicon compounds Chemical class 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 239000007790 solid phase Substances 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000010494 dissociation reaction Methods 0.000 description 2
- 230000005593 dissociations Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000010248 power generation Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- FMRLDPWIRHBCCC-UHFFFAOYSA-L Zinc carbonate Chemical compound [Zn+2].[O-]C([O-])=O FMRLDPWIRHBCCC-UHFFFAOYSA-L 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000013081 microcrystal Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000000746 purification Methods 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H01L31/072—
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- H01L31/022425—
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- H01L31/022466—
-
- H01L31/028—
-
- H01L31/0747—
-
- H01L31/1804—
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Life Sciences & Earth Sciences (AREA)
- Engineering & Computer Science (AREA)
- Sustainable Energy (AREA)
- Sustainable Development (AREA)
- Photovoltaic Devices (AREA)
Abstract
The present invention discloses a kind of silicon substrate heterojunction solar cell and preparation method thereof.The silicon substrate heterojunction solar cell, including：One silicon substrate PN contact structures, one first nesa coating, one second nesa coating, a first electrode and a second electrode.By DC arc discharge high speed deposition nesa coating at low temperature, the silicon substrate heterojunction solar cell has the characteristic for improving its current characteristics and lifting photoelectric transformation efficiency to the present invention.
Description
Technical field
The present invention on a kind of silicon substrate heterojunction solar cell and preparation method thereof, particularly with regard to a kind of silicon substrate heterojunction solar cell with DC arc discharge deposition of transparent conductive film and preparation method thereof.
Background technology
At present due to international energy shortage, and countries in the world are continued for the various feasible alternative energy sources of research and development, and are wherein most attracted attention with the solar cell of solar power generation.At present, the conversion efficiency of the solar cell made with silicon wafer, loss caused by limitation, the reflected light of its solar energy for being only capable of absorbing more than 1.1 electron-volts, material is not enough to the absorbability of sunshine, carrier is just being failed before being not yet exported by the defect seizure in material, or carrier is subject to the suspension bond seizure of material surface to produce the factors such as compound, all declines its efficiency.Therefore, the conversion efficiency of currently marketed silicon wafer solar cell only about 15%, that is, represent that the high efficiency of silicon wafer solar cell also has sizable space in fact.Wherein, the general principle of solar cell high efficiency is exactly the electric layer material for combining different energy gaps, and they are made laminated construction.
Reference U.S. Publication patent the 5th, 213,628, it is entitled：Photovoltaic module
(Photovoltaic device), it mainly discloses a kind of solar cell of combination difference energy gap, by non-crystalline silicon extrinsic semiconductor is added, increases the carrier life-span of solar cell, reduces the compound probability of electronics electricity hole, improves photoelectric current conversion efficiency.
Reference U.S. Publication patent the 6th, 878,921, it is entitled：Photovoltaic module and its preparation method (Photovoltaic device and manufacturing method thereof).As shown in figure 1, it mainly discloses a kind of silicon substrate heterojunction solar cell, indium tin oxide (In2O3 is used:SnO2, ITO) nesa coating as current spreading layer, to lift the characteristic of its current characteristics and lifting photoelectric transformation efficiency.
Reference U.S. Publication patent the 7th, 164,150, it is entitled：Photovoltaic module and preparation method thereof (Photovoltaic device and manufacturing method thereof), its structure and preparation method for mainly disclosing a kind of solar cell.The battery configures a nesa coating between back electrode and photoelectric conversion layer, so that incident light carries out remaking use in being reflected back photoelectric conversion layer, so as to improving current characteristics and increasing the overall photoelectric transformation efficiency of battery.
Reference U.S. Publication patent the 7th, 601,558, it is entitled：Zinc oxide transparent electrode (Transparent zinc oxide electrode having a graded oxygen content) with progressive oxygen content, it mainly discloses a kind of preparation method of solar cell.It utilizes sputtering method depositing zinc oxide nesa coating, by the thickness for improving nesa coating come the veining in the face of improving, the refractive index so as to lifting incident light, and then increases the overall photoelectric transformation efficiency of battery.
Reference U.S. Publication patent the 8th, 513,044, it is entitled：Preparation method (the Method for the manufacturing of thin film photovoltaic converter of film photovoltaic conversion unit
Device), it mainly discloses a kind of solar cell structure and preparation method.It utilizes sputtering method depositing zinc oxide nesa coating, recycling dilute HF acid solution or ion-etching makes nesa coating form texture structure, increase the conduct length of incident light whereby, increase absorbing amount, and then improve the overall photoelectric transformation efficiency of component battery.
For the nesa coating that solar cell is applied, tin indium oxide (ITO) is always mainstay material, but indium ore deposit is rare and expensive also, vulnerable in hydrogen plasma-based, therefore future certainly will will research and develop substitution material.However, the nesa coating that the sputtering method that above-mentioned patent is disclosed is deposited is excessively flat, it is impossible to reach required roughness, texture structure is formed, it is therefore necessary to prepared by the extra etching for carrying out film again, cause to increase the manufacturing cost of solar cell.
Zinc oxide is a potential material of tool, it has the advantages that aboundresources and with low cost, undoped zinc oxide is the electric conductivity and light transmittance for possessing certain level, and strong to the resistance of hydrogen plasma-based, and the zinc oxide of adulterated al is with more the electric conductivity and light transmittance no less than ITO.In sum, it is necessary to propose a kind of silicon substrate heterojunction solar cell to improve above mentioned problem.
The content of the invention
It is a primary object of the present invention to propose a kind of silicon substrate heterojunction solar cell, the surface prepared by DC arc discharge deposition has the nesa coating of rough grain structure, and the overall photoelectric transformation efficiency of battery is improved whereby.
Another object of the present invention is to propose a kind of preparation method of silicon substrate heterojunction solar cell, by the nesa coating with rough grain structure is prepared under the plating rate high with DC arc discharge, the overall photoelectric transformation efficiency of battery is improved whereby.
To reach the main object of the present invention, the present invention provides a kind of silicon substrate heterojunction solar cell, including：
One silicon substrate PN contact structures, with two apparent surfaces, wherein silicon substrate PN contact structures are made up of a p type semiconductor layer with a n type semiconductor layer, and the p type semiconductor layer energy gap be different from the n type semiconductor layer energy gap；
One first nesa coating, is set positioned at a surface of silicon substrate PN contact structures, and its DC arc discharge using plating rate more than 1.5 nm/s is deposited and formed；
One second nesa coating, is set and is located at silicon substrate PN contact structures and relative to another surface of first electrode, and its DC arc discharge using plating rate more than 1.5 nm/s is deposited and formed；
One first electrode, is arranged on first nesa coating, the electric current for taking out silicon substrate PN contact structures；And
One second electrode, is arranged on second nesa coating, the electric current for taking out silicon substrate PN contact structures.
The wherein refractive index of first nesa coating between 1.90 to 1.94, and second nesa coating refractive index between 1.90 to 1.94.
Wherein first nesa coating is selected from zinc oxide, the zinc oxide of doped gallium, the zinc oxide of doping boron, the indium oxide of doping zinc, the indium oxide of doping boron, the indium oxide of doping hydrogen or wherein any two or more combination of adulterated al with second nesa coating.
The wherein crystallite dimension of first nesa coating between 20 nanometers to 30 nanometers, and second nesa coating crystallite dimension between 20 nanometers to 30 nanometers.
The wherein surface roughness of first nesa coating between 3 nanometers to 20 nanometers, and second nesa coating surface roughness between 3 nanometers to 20 nanometers.
To reach another object of the present invention, the present invention also provides a kind of preparation method of silicon substrate heterojunction solar cell, comprises the following steps：
Form a silicon substrate PN contact structures, with two apparent surfaces, wherein silicon substrate PN contact structures are made up of a p type semiconductor layer with a n type semiconductor layer, and the p type semiconductor layer energy gap be different from the n type semiconductor layer energy gap；
One first nesa coating is deposited in a surface of the PN contact structures, it uses plating rate to be more than 1.5
The DC arc discharge deposition of nm/s is formed；
One second nesa coating is deposited in the PN contact structures and relative to another surface of the first electrode, its DC arc discharge using plating rate more than 1.5 nm/s is deposited and formed；And
Formed a first electrode on first nesa coating with formed a second electrode on second nesa coating, the electric current for taking out silicon substrate PN contact structures.
The wherein refractive index of first nesa coating between 1.90 to 1.94, and second nesa coating refractive index between 1.90 to 1.94.
Wherein first nesa coating is selected from zinc oxide, the zinc oxide of doped gallium, the zinc oxide of doping boron, the indium oxide of doping zinc, the indium oxide of doping boron, the indium oxide of doping hydrogen or wherein any two or more combination of adulterated al.
The wherein crystallite dimension of first nesa coating between 20 nanometers to 30 nanometers, and second nesa coating crystallite dimension between 20 nanometers to 30 nanometers.
The wherein surface roughness of first nesa coating between 3 nanometers to 20 nanometers, and second nesa coating surface roughness between 3 nanometers to 20 nanometers.
Present invention has the advantage that：
The present invention prepares nesa coating by DC arc discharge, and it has film forming speed higher is reached less than 200 DEG C in preparation temperature, and surface has good rough grain structure, it is not necessary to again by be used by solar cell by etching program.
Of the invention being technically characterized in that deposit first nesa coating and second nesa coating using DC arc discharge.The volume production for accelerating silicon substrate heterojunction solar cell is reached whereby.Therefore, advantages of the present invention also includes：
The film forming speed of nesa coating is improved, surface has good rough grain structure；
Increase the absorption of light, and most arrive the function of anti-reflecting layer simultaneously, lift output current density, and then improve photoelectric transformation efficiency；
Commercialization volume production speed is provided, volume production preparation cost is reduced.
Brief description of the drawings
Fig. 1 is shown as generalized section in the prior art of silicon substrate heterojunction solar cell；
Fig. 2 is shown as the first embodiment generalized section of heterojunction solar cell of the present invention；
Fig. 3 is shown as the second embodiment generalized section of heterojunction solar cell of the present invention；
Fig. 4 is shown as the 3rd embodiment generalized section of heterojunction solar cell of the present invention；
Fig. 5 is shown as the fourth embodiment generalized section of heterojunction solar cell of the present invention.
In figure：
100 silicon substrate heterojunction solar cells；
110 substrates；
111 first roughened surfaces；
112 second roughened surfaces；
120 first essential amorphous silicon layers；
130 p type semiconductor layers；
140 second intrinsic amorphous silicons layer；
150 n type semiconductor layers；
160 first electrodes；
170 second electrodes；
180 first nesa coatings；
181 undoped nesa coatings；
182 nesa coatings for having doping；
190 second nesa coatings；
191 undoped nesa coatings；
192 nesa coatings for having doping.
Specific embodiment
The invention will be further described with specific embodiment below in conjunction with the accompanying drawings, so that those skilled in the art can be better understood from the present invention and can be practiced, but illustrated embodiment is not as a limitation of the invention.
Referring now to Fig. 2, it is shown as in first embodiment of the invention, a kind of disclosed structure of silicon substrate heterojunction solar cell 100, and it is included：One substrate 110；Semi-conductor layer 130；One first nesa coating 180；One first electrode 160；One second nesa coating 190；And a second electrode 170.
The substrate 110 is selected from one of p-type semiconduction substrate, N-type semiconduction substrate, P-type silicon substrate and N-type silicon substrate.It is preferred that the substrate 110 is selected from N-type semiconduction silicon substrate monocrystal substrate, but do not limit, the substrate 110 is selected from N-type semiconduction III-V monocrystal substrates.
Additionally, substrate of the invention 110 also has one first roughened surface 111 and one second roughened surface 112.In a preferred embodiment, the surface roughness of the first roughened surface 111 and the second roughened surface 112 is between 10 nanometers to 80 nanometers.
Electric conductivity of the electric conductivity of the semiconductor layer 130 relative to the substrate 110.For example, if the substrate 110 is selected from N-type semiconduction substrate, the semiconductor layer
130 electric conductivity is then p type semiconductor layer.
In one embodiment, the electric conductivity of the semiconductor layer 130 is then p type semiconductor layer, is configured on the substrate 110 with N-type semiconduction.In the embodiment of the present invention, the doping concentration of semiconductor layer 130 is between 1018 to 1020 atoms/cms.The semiconductor layer 130 its oxygen content is between 5 × 1018 to 1 × 1017 atoms/cms.Wherein, impurity is added in script material（Impurities）It is used to produce unnecessary electric hole, the semiconductor of most carriers is constituted with electric hole, then referred to as p type semiconductor layer.Example：For silicon or germanium semiconductor, in its extrinsic semiconductor, when mixing the impurity of trivalent atom, that is, it is the function mode of electric current to form unnecessary electric hole, and the electric hole.
Wherein, the preparation of the semiconductor layer 130 can select plasma enhanced type chemical formula vapour deposition and prepare (Plasma-enhanced
Chemical vapor deposition, PECVD), hot filament CVD (Hot-wire
Chemical vapor deposition, HW-CVD) or superfrequency plasma enhanced type chemical formula vapour deposition（Very
high frequency-plasma enhance chemical vapor deposition, VHF-PECVD）Prepare as main preparation method, and be passed through silicon compound（Silicide）Gas such as silane（silane, SH4）And mix hydrogen（Hydrogen, H）, argon gas（Argon,Ar）Deng gas as preparing gas.
The doping way of the semiconductor layer 130 is in the present invention using optional gas doping, thermal diffusion method（Thermal diffusion）, solid phase crystallization（Solid phase
crystalline, SPC）Or excimer laser annealing（Excimer laser anneal, ELA）Deng preparation as main preparation method.Additionally, the semiconductor layer 130 is selected from one of non-crystalline silicon, amorphous silicon germanium, noncrystalline silicon carbide and nanocrystal silicon.
In one embodiment, the electric conductivity of the semiconductor layer 130 is then P-type non-crystalline silicon semiconductor layer, is configured on the substrate 110 with N-type semiconduction monocrystalline silicon, to form a PN contact structures.The first electrode 180, is set positioned at a surface of the PN contact structures；And the second electrode 190, set and be located at the PN contact structures and relative to another surface of the first electrode.
First nesa coating 180, is set positioned at a surface of the PN contact structures, and second nesa coating 190, sets and is located at the PN contact structures and relative to another surface of the first electrode.Referring to the embodiment of Fig. 2, first nesa coating 180 is set positioned at the surface of the semiconductor layer 130, and second nesa coating 190, is set positioned at the surface of the substrate 110 with N-type semiconduction monocrystalline silicon.
The making material of the first nesa coating 180 and the second nesa coating 190 can select indium oxide, tin oxide, zinc oxide, impure indium oxide, impure tin oxide and impure zinc oxide.For example, but not limiting, the zinc oxide (ZnO of adulterated al:Al), zinc oxide (ZnO of doped gallium:Ga), zinc oxide (ZnO of doping boron:B), indium oxide (In of doping zinc2O3:Zn), indium oxide (In of doping boron2O3:B), indium oxide (In of doping hydrogen2O3:H) or its composition.
It is noted that of the invention being technically characterized in that deposit first nesa coating 180 and second nesa coating 190 using DC arc discharge, its plating rate is more than 1.5 nm/s (nm/sec), and preferably plating rate degree is between 1.6 nm/s to 5
Between nm/s；And preparation temperature is less than 200 DEG C, preferably preparation temperature is between 50
DEG C between 150 DEG C.
Between 1.90 to 1.94, thickness can obtain relatively good antireflection effect to the refractive index of first nesa coating 180 between 50nm to 90nm.Between 1.90 to 1.94, thickness can obtain relatively good antireflection effect to the refractive index of second nesa coating 190 between 50nm (nanometer) to 90nm (nanometer).
The crystallite dimension of first nesa coating 180 and second nesa coating 190 can also obtain relatively good antireflection effect between 20 nanometers to 50 nanometers.
The preparation method of the first nesa coating 180 and the second nesa coating 190 can be selected from the preparation of any one of vapour deposition method, sputtering method, galvanoplastic, wet chemical, chemical vapour deposition technique, print process and arc discharge sedimentation, wherein preferably DC arc discharge sedimentation.
DC arc discharge sedimentation its operation principle is hot anode or the DC arc discharge produced by hot cathode, and the current density of this region electrode may be up to 106A/cm2, the DC arc discharge with superelevation dissociation yield can be whereby produced to melt target, therefore the more conventional sputtering method of its deposition velocity is fast, up to hundreds of nanometers per minute.Additionally, when target is subject to the anode arc direct-current discharge with dissociation yield high to bombard, the atomic deposition of larger particles can be caused in substrate, the film surface of out-of-flatness is made it have.Therefore, DC arc discharge of first nesa coating 180 using plating rate more than 1.5 nm/s (nm/sec) is deposited and formed, and its surface roughness is between 3 nanometers to 20 nanometers, and crystallite dimension is between 20 nanometers to 30 nanometers；And DC arc discharge of second nesa coating 190 using plating rate more than 2 nm/s (nm/sec) is deposited and formed, surface roughness is between 3 nanometers to 20 nanometers, and crystallite dimension is between 20 nanometers to 30 nanometers.In the present invention, the first nesa coating 180 and the second nesa coating 190 have roughened surface, can increase the utilization rate of incident light, are used to improve photocurrent characteristics.
First electrode 160 is configured on the first nesa coating 180, and second electrode 170 is configured on the second nesa coating 190, is used to take out the efficiency of electric energy and lifting opto-electronic conversion.Wherein, the material of first electrode 160 and second electrode 170 can select nickel, gold, silver, titanium, copper, palladium and aluminium.In a preferred embodiment, the material selection silver of first electrode 160 and second electrode 170.In the present embodiment, its thickness is between 100 nanometers to 900 nanometers.
The electrode line width of the first electrode 160 and the second electrode 170 is between 100 microns to 2000 microns.In figure, although two first electrodes 160 are only shown, with two second electrodes 170, but when implementing, however it is not limited to two, preferably, the first electrode 160 has the electrode wires of at least more than two with the second electrode 170, and the quantity of electrode wires is between 2 to 20.When the first electrode 160 is smaller with the electrode line width of the second electrode 170, the quantity of electrode wires is more；Conversely, when the electrode line width of the first electrode 160 and the second electrode 170 is bigger, the quantity of electrode wires is fewer.Whereby, the transparent open area of light do not covered by the first electrode 160 and the second electrode 170 at least has more than 95%.
The first electrode 160 is that can select simple metal and metallic compound with the material of the second electrode 170.Metal can include gold, silver, copper, nickel, aluminium and its alloy, and preparation method can be selected from the preparation of any one of vapour deposition method, sputtering method, galvanoplastic, electric arc plasma-based sedimentation, wet chemical and print process.Between 100 nanometers to 900 nanometers, resistance value is between the Ω of 0.1 Ω to 5 for the thickness of first electrode 160 and second electrode 170.It is preferred that the material of first electrode 160 and second electrode 170 is silver.
Current nesa coating will be deposited on silicon substrate and there is certain difficulty, mainly there is following reason:(1) silicon has different crystal structures from nesa coating, and lattice parameter difference is more.(2) the thermal coefficient of expansion difference of the two is larger.On a silicon substrate during growth nesa coating, big lattice mismatch and thermal mismatching can cause that easily generation mismatch misplaces and defect in film.Therefore one layer of undoped nesa coating is added as cushion with the nesa coating intermediate demand of doping in silicon substrate, it is possible to resolve lattice mismatch and thermal mismatch problem.
Referring now to Fig. 3, during it is shown as according to the second embodiment of the present invention, a kind of disclosed structure of silicon substrate heterojunction solar cell 100, it is included：One substrate 110；Semi-conductor layer 130；One first nesa coating 180；One first electrode 160；One second nesa coating 190；And a second electrode 170.
The second embodiment is substantially similar to first embodiment, and similarity is repeated no more.The second embodiment is with the Main Differences of first embodiment：First nesa coating 180 is made up of two layers of unlike material respectively, the nesa coating 182 for having doping comprising a undoped nesa coating 181 and.Second nesa coating 190 is made up of two layers of material respectively, the nesa coating 192 for having doping comprising a undoped nesa coating 191 and.
It is noted that undoped nesa coating 181 is disposed between the nesa coating 182 that this has doping and the semiconductor layer 130；Undoped nesa coating 191 is disposed between the nesa coating 192 that this has doping and base version 110.
It is noted that the refractive index of first nesa coating 180 is between 1.90 to 1.94, thickness can obtain relatively good antireflection effect between 50nm to 90nm.Between 1.90 to 1.94, thickness can obtain relatively good antireflection effect to the refractive index of second nesa coating 190 between 50nm to 90nm.Wherein, the thickness of undoped nesa coating 181 and undoped nesa coating 191 is between 10 to 30 nanometers.
The making material for having the nesa coating of doping can select impure indium oxide, impure tin oxide and impure zinc oxide.For example, but not limiting, the zinc oxide (ZnO of adulterated al:Al), zinc oxide (ZnO of doped gallium:Ga), zinc oxide (ZnO of doping boron:B), indium oxide (In of doping zinc2O3:Zn), indium oxide (In of doping boron2O3:B), indium oxide (In of doping hydrogen2O3:H) or its composition.The making material of undoped nesa coating can select indium oxide, tin oxide, zinc oxide.
Referring now to Fig. 4, during according to the third embodiment of the invention it be shown as, a kind of disclosed heterojunction solar cell 100, it is included：One substrate 110；One first essential amorphous silicon layer 120；One first semiconductor layer 130；One first nesa coating 180；One second intrinsic amorphous silicon layer 140；One second semiconductor layer 150；And one second nesa coating 190；And a second electrode 170.
The 3rd embodiment is substantially similar to first embodiment, and its Main Differences is that the heterojunction solar cell 100 also includes：One first essential amorphous silicon layer 120；One second intrinsic amorphous silicon layer 140 and one second semiconductor layer 150.Also it is, between the substrate 110 and first semiconductor layer 130, also including one first essential amorphous silicon layer 120.Between the substrate 110 and second nesa coating 190, also sequentially include one second intrinsic amorphous silicon layer 140；One second semiconductor layer 150.Also it is, between the substrate 110 and second semiconductor layer 150, including second intrinsic amorphous silicon layer 140.
The substrate 110 of the second embodiment, first nesa coating 180 and second nesa coating 190 are same as the substrate 110 of the first embodiment, first nesa coating 180 and second nesa coating 190, and first semiconductor layer 130 of the second embodiment is same as the semiconductor layer 130 of the first embodiment.That is, feature is same as taking off described in first embodiment, therefore will not be repeated here.
First essential amorphous silicon layer 120 is configured in the first roughened surface 111 of the substrate 110, is arranged between the substrate 110 and first semiconductor layer 130, and its hydrogen content is between 3% to 10%.Second intrinsic amorphous silicon layer 140 is configured in the second roughened surface 112 of the substrate 110, it is relative to the another side on the substrate 110 with respect to the first essential amorphous silicon layer 120, especially it is disposed between the substrate 110 and second semiconductor layer 150, its hydrogen content is between 3% to 10%.
Wherein, the making material of the first essential intrinsic amorphous silicon of amorphous silicon layer 120 and second layer 140 can select one of non-crystalline silicon, amorphous silicon germanium, nanocrystal silicon, microcrystal silicon, crystallite SiGe, polysilicon and polycrystalline silicon germanium.Additionally, the first essential intrinsic amorphous silicon of amorphous silicon layer 120 and second layer 140 may be used to form quantum confinement effect, so as to improving electrical characteristics, to increase absorbable incident optical energy spectral limit.
The first essential intrinsic amorphous silicon of amorphous silicon layer 120 and second layer 140 can select plasma enhanced type chemical formula vapour deposition and prepare (Plasma-enhanced chemical vapor deposition, PECVD), hot filament CVD (Hot-wire chemical vapor deposition, HW-CVD) or superfrequency plasma enhanced type chemical formula vapour deposition（Very high frequency-plasma enhance chemical vapor deposition,
VHF-PECVD）Prepare as main preparation method, and be passed through silicon compound（Silicide）Gas such as silane（silane, SH4）And mix hydrogen（Hydrogen, H）, argon gas（Argon, Ar）Deng gas as preparing gas.In presently preferred embodiments of the present invention, the thickness of the first essential intrinsic amorphous silicon of amorphous silicon layer 120 and second layer 140 is between 5 nanometers to 20 nanometers, and hydrogen content is between 3% to 7%.It may be noted that the difference of hydrogen content will influence light transfer characteristic.Additionally, the first essential intrinsic amorphous silicon of amorphous silicon layer 120 and second layer 140 also may be used to fill up the defect occurred at p type semiconductor layer 130 and the junction of substrate 110 or at n type semiconductor layer 150 and the junction of substrate 110, to increase conversion efficiency.
In this second embodiment, the electric conductivity of first semiconductor layer 130 is then P-type non-crystalline silicon semiconductor layer, is configured on the substrate 110 with N-type semiconduction monocrystalline silicon, to form a PN contact structures.
Therefore, second semiconductor layer 150 is n type semiconductor layer, is configured on second intrinsic amorphous silicon layer 140.The doping concentration of second semiconductor layer 150 is 1018To 1020Between atoms/cm, and its oxygen content is between 5 × 1018To 1 × 1017Between atoms/cm.Wherein, second semiconductor layer 150 refers to that the impurity added in this material can produce unnecessary electronics, and the semiconductor of most carriers is constituted with electronics.For example, for silicon and germanium semiconductor, if the impurity of 5 valency atoms is mixed in its extrinsic semiconductor, that is, forming unnecessary electronics.Wherein, electron stream is operated based on electronics.
The doping way of second semiconductor layer 150 it is optional for gas doping heat, excimer laser annealing, solid phase crystallization, diffusion method or ion implantation as main preparation method.In one embodiment, second semiconductor layer 150 is selected from one of non-crystalline silicon, amorphous silicon germanium, noncrystalline silicon carbide and nanocrystal silicon.
Fig. 5 is refer to, during it is shown as according to the fourth embodiment of the invention.The fourth embodiment is substantially similar to 3rd embodiment, and similarity is repeated no more.The 3rd embodiment is with the Main Differences of second embodiment：First nesa coating 180 is made up of two layers of unlike material respectively, the nesa coating 182 for having doping comprising a undoped nesa coating 181 and.Second nesa coating 190 is made up of two layers of material respectively, the nesa coating 192 for having doping comprising a undoped nesa coating 191 and.
It is noted that undoped nesa coating 181 is disposed between the nesa coating 182 that this has doping and first semiconductor layer 130；Undoped nesa coating 191 is disposed between the nesa coating 192 that this has doping and second semiconductor layer 150.
It is noted that the refractive index of first nesa coating 180 is between 1.90 to 1.94, thickness can obtain relatively good antireflection effect between 50nm to 90nm.Between 1.90 to 1.94, thickness can obtain relatively good antireflection effect to the refractive index of second nesa coating 190 between 50nm to 90nm.Wherein, the thickness of undoped nesa coating 181 and undoped nesa coating 191 is between 10 to 30 nanometers.
The making material for having the nesa coating of doping can select impure indium oxide, impure tin oxide and impure zinc oxide.For example, but not limiting, the zinc oxide (ZnO of adulterated al:Al), zinc oxide (ZnO of doped gallium:Ga), zinc oxide (ZnO of doping boron:B), indium oxide (In of doping zinc2O3:Zn), indium oxide (In of doping boron2O3:B), indium oxide (In of doping hydrogen2O3:H) or its composition.The making material of undoped nesa coating can select indium oxide, tin oxide, zinc oxide.
Should be noted, the configuration of the first nesa coating 180 and the second nesa coating 190 also may be used to fill up the defect occurred at the first semiconductor layer 130, the second semiconductor layer 150 and first electrode 160, the junction of second electrode 170, and translucency and excellent photoelectric characteristic by the first nesa coating 180 and the second nesa coating 190.
The roughened surface that substrate of the invention 110 has is used to increase the scattered power of incident light, by the scattered power for increasing incident light, can increase the efficiency that light mends limit (light-trapping), improves electrical characteristics.First nesa coating 180 and the second nesa coating 190 also have roughened surface, and its function is same with the roughened surface function phase that substrate 110 has.
It may be noted that when substrate is N-type silicon substrate, then irradiation face is p type semiconductor layer, and n type semiconductor layer and the second intrinsic amorphous silicon layer can then form the effect of dorsad surface field (Back Surface Field, BSF).Conversely, when substrate is P-type silicon substrate, then irradiation face is n type semiconductor layer, and p type semiconductor layer and the first essential amorphous silicon layer can then form the effect of dorsad surface field.
The preparation of silicon substrate heterojunction solar cell 100 to illustrate the invention, the preparation flow of disclosed silicon substrate heterojunction solar cell 100 is comprised the steps of：
Step 210 is：Form a silicon substrate PN contact structures, with two apparent surfaces, wherein silicon substrate PN contact structures are made up of a p type semiconductor layer with a n type semiconductor layer, and the p type semiconductor layer energy gap be different from the n type semiconductor layer energy gap；
Step 220 is：One first nesa coating is deposited in a surface of the PN contact structures, its DC arc discharge using plating rate more than 1.5 nm/s is deposited and formed；
Step 230 is：One second nesa coating is deposited in the PN contact structures and relative to another surface of the first electrode, its DC arc discharge using plating rate more than 1.5 nm/s is deposited and formed；And
Step 240 is：A first electrode is formed on first nesa coating and one second electrode of formation is on second nesa coating, the electric current for taking out silicon substrate PN contact structures.
In step 210, because of the pollution such as easy residual particulates in the surface of substrate 110, organic matter, metal residue, compound, so must first by substrate 110 through over cleaning with clean surface.In addition, the purpose for etching substrate 110 is to form it into one first roughened surface 111 and one second roughened surface 112, is used to increase the scattered power of incident light, by the scattered power for increasing incident light, the efficiency that light mends limit (light-trapping) can be increased, electrical characteristics are improved.Wherein, it is used to be formed the etching solution of the roughened surface of substrate 110 for alkaline solution, it is mainly by NaOH (0.1~8wt%)+isopropanol (IPA)
(<1wt%) or KOH (3~6%)+isopropanol (IPA) (<1wt%) it is formulated, the etching solution is made with (100) facet etch speed difference by (111) face to substrate 110.It may be noted that etching solution also can be by acid solution HF and HNO3It is formulated, wherein HNO3Divided by HF ratio between 10 to 30.
Silicon substrate PN contact structures are made up of a p type semiconductor layer with a n type semiconductor layer.
For example, in the first embodiment, the electric conductivity of the semiconductor layer 130 is then P-type non-crystalline silicon semiconductor layer, is configured on the substrate 110 with N-type semiconduction monocrystalline silicon, to form a PN contact structures.
For example, in this second embodiment, the first essential amorphous silicon layer 120 is configured in the first roughened surface 111, is arranged between the substrate 110 and first semiconductor layer 130, and its hydrogen content is between 3% to 10%.The substrate 110 forms PN contact structures with first semiconductor layer 130.Second intrinsic amorphous silicon layer 140 is configured in the second roughened surface 112, is arranged between the substrate 110 and second semiconductor layer 150, and its hydrogen content is between 3% to 10%.
The preparation of the first essential amorphous silicon layer 120, the second intrinsic amorphous silicon layer 140, p type semiconductor layer and n type semiconductor layer prepares (Plasma-enhanced chemical vapor deposition by plasma enhanced type chemical formula vapour deposition, PECVD), hot filament CVD (Hot-wire chemical vapor deposition, HW-CVD) and superfrequency plasma enhanced type chemical formula vapour deposition（Very high frequency-plasma enhance chemical vapor deposition, VHF-PECVD）One of.
In above-mentioned chemical formula gas-phase deposition system, at least it is passed through hydrogen and silane gas, the the first essential intrinsic amorphous silicon of amorphous silicon layer 120 and second layer 140 is set to be deposited in the first roughened surface 111 and in the second roughened surface 112, and by the hydrogen flowing quantity and the ratio of silane gas flow being passed through between 1 times to 100 times, make first 140 its hydrogen content of the essential intrinsic amorphous silicon of amorphous silicon layer 120 and second layer between 3% to 10%.
The preparation of p type semiconductor layer is oxygen content between 5 × 1018To 1 × 1017Between atoms/cm, it selects plasma enhanced type chemical formula vapour deposition preparation, hot filament CVD or the vapour deposition of superfrequency plasma enhanced type chemical formula to prepare as main preparation method, and by being passed through silicon compound（Silicide）Gas such as silane（silane, SH4）And mix hydrogen（Hydrogen, H）, argon gas（Argon, Ar）Deng gas as preparing gas.Such as：Collocation is mixed with silane gas with hydrogen；Silane gas, hydrogen mix with argon gas；Silane gas, Germane gas mix with hydrogen；Silane gas, Germane gas, hydrogen mix any one of constituted group with argon gas and prepare completion.By silane and hydrogen mixing ratio and the gas being passed through is changed, p type semiconductor layer 130 can be made to be one of non-crystalline silicon, amorphous silicon germanium, noncrystalline silicon carbide and nanocrystal silicon.In the embodiment of the present invention, the doping concentration of p type semiconductor layer is 1018To 1020Between atoms/cm.
The preparation of n type semiconductor layer is oxygen content between 5 × 1018To 1 × 1017Between atoms/cm, it selects plasma enhanced type chemical formula vapour deposition preparation, hot filament CVD or the vapour deposition of superfrequency plasma enhanced type chemical formula to prepare as main preparation method, and by being passed through silicon compound（Silicide）Gas such as silane（silane, SH4）And mix hydrogen（Hydrogen, H）, argon gas（Argon, Ar）Deng gas as preparing gas.Such as：Collocation is mixed with silane gas with hydrogen；Silane gas, hydrogen mix with argon gas；Silane gas, Germane gas mix with hydrogen；Silane gas, Germane gas, hydrogen mix any one of constituted group with argon gas and prepare completion.By silane and hydrogen mixing ratio and the gas being passed through is changed, n type semiconductor layer 150 can be made to be one of non-crystalline silicon, amorphous silicon germanium, noncrystalline silicon carbide and nanocrystal silicon.In the embodiment of the present invention, the doping concentration of n type semiconductor layer is 1018To 1020 Between atoms/cm.
In step 220 and step 230, the first nesa coating 180 and the second nesa coating 190 are respectively arranged on first semiconductor layer 130 and second semiconductor layer 150.Wherein, the preparation method of the first nesa coating 180 and the second nesa coating 190 constitutes any one of group and prepares selected from vapour deposition method, sputtering method, galvanoplastic, wet chemical, chemical vapour deposition technique, print process and DC arc discharge sedimentation.
But in order to obtain a preferably surface roughness, the first nesa coating 180 is formed with the second nesa coating 190 with DC arc discharge sedimentation, must have the electrically conducting transparent unit of rough grain structure by then need not being again etched step.
It may be noted that of the invention being technically characterized in that deposit first nesa coating 180 and second nesa coating 190 using DC arc discharge, its plating rate is more than 1.5 nm/s, and preferably plating rate degree is between the nm/s of 1.6 nm/s to 5；And preparation temperature is less than 200 DEG C, preferably preparation temperature is between 50 DEG C to 150 DEG C.Nesa coating has special function using low temperature preparation, is also the effect that heating anneal will not be produced to the previous film for preparing.
It is noted that the refractive index of first nesa coating 180 is between 1.90 to 1.94, thickness can obtain relatively good antireflection effect between 50nm to 90nm.Between 1.90 to 1.94, thickness can obtain relatively good antireflection effect to the refractive index of second nesa coating 190 between 50nm to 90nm.
It is preferred that the first nesa coating 180 is made up of two layers of unlike material respectively, there is the nesa coating 182 of doping comprising a undoped nesa coating 181 and one.Second nesa coating 190 is made up of two layers of material respectively, the nesa coating 192 for having doping comprising a undoped nesa coating 191 and.Wherein, the thickness of undoped nesa coating 181 and undoped nesa coating 191 is between 10 to 30 nanometers.Wherein, undoped nesa coating 181 and the volume thickness of undoped nesa coating 191 are between 10 to 30 nanometers.
Step 240, first electrode 160 and second electrode 170 constitute any one of group and prepare using vapour deposition method, sputtering method, chemical vapour deposition technique, galvanoplastic, wet chemical, print process and cathode anode electric arc direct-current discharge sedimentation, and the material of first electrode 160 and second electrode 170 can select nickel, gold, silver, titanium, copper, palladium and aluminium.Between 100 nanometers to 900 nanometers, resistance value is between the Ω of 0.1 Ω to 5 for the thickness of first electrode 160 and second electrode 170.It is preferred that the material of first electrode 160 and second electrode 170 is silver.It is noted that different first electrodes 160 and the preparation method of second electrode 170 can also influence the quality of its photoelectric characteristic having.
In embodiments of the invention, DC arc discharge sedimentation is used to prepare zinc oxide as the first nesa coating 180 and the second nesa coating 190, and coordinate the essential amorphous silicon layers 120 of different first, p type semiconductor layer 130, the second intrinsic amorphous silicon layer 140 and n type semiconductor layer 150 preparation method can also influence silicon substrate heterojunction solar cell 100 photoelectric characteristic quality.Nesa coating has special function using low temperature preparation, is also the effect that heating anneal will not be produced to the previous film for preparing.
There can be plating rate high to reach under low temperature, DC arc discharge sedimentation is mainly the other preparation parameters of control, comprising：Gas flow, gas pressure ratio and DC arc discharge electric current.In a preferred embodiment, the preparation parameter of the direct-current plate arc discharge deposition that the first nesa coating 180 and the second nesa coating 190 are used.Its gas flow ratio (argon gas:Oxygen) between 1:4 to 1:Between 12, and a preferably gas flow ratio is between 1:6 to 1:Between 10；Wherein, oxygen flow speed is between the sccm of 5 sccm to 30.The DC arc discharge electric current of its zinc target between 20A to 150A, and a preferably zinc target anode arc direct-current discharge electric current between 50A to 100A；Its chamber pressure is between 10-3Hold in the palm ear (torr) to 10-4Between support ear (torr).
At least one prepares gas by purification step in a preferred embodiment of the invention, and oxygen content in gas is prepared to reduce this.Oxygen content excessively will produce polyoxy vacancy in the membrane structure of deposition in preparing gas, cause the carrier mobility in solar cell to reduce, and then make decrease of power generation.The step of by purified gases are carried out, the oxygen concentration of the film grown up in the preferred embodiment is less than 5 × 1018Atoms/cm.It is noted that disclosed structure and method, are applicable not only to single unit battery, more may be implemented in modular solar cell and prepare.
Compared to traditional silicon substrate heterojunction silicon solar cell, silicon substrate heterojunction solar cell 100 proposed by the present invention has the advantage that as follows：
Using the nesa coating of low cost, it is possible to decrease production cost.
Nesa coating is not required to additionally add etching program, can shorten preparation time.
The utilization of ultraviolet light can be effectively increased, with raising efficiency.
Embodiment described above is only the preferred embodiment lifted to absolutely prove the present invention, protection scope of the present invention not limited to this.Equivalent substitute or conversion that those skilled in the art are made on the basis of the present invention, within protection scope of the present invention.Protection scope of the present invention is defined by claims.
Claims (10)
1. a kind of silicon substrate heterojunction solar cell, it is characterised in that including：
One silicon substrate PN contact structures, with two apparent surfaces, wherein silicon substrate PN contact structures are made up of a p type semiconductor layer with a n type semiconductor layer, and the p type semiconductor layer energy gap be different from the n type semiconductor layer energy gap；
One first nesa coating, is set positioned at a surface of silicon substrate PN contact structures, and its DC arc discharge using plating rate more than 1.5 nm/s is deposited and formed；
One second nesa coating, is set and is located at silicon substrate PN contact structures and relative to another surface of first electrode, and its DC arc discharge using plating rate more than 1.5 nm/s is deposited and formed；
One first electrode, is arranged on first nesa coating, the electric current for taking out silicon substrate PN contact structures；And
One second electrode, is arranged on second nesa coating, the electric current for taking out silicon substrate PN contact structures.
2. silicon substrate heterojunction solar cell according to claim 1, it is characterised in that the wherein refractive index of first nesa coating between 1.90 to 1.94, and second nesa coating refractive index between 1.90 to 1.94.
3. silicon substrate heterojunction solar cell according to claim 1, characterized in that, wherein first nesa coating is selected from zinc oxide, the zinc oxide of doped gallium, the zinc oxide of doping boron, the indium oxide of doping zinc, the indium oxide of doping boron, the indium oxide of doping hydrogen or wherein any two or more combination of adulterated al with second nesa coating.
4. silicon substrate heterojunction solar cell according to claim 1, it is characterised in that the wherein crystallite dimension of first nesa coating between 20 nanometers to 30 nanometers, and second nesa coating crystallite dimension between 20 nanometers to 30 nanometers.
5. silicon substrate heterojunction solar cell according to claim 1, it is characterized in that, the wherein surface roughness of first nesa coating between 3 nanometers to 20 nanometers, and second nesa coating surface roughness between 3 nanometers to 20 nanometers.
6. a kind of preparation method of silicon substrate heterojunction solar cell, it is characterised in that comprise the following steps：
Form a silicon substrate PN contact structures, with two apparent surfaces, wherein silicon substrate PN contact structures are made up of a p type semiconductor layer with a n type semiconductor layer, and the p type semiconductor layer energy gap be different from the n type semiconductor layer energy gap；
One first nesa coating is deposited in a surface of the PN contact structures, its DC arc discharge using plating rate more than 1.5 nm/s is deposited and formed；
One second nesa coating is deposited in the PN contact structures and relative to another surface of the first electrode, its DC arc discharge using plating rate more than 1.5 nm/s is deposited and formed；And
Formed a first electrode on first nesa coating with formed a second electrode on second nesa coating, the electric current for taking out silicon substrate PN contact structures.
7. the preparation method of silicon substrate heterojunction solar cell according to claim 6, it is characterised in that the wherein refractive index of first nesa coating between 1.90 to 1.94, and second nesa coating refractive index between 1.90 to 1.94.
8. the preparation method of silicon substrate heterojunction solar cell according to claim 6, characterized in that, wherein first nesa coating is selected from zinc oxide, the zinc oxide of doped gallium, the zinc oxide of doping boron, the indium oxide of doping zinc, the indium oxide of doping boron, the indium oxide of doping hydrogen or wherein any two or more combination of adulterated al.
9. the preparation method of silicon substrate heterojunction solar cell according to claim 6, it is characterized in that, the wherein crystallite dimension of first nesa coating between 20 nanometers to 50 nanometers, and second nesa coating crystallite dimension between 20 nanometers to 50 nanometers.
10. the preparation method of silicon substrate heterojunction solar cell according to claim 6, it is characterized in that, the wherein surface roughness of first nesa coating between 3 nanometers to 20 nanometers, and second nesa coating surface roughness between 3 nanometers to 20 nanometers.
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| EP4174958A4 (en) * | 2021-09-15 | 2023-08-02 | Zhongwei New Energy (Chengdu) Co., Ltd. | Transparent conductive oxide thin film and heterojunction solar cell |
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