FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

Time And Relative Dimension In Logic (TARDIL)

This repo provide an index of VLSI content creators and their materials

Real-time embedded variable & trace viewer

A http/https proxy using QUIC as transport layer

Experimental flows using nextpnr for Xilinx devices

tser - tiny serialization for C++

Python toolkit for quantitative finance

A curated list of insanely awesome libraries, packages and resources for Quants (Quantitative Finance)

A huge collection of VHDL/Verilog open-source IP cores scraped from the web

Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference for understanding and implementing robust clock domain crossi…

List of awesome open source hardware tools, generators, and reusable designs

RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.

Embedded Template Library

Digilent JTAG clone hardware + eeprom firmware (.bin)

Recipe for FPGA cooking

HDLBits website practices & solutions

Verilog (SystemVerilog) coding style

The C++ Core Guidelines are a set of tried-and-true guidelines, rules, and best practices about coding in C++

UVM Book Examples - A Practical Guide to Adopting the Universal Verification Methodology (UVM) Second Edition

Port Knocking for Windows

FPGA Logic Analyzer and GUI

HDL code for a DDS (direct digital synthesizer) with AXI stream interface

DPDK based packet generator

A self-contained online book containing a library of FPGA design modules and related coding/design guides.

Monotone, 8×8px fill patterns

Pcap editing and replay tools for *NIX and Windows - Users please download source from

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

All CPU and MCU documentation in one place